OpenOCD
x86_32_common.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Copyright(c) 2013-2016 Intel Corporation.
5  *
6  * Adrian Burns (adrian.burns@intel.com)
7  * Thomas Faust (thomas.faust@intel.com)
8  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
9  * Julien Carreno (julien.carreno@intel.com)
10  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
11  *
12  * Contact Information:
13  * Intel Corporation
14  */
15 
16 /*
17  * @file
18  * This is the interface to the x86 32 bit memory and breakpoint operations.
19  */
20 
21 #ifndef OPENOCD_TARGET_X86_32_COMMON_H
22 #define OPENOCD_TARGET_X86_32_COMMON_H
23 
24 #include <jtag/jtag.h>
25 #include <helper/command.h>
26 #include <helper/types.h>
27 
28 extern const struct command_registration x86_32_command_handlers[];
29 
30 /* for memory access */
31 #define BYTE 1
32 #define WORD 2
33 #define DWORD 4
34 
35 #define EFLAGS_TF ((uint32_t)0x00000100) /* Trap Flag */
36 #define EFLAGS_IF ((uint32_t)0x00000200) /* Interrupt Flag */
37 #define EFLAGS_RF ((uint32_t)0x00010000) /* Resume Flag */
38 #define EFLAGS_VM86 ((uint32_t)0x00020000) /* Virtual 8086 Mode */
39 
40 #define CSAR_DPL ((uint32_t)0x00006000)
41 #define CSAR_D ((uint32_t)0x00400000)
42 #define SSAR_DPL ((uint32_t)0x00006000)
43 
44 #define CR0_PE ((uint32_t)0x00000001) /* Protected Mode Enable */
45 #define CR0_NW ((uint32_t)0x20000000) /* Non Write-Through */
46 #define CR0_CD ((uint32_t)0x40000000) /* Cache Disable */
47 #define CR0_PG ((uint32_t)0x80000000) /* Paging Enable */
48 
49 /* TODO - move back to PM specific file */
50 #define PM_DR6 ((uint32_t)0xFFFF0FF0)
51 
52 #define DR6_BRKDETECT_0 ((uint32_t)0x00000001) /* B0 through B3 */
53 #define DR6_BRKDETECT_1 ((uint32_t)0x00000002) /* breakpoint condition detected */
54 #define DR6_BRKDETECT_2 ((uint32_t)0x00000004)
55 #define DR6_BRKDETECT_3 ((uint32_t)0x00000008)
56 
57 enum {
58  /* general purpose registers */
59  EAX = 0,
60  ECX,
61  EDX,
62  EBX,
63  ESP,
64  EBP,
65  ESI,
66  EDI,
67  /* instruction pointer & flags */
68  EIP,
70 
71  /* segment registers */
72  CS,
73  SS,
74  DS,
75  ES,
76  FS,
77  GS,
78 
79  /* floating point unit registers */
80  ST0,
81  ST1,
82  ST2,
83  ST3,
84  ST4,
85  ST5,
86  ST6,
87  ST7,
95  FOP,
96 
97  /* control registers */
98  CR0,
99  CR2,
102 
103  /* debug registers */
110 
111  /* descriptor tables */
118  TR,
123 
124  /* segment registers */
146 
147  /* PM control reg */
149 };
150 
151 #define X86_32_COMMON_MAGIC 0x86328632U
152 
153 enum {
154  /* memory read/write */
155  MEMRDB32 = 0,
167  /* IO read/write */
180  /* lakemont1 core shadow ram access opcodes */
185 };
186 
189  LMT3_5
190 };
191 
193  uint8_t orig_byte;
194  uint32_t swbp_unique_id;
195  uint32_t physaddr;
197 };
198 
199 /* TODO - probemode specific - consider removing */
200 #define NUM_PM_REGS 18 /* regs used in save/restore */
201 
203  unsigned int common_magic;
204 
205  void *arch_info;
207  struct reg_cache *cache;
209  uint32_t stored_pc;
211  int flush;
212 
213  /* pm_regs are for probemode save/restore state */
214  uint32_t pm_regs[NUM_PM_REGS];
215 
216  /* working area for fastdata access */
218 
222 
223  /* core probemode implementation dependent functions */
224  uint8_t (*get_num_user_regs)(struct target *t);
225  bool (*is_paging_enabled)(struct target *t);
226  int (*disable_paging)(struct target *t);
227  int (*enable_paging)(struct target *t);
228  bool (*sw_bpts_supported)(struct target *t);
229  int (*transaction_status)(struct target *t);
230  int (*submit_instruction)(struct target *t, int num);
231  int (*read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache);
232  int (*write_hw_reg)(struct target *t, int reg,
233  uint32_t regval, uint8_t cache);
234 
235  /* register cache to processor synchronization */
236  int (*read_hw_reg_to_cache)(struct target *target, int num);
237  int (*write_hw_reg_from_cache)(struct target *target, int num);
238 };
239 
240 static inline struct x86_32_common *
242 {
243  return target->arch_info;
244 }
245 bool check_not_halted(const struct target *t);
246 
247 /* breakpoint defines */
248 #define MAX_DEBUG_REGS 4
249 #define SW_BP_OPCODE 0xf1
250 #define MAX_SW_BPTS 20
251 
253  int used;
254  uint32_t bp_value;
255 };
256 
257 #define DR7_G_ENABLE_SHIFT 1
258 #define DR7_ENABLE_SIZE 2 /* 2 bits per debug reg */
259 #define DR7_RW_SHIFT 16
260 #define DR7_LENGTH_SHIFT 18
261 #define DR7_RW_LEN_SIZE 4
262 #define DR7_BP_EXECUTE 0 /* 00 - only on instruction execution*/
263 #define DR7_BP_WRITE 1 /* 01 - only on data writes */
264 /*#define DR7_RW_IORW 2 UNSUPPORTED 10 - an I/O read and I/O write */
265 #define DR7_BP_READWRITE 3 /* on data read or data write */
266 #define DR7_BP_LENGTH_1 0 /* 00 - 1 byte length */
267 #define DR7_BP_LENGTH_2 1 /* 01 - 2 byte length */
268 #define DR7_BP_LENGTH_4 3 /* 11 - 4 byte length */
269 
270 #define DR7_GLOBAL_ENABLE(val, regnum) \
271  (val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
272 
273 #define DR7_GLOBAL_DISABLE(val, regnum) \
274  (val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
275 
276 #define DR7_BP_FREE(val, regnum) \
277  ((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
278 
279 #define DR7_RESET_RWLEN_BITS(val, regnum) \
280  (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
281 
282 #define DR7_SET_EXE(val, regnum) \
283  (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
284 
285 #define DR7_SET_WRITE(val, regnum) \
286  (val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
287 
288 #define DR7_SET_ACCESS(val, regnum) \
289  (val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
290 
291 #define DR7_SET_LENGTH(val, regnum, len) \
292  (val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
293  (len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
294  (DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
295 
296 /* public interface */
297 int x86_32_get_gdb_reg_list(struct target *t,
298  struct reg **reg_list[], int *reg_list_size,
299  enum target_register_class reg_class);
301  struct x86_32_common *x86_32);
302 int x86_32_common_mmu(struct target *t, int *enabled);
303 int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical);
304 int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
305  uint32_t size, uint32_t count, uint8_t *buffer);
306 int x86_32_common_write_phys_mem(struct target *t, target_addr_t phys_address,
307  uint32_t size, uint32_t count, const uint8_t *buffer);
309  uint32_t size, uint32_t count, uint8_t *buf);
311  uint32_t size, uint32_t count, const uint8_t *buf);
312 int x86_32_common_read_io(struct target *t, uint32_t addr,
313  uint32_t size, uint8_t *buf);
314 int x86_32_common_write_io(struct target *t, uint32_t addr,
315  uint32_t size, const uint8_t *buf);
316 int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
317 int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
318 int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
319 int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
321 
322 #endif /* OPENOCD_TARGET_X86_32_COMMON_H */
The JTAG interface can be implemented with a software or hardware fifo.
uint32_t addr
Definition: nuttx.c:65
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
Definition: jtag.h:100
Definition: register.h:111
struct swbp_mem_patch * next
uint32_t swbp_unique_id
uint32_t physaddr
Definition: target.h:120
void * arch_info
Definition: target.h:169
int(* read_hw_reg_to_cache)(struct target *target, int num)
enum x86_core_type core_type
struct swbp_mem_patch * swbbp_mem_patch_list
bool(* sw_bpts_supported)(struct target *t)
int(* disable_paging)(struct target *t)
struct x86_32_dbg_reg * hw_break_list
uint32_t stored_pc
int(* write_hw_reg_from_cache)(struct target *target, int num)
int(* read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache)
bool(* is_paging_enabled)(struct target *t)
uint8_t(* get_num_user_regs)(struct target *t)
int(* write_hw_reg)(struct target *t, int reg, uint32_t regval, uint8_t cache)
struct reg_cache * cache
int forced_halt_for_reset
int(* enable_paging)(struct target *t)
uint32_t pm_regs[NUM_PM_REGS]
int(* submit_instruction)(struct target *t, int num)
struct jtag_tap * curr_tap
struct working_area * fast_data_area
unsigned int common_magic
int(* transaction_status)(struct target *t)
uint32_t bp_value
target_register_class
Definition: target.h:114
uint64_t target_addr_t
Definition: types.h:335
uint8_t count[4]
Definition: vdebug.c:22
@ MEMRDH32
@ MEMRDB16
@ MEMWRB32
@ SRAM2PDR
@ IORDB32
@ IORDW32
@ MEMWRH16
@ IOWRB32
@ IOWRB16
@ MEMRDH16
@ MEMWRH32
@ SRAMACCESS
@ IOWRH16
@ IORDW16
@ PDR2SRAM
@ MEMRDB32
@ IORDH16
@ MEMWRW16
@ IOWRH32
@ IOWRW32
@ MEMRDW16
@ WBINVD
@ MEMWRB16
@ IORDB16
@ MEMRDW32
@ IOWRW16
@ MEMWRW32
@ IORDH32
const struct command_registration x86_32_command_handlers[]
int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp)
int x86_32_common_read_io(struct target *t, uint32_t addr, uint32_t size, uint8_t *buf)
int x86_32_common_read_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, uint8_t *buf)
int x86_32_common_init_arch_info(struct target *target, struct x86_32_common *x86_32)
Definition: x86_32_common.c:80
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical)
int x86_32_common_write_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, const uint8_t *buf)
int x86_32_get_gdb_reg_list(struct target *t, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: x86_32_common.c:57
#define NUM_PM_REGS
int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer)
int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp)
int x86_32_common_mmu(struct target *t, int *enabled)
Definition: x86_32_common.c:99
bool check_not_halted(const struct target *t)
Definition: lakemont.c:206
static struct x86_32_common * target_to_x86_32(struct target *target)
x86_core_type
@ LMT1
@ LMT3_5
void x86_32_common_reset_breakpoints_watchpoints(struct target *t)
int x86_32_common_write_phys_mem(struct target *t, target_addr_t phys_address, uint32_t size, uint32_t count, const uint8_t *buffer)
int x86_32_common_write_io(struct target *t, uint32_t addr, uint32_t size, const uint8_t *buf)
@ GDTB
@ ST7
Definition: x86_32_common.h:87
@ GDTL
@ EFLAGS
Definition: x86_32_common.h:69
@ GSAR
@ DSB
@ SSB
@ FSTAT
Definition: x86_32_common.h:89
@ FOOFF
Definition: x86_32_common.h:94
@ FTAG
Definition: x86_32_common.h:90
@ EDI
Definition: x86_32_common.h:66
@ TR
@ ESP
Definition: x86_32_common.h:63
@ GDTAR
@ LDTL
@ CSAR
@ CR2
Definition: x86_32_common.h:99
@ FOSEG
Definition: x86_32_common.h:93
@ ST2
Definition: x86_32_common.h:82
@ ECX
Definition: x86_32_common.h:60
@ LDTR
@ FCTRL
Definition: x86_32_common.h:88
@ GSL
@ DR1
@ CR4
@ DR2
@ CR0
Definition: x86_32_common.h:98
@ ST1
Definition: x86_32_common.h:81
@ ESI
Definition: x86_32_common.h:65
@ DR6
@ GSB
@ FSAR
@ EAX
Definition: x86_32_common.h:59
@ FS
Definition: x86_32_common.h:76
@ ES
Definition: x86_32_common.h:75
@ FISEG
Definition: x86_32_common.h:91
@ ESL
@ ST5
Definition: x86_32_common.h:85
@ LDTB
@ CS
Definition: x86_32_common.h:72
@ DR0
@ IDTAR
@ EBX
Definition: x86_32_common.h:62
@ CSB
@ FIOFF
Definition: x86_32_common.h:92
@ TSSAR
@ SSAR
@ EIP
Definition: x86_32_common.h:68
@ EDX
Definition: x86_32_common.h:61
@ GS
Definition: x86_32_common.h:77
@ CSL
@ DSL
@ IDTB
@ ST4
Definition: x86_32_common.h:84
@ ST6
Definition: x86_32_common.h:86
@ FSL
@ SSL
@ DS
Definition: x86_32_common.h:74
@ IDTL
@ FSB
@ DSAR
@ TSSL
@ FOP
Definition: x86_32_common.h:95
@ SS
Definition: x86_32_common.h:73
@ DR7
@ CR3
@ EBP
Definition: x86_32_common.h:64
@ TSSB
@ ST3
Definition: x86_32_common.h:83
@ DR3
@ LDTAR
@ ESAR
@ ST0
Definition: x86_32_common.h:80
@ PMCR
@ ESB
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp)