OpenOCD
stmqspi.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2016 - 2019 by Andreas Bolsch *
5  * andreas.bolsch@mni.thm.de *
6  * *
7  * Copyright (C) 2010 by Antonio Borneo *
8  * borneo.antonio@gmail.com *
9  ***************************************************************************/
10 
11 /* STM QuadSPI (QSPI) and OctoSPI (OCTOSPI) controller are SPI bus controllers
12  * specifically designed for SPI memories.
13  * Two working modes are available:
14  * - indirect mode: the SPI is controlled by SW. Any custom commands can be sent
15  * on the bus.
16  * - memory mapped mode: the SPI is under QSPI/OCTOSPI control. Memory content
17  * is directly accessible in CPU memory space. CPU can read and execute from
18  * memory (but not write to) */
19 
20 /* ATTENTION:
21  * To have flash mapped in CPU memory space, the QSPI/OCTOSPI controller
22  * has to be in "memory mapped mode". This requires following constraints:
23  * 1) The command "reset init" has to initialize QSPI/OCTOSPI controller and put
24  * it in memory mapped mode;
25  * 2) every command in this file has to return to prompt in memory mapped mode. */
26 
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30 
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <helper/bits.h>
34 #include <helper/time_support.h>
35 #include <target/algorithm.h>
36 #include <target/armv7m.h>
37 #include <target/image.h>
38 #include "stmqspi.h"
39 #include "sfdp.h"
40 
41 /* deprecated */
42 #undef SPIFLASH_READ
43 #undef SPIFLASH_PAGE_PROGRAM
44 
45 /* saved mode settings */
46 #define QSPI_MODE (stmqspi_info->saved_ccr & \
47  (0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4))
48 
49 /* saved read mode settings but indirect read instead of memory mapped
50  * in particular, use the dummy cycle setting from this saved setting */
51 #define QSPI_CCR_READ (QSPI_READ_MODE | (stmqspi_info->saved_ccr & \
52  (0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4 | 0xFF)))
53 
54 /* QSPI_CCR for various other commands, these never use dummy cycles nor alternate bytes */
55 #define QSPI_CCR_READ_STATUS \
56  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
57  (QSPI_READ_MODE | SPIFLASH_READ_STATUS))
58 
59 #define QSPI_CCR_READ_ID \
60  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
61  (QSPI_READ_MODE | SPIFLASH_READ_ID))
62 
63 #define QSPI_CCR_READ_MID \
64  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
65  (QSPI_READ_MODE | SPIFLASH_READ_MID))
66 
67 /* always use 3-byte addresses for read SFDP */
68 #define QSPI_CCR_READ_SFDP \
69  ((QSPI_MODE & ~QSPI_DCYC_MASK & ~QSPI_ADDR4 & QSPI_NO_ALTB) | \
70  (QSPI_READ_MODE | QSPI_ADDR3 | SPIFLASH_READ_SFDP))
71 
72 #define QSPI_CCR_WRITE_ENABLE \
73  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB & QSPI_NO_DATA) | \
74  (QSPI_WRITE_MODE | SPIFLASH_WRITE_ENABLE))
75 
76 #define QSPI_CCR_SECTOR_ERASE \
77  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & QSPI_NO_DATA) | \
78  (QSPI_WRITE_MODE | stmqspi_info->dev.erase_cmd))
79 
80 #define QSPI_CCR_MASS_ERASE \
81  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB & QSPI_NO_DATA) | \
82  (QSPI_WRITE_MODE | stmqspi_info->dev.chip_erase_cmd))
83 
84 #define QSPI_CCR_PAGE_PROG \
85  ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB) | \
86  (QSPI_WRITE_MODE | stmqspi_info->dev.pprog_cmd))
87 
88 /* saved mode settings */
89 #define OCTOSPI_MODE (stmqspi_info->saved_cr & 0xCFFFFFFF)
90 
91 #define OPI_MODE ((stmqspi_info->saved_ccr & OCTOSPI_ISIZE_MASK) != 0)
92 
93 #define OCTOSPI_MODE_CCR (stmqspi_info->saved_ccr & \
94  (0xF0000000U | OCTOSPI_8LINE_MODE | OCTOSPI_ALTB_MODE | OCTOSPI_ADDR4))
95 
96 /* use saved ccr for read */
97 #define OCTOSPI_CCR_READ OCTOSPI_MODE_CCR
98 
99 /* OCTOSPI_CCR for various other commands, these never use alternate bytes *
100  * for READ_STATUS and READ_ID, 4-byte address 0 *
101  * 4 dummy cycles must sent in OPI mode when DQS is disabled. However, when *
102  * DQS is enabled, some STM32 devices need at least 6 dummy cycles for *
103  * proper operation, but otherwise the actual number has no effect! *
104  * E.g. RM0432 Rev. 7 is incorrect regarding this: L4R9 works well with 4 *
105  * dummy clocks whereas L4P5 not at all. *
106  */
107 #define OPI_DUMMY \
108  ((stmqspi_info->saved_ccr & OCTOSPI_DQSEN) ? 6U : 4U)
109 
110 #define OCTOSPI_CCR_READ_STATUS \
111  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & \
112  (OPI_MODE ? ~0U : OCTOSPI_NO_ADDR) & OCTOSPI_NO_ALTB))
113 
114 #define OCTOSPI_CCR_READ_ID \
115  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & \
116  (OPI_MODE ? ~0U : OCTOSPI_NO_ADDR) & OCTOSPI_NO_ALTB))
117 
118 #define OCTOSPI_CCR_READ_MID OCTOSPI_CCR_READ_ID
119 
120 /* 4-byte address in octo mode, else 3-byte address for read SFDP */
121 #define OCTOSPI_CCR_READ_SFDP(len) \
122  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & ~OCTOSPI_ADDR4 & OCTOSPI_NO_ALTB) | \
123  (((len) < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
124 
125 #define OCTOSPI_CCR_WRITE_ENABLE \
126  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
127 
128 #define OCTOSPI_CCR_SECTOR_ERASE \
129  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
130 
131 #define OCTOSPI_CCR_MASS_ERASE \
132  ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
133 
134 #define OCTOSPI_CCR_PAGE_PROG \
135  ((OCTOSPI_MODE_CCR & QSPI_NO_ALTB))
136 
137 #define SPI_ADSIZE (((stmqspi_info->saved_ccr >> SPI_ADSIZE_POS) & 0x3) + 1)
138 
139 #define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t)(cmd)) << 8) | (~(cmd) & 0xFFU)) : (cmd)))
140 
141 /* convert uint32_t into 4 uint8_t in little endian byte order */
142 static inline uint32_t h_to_le_32(uint32_t val)
143 {
144  uint32_t result;
145 
146  h_u32_to_le((uint8_t *)&result, val);
147  return result;
148 }
149 
150 /* Timeout in ms */
151 #define SPI_CMD_TIMEOUT (100)
152 #define SPI_PROBE_TIMEOUT (100)
153 #define SPI_MAX_TIMEOUT (2000)
154 #define SPI_MASS_ERASE_TIMEOUT (400000)
155 
156 struct sector_info {
157  uint32_t offset;
158  uint32_t size;
159  uint32_t result;
160 };
161 
163  bool probed;
164  char devname[32];
165  bool octo;
166  struct flash_device dev;
167  uint32_t io_base;
168  uint32_t saved_cr; /* in particular FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
169  uint32_t saved_ccr; /* different meaning for QUADSPI and OCTOSPI */
170  uint32_t saved_tcr; /* only for OCTOSPI */
171  uint32_t saved_ir; /* only for OCTOSPI */
172  unsigned int sfdp_dummy1; /* number of dummy bytes for SFDP read for flash1 and octo */
173  unsigned int sfdp_dummy2; /* number of dummy bytes for SFDP read for flash2 */
174 };
175 
176 static inline int octospi_cmd(struct flash_bank *bank, uint32_t mode,
177  uint32_t ccr, uint32_t ir)
178 {
179  struct target *target = bank->target;
180  const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
181  const uint32_t io_base = stmqspi_info->io_base;
182 
183  int retval = target_write_u32(target, io_base + OCTOSPI_CR,
184  OCTOSPI_MODE | mode);
185 
186  if (retval != ERROR_OK)
187  return retval;
188 
190  (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
191  ((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ?
192  (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0));
193 
194  if (retval != ERROR_OK)
195  return retval;
196 
197  retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr);
198 
199  if (retval != ERROR_OK)
200  return retval;
201 
203 }
204 
205 FLASH_BANK_COMMAND_HANDLER(stmqspi_flash_bank_command)
206 {
207  struct stmqspi_flash_bank *stmqspi_info;
208  uint32_t io_base;
209 
210  LOG_DEBUG("%s", __func__);
211 
212  if (CMD_ARGC < 7)
214 
216 
217  stmqspi_info = malloc(sizeof(struct stmqspi_flash_bank));
218  if (!stmqspi_info) {
219  LOG_ERROR("not enough memory");
220  return ERROR_FAIL;
221  }
222 
223  bank->driver_priv = stmqspi_info;
224  stmqspi_info->sfdp_dummy1 = 0;
225  stmqspi_info->sfdp_dummy2 = 0;
226  stmqspi_info->probed = false;
227  stmqspi_info->io_base = io_base;
228 
229  return ERROR_OK;
230 }
231 
232 /* Poll busy flag */
233 /* timeout in ms */
234 static int poll_busy(struct flash_bank *bank, int timeout)
235 {
236  struct target *target = bank->target;
237  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
238  uint32_t io_base = stmqspi_info->io_base;
239  long long endtime;
240 
241  endtime = timeval_ms() + timeout;
242  do {
243  uint32_t spi_sr;
244  int retval = target_read_u32(target, io_base + SPI_SR, &spi_sr);
245 
246  if (retval != ERROR_OK)
247  return retval;
248 
249  if ((spi_sr & BIT(SPI_BUSY)) == 0) {
250  /* Clear transmit finished flag */
252  } else
253  LOG_DEBUG("busy: 0x%08X", spi_sr);
254  alive_sleep(1);
255  } while (timeval_ms() < endtime);
256 
257  LOG_ERROR("Timeout while polling BUSY");
259 }
260 
261 static int stmqspi_abort(struct flash_bank *bank)
262 {
263  struct target *target = bank->target;
264  const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
265  const uint32_t io_base = stmqspi_info->io_base;
266  uint32_t cr;
267 
268  int retval = target_read_u32(target, io_base + SPI_CR, &cr);
269 
270  if (retval != ERROR_OK)
271  cr = 0;
272 
274 }
275 
276 /* Set to memory-mapped mode, e.g. after an error */
277 static int set_mm_mode(struct flash_bank *bank)
278 {
279  struct target *target = bank->target;
280  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
281  uint32_t io_base = stmqspi_info->io_base;
282  int retval;
283 
284  /* Reset Address register bits 0 and 1, see various errata sheets */
285  retval = target_write_u32(target, io_base + SPI_AR, 0x0);
286  if (retval != ERROR_OK)
287  return retval;
288 
289  /* Abort any previous operation */
290  retval = stmqspi_abort(bank);
291  if (retval != ERROR_OK)
292  return retval;
293 
294  /* Wait for busy to be cleared */
295  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
296  if (retval != ERROR_OK)
297  return retval;
298 
299  /* Finally switch to memory mapped mode */
300  if (IS_OCTOSPI) {
303  if (retval == ERROR_OK)
305  stmqspi_info->saved_ccr);
306  if (retval == ERROR_OK)
308  stmqspi_info->saved_tcr);
309  if (retval == ERROR_OK)
311  stmqspi_info->saved_ir);
312  } else {
314  stmqspi_info->saved_cr);
315  if (retval == ERROR_OK)
317  stmqspi_info->saved_ccr);
318  }
319  return retval;
320 }
321 
322 /* Read the status register of the external SPI flash chip(s). */
323 static int read_status_reg(struct flash_bank *bank, uint16_t *status)
324 {
325  struct target *target = bank->target;
326  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
327  uint32_t io_base = stmqspi_info->io_base;
328  uint8_t data;
329  int count, retval;
330 
331  /* Abort any previous operation */
332  retval = stmqspi_abort(bank);
333  if (retval != ERROR_OK)
334  return retval;
335 
336  /* Wait for busy to be cleared */
337  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
338  if (retval != ERROR_OK)
339  goto err;
340 
341  /* Read always two (for DTR mode) bytes per chip */
342  count = 2;
344  ((stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
345  if (retval != ERROR_OK)
346  goto err;
347 
348  /* Read status */
349  if (IS_OCTOSPI) {
352  if (OPI_MODE) {
353  /* Dummy address 0, only required for 8-line mode */
354  retval = target_write_u32(target, io_base + SPI_AR, 0);
355  if (retval != ERROR_OK)
356  goto err;
357  }
358  } else
360  if (retval != ERROR_OK)
361  goto err;
362 
363  *status = 0;
364 
365  /* for debugging only */
366  uint32_t dummy;
368 
369  for ( ; count > 0; --count) {
370  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
371  != BIT(SPI_FSEL_FLASH)) {
372  /* get status of flash 1 in dual mode or flash 1 only mode */
373  retval = target_read_u8(target, io_base + SPI_DR, &data);
374  if (retval != ERROR_OK)
375  goto err;
376  *status |= data;
377  }
378 
379  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
380  /* get status of flash 2 in dual mode or flash 2 only mode */
381  retval = target_read_u8(target, io_base + SPI_DR, &data);
382  if (retval != ERROR_OK)
383  goto err;
384  *status |= ((uint16_t)data) << 8;
385  }
386  }
387 
388  LOG_DEBUG("flash status regs: 0x%04" PRIx16, *status);
389 
390 err:
391  return retval;
392 }
393 
394 /* check for WIP (write in progress) bit(s) in status register(s) */
395 /* timeout in ms */
396 static int wait_till_ready(struct flash_bank *bank, int timeout)
397 {
398  uint16_t status;
399  int retval;
400  long long endtime;
401 
402  endtime = timeval_ms() + timeout;
403  do {
404  /* Read flash status register(s) */
405  retval = read_status_reg(bank, &status);
406  if (retval != ERROR_OK)
407  return retval;
408 
409  if ((status & ((SPIFLASH_BSY_BIT << 8) | SPIFLASH_BSY_BIT)) == 0)
410  return retval;
411  alive_sleep(25);
412  } while (timeval_ms() < endtime);
413 
414  LOG_ERROR("timeout");
416 }
417 
418 /* Send "write enable" command to SPI flash chip(s). */
419 static int qspi_write_enable(struct flash_bank *bank)
420 {
421  struct target *target = bank->target;
422  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
423  uint32_t io_base = stmqspi_info->io_base;
424  uint16_t status;
425  int retval;
426 
427  /* Abort any previous operation */
428  retval = stmqspi_abort(bank);
429  if (retval != ERROR_OK)
430  return retval;
431 
432  /* Wait for busy to be cleared */
433  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
434  if (retval != ERROR_OK)
435  goto err;
436 
437  /* Send write enable command */
438  if (IS_OCTOSPI) {
441  if (OPI_MODE) {
442  /* Dummy address 0, only required for 8-line mode */
443  retval = target_write_u32(target, io_base + SPI_AR, 0);
444  if (retval != ERROR_OK)
445  goto err;
446  }
447  } else
449  if (retval != ERROR_OK)
450  goto err;
451 
452 
453  /* Wait for transmit of command completed */
455  if (retval != ERROR_OK)
456  goto err;
457 
458  /* Read flash status register */
459  retval = read_status_reg(bank, &status);
460  if (retval != ERROR_OK)
461  goto err;
462 
463  /* Check write enabled for flash 1 */
464  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
465  != BIT(SPI_FSEL_FLASH))
467  LOG_ERROR("Cannot write enable flash1. Status=0x%02x",
468  status & 0xFFU);
470  }
471 
472  /* Check write enabled for flash 2 */
473  status >>= 8;
474  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0)
476  LOG_ERROR("Cannot write enable flash2. Status=0x%02x",
477  status & 0xFFU);
479  }
480 
481 err:
482  return retval;
483 }
484 
485 COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
486 {
487  struct target *target = NULL;
488  struct flash_bank *bank;
489  struct stmqspi_flash_bank *stmqspi_info;
490  struct duration bench;
491  uint32_t io_base;
492  uint16_t status;
493  unsigned int sector;
494  int retval;
495 
496  LOG_DEBUG("%s", __func__);
497 
498  if (CMD_ARGC != 1)
500 
501  retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
502  if (retval != ERROR_OK)
503  return retval;
504 
505  stmqspi_info = bank->driver_priv;
506  target = bank->target;
507 
508  if (target->state != TARGET_HALTED) {
509  LOG_ERROR("Target not halted");
511  }
512 
513  if (!(stmqspi_info->probed)) {
514  LOG_ERROR("Flash bank not probed");
516  }
517 
518  if (stmqspi_info->dev.chip_erase_cmd == 0x00) {
519  LOG_ERROR("Mass erase not available for this device");
521  }
522 
523  for (sector = 0; sector < bank->num_sectors; sector++) {
524  if (bank->sectors[sector].is_protected) {
525  LOG_ERROR("Flash sector %u protected", sector);
526  return ERROR_FLASH_PROTECTED;
527  }
528  }
529 
530  io_base = stmqspi_info->io_base;
531  duration_start(&bench);
532 
533  retval = qspi_write_enable(bank);
534  if (retval != ERROR_OK)
535  goto err;
536 
537  /* Send Mass Erase command */
538  if (IS_OCTOSPI)
540  stmqspi_info->dev.chip_erase_cmd);
541  else
542  retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_MASS_ERASE);
543  if (retval != ERROR_OK)
544  goto err;
545 
546  /* Wait for transmit of command completed */
548  if (retval != ERROR_OK)
549  goto err;
550 
551  /* Read flash status register(s) */
552  retval = read_status_reg(bank, &status);
553  if (retval != ERROR_OK)
554  goto err;
555 
556  /* Check for command in progress for flash 1 */
557  if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
558  != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
559  ((status & SPIFLASH_WE_BIT) != 0)) {
560  LOG_ERROR("Mass erase command not accepted by flash1. Status=0x%02x",
561  status & 0xFFU);
563  goto err;
564  }
565 
566  /* Check for command in progress for flash 2 */
567  status >>= 8;
568  if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
569  ((status & SPIFLASH_BSY_BIT) == 0) &&
570  ((status & SPIFLASH_WE_BIT) != 0)) {
571  LOG_ERROR("Mass erase command not accepted by flash2. Status=0x%02x",
572  status & 0xFFU);
574  goto err;
575  }
576 
577  /* Poll WIP for end of self timed Sector Erase cycle */
579 
580  duration_measure(&bench);
581  if (retval == ERROR_OK)
582  command_print(CMD, "stmqspi mass erase completed in %fs (%0.3f KiB/s)",
583  duration_elapsed(&bench),
584  duration_kbps(&bench, bank->size));
585  else
586  command_print(CMD, "stmqspi mass erase not completed even after %fs",
587  duration_elapsed(&bench));
588 
589 err:
590  /* Switch to memory mapped mode before return to prompt */
591  set_mm_mode(bank);
592 
593  return retval;
594 }
595 
596 static int log2u(uint32_t word)
597 {
598  int result;
599 
600  for (result = 0; (unsigned int) result < sizeof(uint32_t) * CHAR_BIT; result++)
601  if (word == BIT(result))
602  return result;
603 
604  return -1;
605 }
606 
607 COMMAND_HANDLER(stmqspi_handle_set)
608 {
609  struct flash_bank *bank = NULL;
610  struct target *target = NULL;
611  struct stmqspi_flash_bank *stmqspi_info = NULL;
612  struct flash_sector *sectors = NULL;
613  uint32_t io_base;
614  unsigned int index = 0, dual, fsize;
615  int retval;
616 
617  LOG_DEBUG("%s", __func__);
618 
619  /* chip_erase_cmd, sectorsize and erase_cmd are optional */
620  if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
622 
623  retval = CALL_COMMAND_HANDLER(flash_command_get_bank, index++, &bank);
624  if (retval != ERROR_OK)
625  return retval;
626 
627  target = bank->target;
628  stmqspi_info = bank->driver_priv;
629  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
630 
631  /* invalidate all flash device info */
632  if (stmqspi_info->probed)
633  free(bank->sectors);
634  bank->size = 0;
635  bank->num_sectors = 0;
636  bank->sectors = NULL;
637  stmqspi_info->sfdp_dummy1 = 0;
638  stmqspi_info->sfdp_dummy2 = 0;
639  stmqspi_info->probed = false;
640  memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
641  stmqspi_info->dev.name = "unknown";
642 
643  strncpy(stmqspi_info->devname, CMD_ARGV[index++], sizeof(stmqspi_info->devname) - 1);
644  stmqspi_info->devname[sizeof(stmqspi_info->devname) - 1] = '\0';
645 
646  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.size_in_bytes);
647  if (log2u(stmqspi_info->dev.size_in_bytes) < 8) {
648  command_print(CMD, "stmqspi: device size must be 2^n with n >= 8");
650  }
651 
652  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.pagesize);
653  if (stmqspi_info->dev.pagesize > stmqspi_info->dev.size_in_bytes ||
654  (log2u(stmqspi_info->dev.pagesize) < 0)) {
655  command_print(CMD, "stmqspi: page size must be 2^n and <= device size");
657  }
658 
659  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.read_cmd);
660  if ((stmqspi_info->dev.read_cmd != 0x03) &&
661  (stmqspi_info->dev.read_cmd != 0x13)) {
662  command_print(CMD, "stmqspi: only 0x03/0x13 READ cmd allowed");
664  }
665 
666  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.qread_cmd);
667  if ((stmqspi_info->dev.qread_cmd != 0x00) &&
668  (stmqspi_info->dev.qread_cmd != 0x0B) &&
669  (stmqspi_info->dev.qread_cmd != 0x0C) &&
670  (stmqspi_info->dev.qread_cmd != 0x3B) &&
671  (stmqspi_info->dev.qread_cmd != 0x3C) &&
672  (stmqspi_info->dev.qread_cmd != 0x6B) &&
673  (stmqspi_info->dev.qread_cmd != 0x6C) &&
674  (stmqspi_info->dev.qread_cmd != 0xBB) &&
675  (stmqspi_info->dev.qread_cmd != 0xBC) &&
676  (stmqspi_info->dev.qread_cmd != 0xEB) &&
677  (stmqspi_info->dev.qread_cmd != 0xEC) &&
678  (stmqspi_info->dev.qread_cmd != 0xEE)) {
679  command_print(CMD, "stmqspi: only 0x0B/0x0C/0x3B/0x3C/"
680  "0x6B/0x6C/0xBB/0xBC/0xEB/0xEC/0xEE QREAD allowed");
682  }
683 
684  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.pprog_cmd);
685  if ((stmqspi_info->dev.pprog_cmd != 0x02) &&
686  (stmqspi_info->dev.pprog_cmd != 0x12) &&
687  (stmqspi_info->dev.pprog_cmd != 0x32)) {
688  command_print(CMD, "stmqspi: only 0x02/0x12/0x32 PPRG cmd allowed");
690  }
691 
692  if (index < CMD_ARGC)
693  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.chip_erase_cmd);
694  else
695  stmqspi_info->dev.chip_erase_cmd = 0x00;
696 
697  if (index < CMD_ARGC) {
698  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.sectorsize);
699  if ((stmqspi_info->dev.sectorsize > stmqspi_info->dev.size_in_bytes) ||
700  (stmqspi_info->dev.sectorsize < stmqspi_info->dev.pagesize) ||
701  (log2u(stmqspi_info->dev.sectorsize) < 0)) {
702  command_print(CMD, "stmqspi: sector size must be 2^n and <= device size");
704  }
705 
706  if (index < CMD_ARGC)
707  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.erase_cmd);
708  else
710  } else {
711  /* no sector size / sector erase cmd given, treat whole bank as a single sector */
712  stmqspi_info->dev.erase_cmd = 0x00;
713  stmqspi_info->dev.sectorsize = stmqspi_info->dev.size_in_bytes;
714  }
715 
716  /* set correct size value */
717  bank->size = stmqspi_info->dev.size_in_bytes << dual;
718 
719  io_base = stmqspi_info->io_base;
720 
721  uint32_t dcr;
722  retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
723  if (retval != ERROR_OK)
724  return retval;
725  fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
726 
727  LOG_DEBUG("FSIZE = 0x%04x", fsize);
728  if (bank->size == BIT(fsize + 1))
729  LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
730  else if (bank->size == BIT(fsize + 0))
731  LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
732  else
733  LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
734 
735  /* create and fill sectors array */
736  bank->num_sectors =
737  stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
738  sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
739  if (!sectors) {
740  LOG_ERROR("not enough memory");
741  return ERROR_FAIL;
742  }
743 
744  for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
745  sectors[sector].offset = sector * (stmqspi_info->dev.sectorsize << dual);
746  sectors[sector].size = (stmqspi_info->dev.sectorsize << dual);
747  sectors[sector].is_erased = -1;
748  sectors[sector].is_protected = 0;
749  }
750 
751  bank->sectors = sectors;
752  stmqspi_info->dev.name = stmqspi_info->devname;
753  if (stmqspi_info->dev.size_in_bytes / 4096)
754  LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " KiB,"
755  " bank size = %" PRIu32 " KiB", stmqspi_info->dev.name,
756  stmqspi_info->dev.size_in_bytes / 1024,
757  (stmqspi_info->dev.size_in_bytes / 1024) << dual);
758  else
759  LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 " B,"
760  " bank size = %" PRIu32 " B", stmqspi_info->dev.name,
761  stmqspi_info->dev.size_in_bytes,
762  stmqspi_info->dev.size_in_bytes << dual);
763 
764  stmqspi_info->probed = true;
765 
766  return ERROR_OK;
767 }
768 
769 COMMAND_HANDLER(stmqspi_handle_cmd)
770 {
771  struct target *target = NULL;
772  struct flash_bank *bank;
773  struct stmqspi_flash_bank *stmqspi_info = NULL;
774  uint32_t io_base, addr;
775  uint8_t num_write, num_read, cmd_byte, data;
776  unsigned int count;
777  const int max = 21;
778  char temp[4], output[(2 + max + 256) * 3 + 8];
779  int retval;
780 
781  LOG_DEBUG("%s", __func__);
782 
783  if (CMD_ARGC < 3)
785 
786  num_write = CMD_ARGC - 2;
787  if (num_write > max) {
788  LOG_ERROR("at most %d bytes may be sent", max);
790  }
791 
792  retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
793  if (retval != ERROR_OK)
794  return retval;
795 
796  target = bank->target;
797  stmqspi_info = bank->driver_priv;
798  io_base = stmqspi_info->io_base;
799 
800  if (target->state != TARGET_HALTED) {
801  LOG_ERROR("Target not halted");
803  }
804 
805  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], num_read);
806  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);
807 
808  if (num_read == 0) {
809  /* nothing to read, then one command byte and for dual flash
810  * an *even* number of data bytes to follow */
811  if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
812  if ((num_write & 1) == 0) {
813  LOG_ERROR("number of data bytes to write must be even in dual mode");
815  }
816  }
817  } else {
818  /* read mode, one command byte and up to four following address bytes */
819  if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
820  if ((num_read & 1) != 0) {
821  LOG_ERROR("number of bytes to read must be even in dual mode");
823  }
824  }
825  if ((num_write < 1) || (num_write > 5)) {
826  LOG_ERROR("one cmd and up to four addr bytes must be send when reading");
828  }
829  }
830 
831  /* Abort any previous operation */
832  retval = stmqspi_abort(bank);
833  if (retval != ERROR_OK)
834  return retval;
835 
836  /* Wait for busy to be cleared */
837  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
838  if (retval != ERROR_OK)
839  return retval;
840 
841  /* send command byte */
842  snprintf(output, sizeof(output), "spi: %02x ", cmd_byte);
843  if (num_read == 0) {
844  /* write, send cmd byte */
845  retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_write) - 2);
846  if (retval != ERROR_OK)
847  goto err;
848 
849  if (IS_OCTOSPI)
852  ((num_write == 1) ? OCTOSPI_NO_DATA : ~0U)), cmd_byte);
853  else
856  ((num_write == 1) ? QSPI_NO_DATA : ~0U)) |
857  (QSPI_WRITE_MODE | cmd_byte));
858  if (retval != ERROR_OK)
859  goto err;
860 
861  /* send additional data bytes */
862  for (count = 3; count < CMD_ARGC; count++) {
863  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
864  snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
865  retval = target_write_u8(target, io_base + SPI_DR, data);
866  if (retval != ERROR_OK)
867  goto err;
868  strncat(output, temp, sizeof(output) - strlen(output) - 1);
869  }
870  strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
871  } else {
872  /* read, pack additional bytes into address */
873  addr = 0;
874  for (count = 3; count < CMD_ARGC; count++) {
875  COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
876  snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
877  addr = (addr << 8) | data;
878  strncat(output, temp, sizeof(output) - strlen(output) - 1);
879  }
880  strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
881 
882  /* send cmd byte, if ADMODE indicates no address, this already triggers command */
883  retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_read) - 1);
884  if (retval != ERROR_OK)
885  goto err;
886  if (IS_OCTOSPI)
889  ((num_write == 1) ? OCTOSPI_NO_ADDR : ~0U)) |
890  (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS), cmd_byte);
891  else
894  ((num_write == 1) ? QSPI_NO_ADDR : ~0U)) |
895  ((QSPI_READ_MODE | (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS) | cmd_byte)));
896  if (retval != ERROR_OK)
897  goto err;
898 
899  if (num_write > 1) {
900  /* if ADMODE indicates address required, only the write to AR triggers command */
901  retval = target_write_u32(target, io_base + SPI_AR, addr);
902  if (retval != ERROR_OK)
903  goto err;
904  }
905 
906  /* read response bytes */
907  for ( ; num_read > 0; num_read--) {
908  retval = target_read_u8(target, io_base + SPI_DR, &data);
909  if (retval != ERROR_OK)
910  goto err;
911  snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
912  strncat(output, temp, sizeof(output) - strlen(output) - 1);
913  }
914  }
915  command_print(CMD, "%s", output);
916 
917 err:
918  /* Switch to memory mapped mode before return to prompt */
919  set_mm_mode(bank);
920 
921  return retval;
922 }
923 
924 static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
925 {
926  struct target *target = bank->target;
927  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
928  uint32_t io_base = stmqspi_info->io_base;
929  uint16_t status;
930  int retval;
931 
932  retval = qspi_write_enable(bank);
933  if (retval != ERROR_OK)
934  goto err;
935 
936  /* Send Sector Erase command */
937  if (IS_OCTOSPI)
939  stmqspi_info->dev.erase_cmd);
940  else
942  if (retval != ERROR_OK)
943  goto err;
944 
945  /* Address is sector offset, this write initiates command transmission */
946  retval = target_write_u32(target, io_base + SPI_AR, bank->sectors[sector].offset);
947  if (retval != ERROR_OK)
948  goto err;
949 
950  /* Wait for transmit of command completed */
952  if (retval != ERROR_OK)
953  goto err;
954 
955  /* Read flash status register(s) */
956  retval = read_status_reg(bank, &status);
957  if (retval != ERROR_OK)
958  goto err;
959 
960  LOG_DEBUG("erase status regs: 0x%04" PRIx16, status);
961 
962  /* Check for command in progress for flash 1 */
963  /* If BSY and WE are already cleared the erase did probably complete already */
964  if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
965  != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
966  ((status & SPIFLASH_WE_BIT) != 0)) {
967  LOG_ERROR("Sector erase command not accepted by flash1. Status=0x%02x",
968  status & 0xFFU);
970  goto err;
971  }
972 
973  /* Check for command in progress for flash 2 */
974  /* If BSY and WE are already cleared the erase did probably complete already */
975  status >>= 8;
976  if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
977  ((status & SPIFLASH_BSY_BIT) == 0) &&
978  ((status & SPIFLASH_WE_BIT) != 0)) {
979  LOG_ERROR("Sector erase command not accepted by flash2. Status=0x%02x",
980  status & 0xFFU);
982  goto err;
983  }
984 
985  /* Erase takes a long time, so some sort of progress message is a good idea */
986  LOG_DEBUG("erasing sector %4u", sector);
987 
988  /* Poll WIP for end of self timed Sector Erase cycle */
990 
991 err:
992  return retval;
993 }
994 
995 static int stmqspi_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
996 {
997  struct target *target = bank->target;
998  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
999  unsigned int sector;
1000  int retval = ERROR_OK;
1001 
1002  LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
1003 
1004  if (target->state != TARGET_HALTED) {
1005  LOG_ERROR("Target not halted");
1006  return ERROR_TARGET_NOT_HALTED;
1007  }
1008 
1009  if (!(stmqspi_info->probed)) {
1010  LOG_ERROR("Flash bank not probed");
1012  }
1013 
1014  if (stmqspi_info->dev.erase_cmd == 0x00) {
1015  LOG_ERROR("Sector erase not available for this device");
1017  }
1018 
1019  if ((last < first) || (last >= bank->num_sectors)) {
1020  LOG_ERROR("Flash sector invalid");
1022  }
1023 
1024  for (sector = first; sector <= last; sector++) {
1025  if (bank->sectors[sector].is_protected) {
1026  LOG_ERROR("Flash sector %u protected", sector);
1027  return ERROR_FLASH_PROTECTED;
1028  }
1029  }
1030 
1031  for (sector = first; sector <= last; sector++) {
1032  retval = qspi_erase_sector(bank, sector);
1033  if (retval != ERROR_OK)
1034  break;
1035  alive_sleep(10);
1036  keep_alive();
1037  }
1038 
1039  if (retval != ERROR_OK)
1040  LOG_ERROR("Flash sector_erase failed on sector %u", sector);
1041 
1042  /* Switch to memory mapped mode before return to prompt */
1043  set_mm_mode(bank);
1044 
1045  return retval;
1046 }
1047 
1048 static int stmqspi_protect(struct flash_bank *bank, int set,
1049  unsigned int first, unsigned int last)
1050 {
1051  unsigned int sector;
1052 
1053  for (sector = first; sector <= last; sector++)
1054  bank->sectors[sector].is_protected = set;
1055 
1056  if (set)
1057  LOG_WARNING("setting soft protection only, not related to flash's hardware write protection");
1058 
1059  return ERROR_OK;
1060 }
1061 
1062 /* Check whether flash is blank */
1064 {
1065  struct target *target = bank->target;
1066  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1067  struct duration bench;
1068  struct reg_param reg_params[2];
1069  struct armv7m_algorithm armv7m_info;
1070  struct working_area *algorithm;
1071  const uint8_t *code;
1072  struct sector_info erase_check_info;
1073  uint32_t codesize, maxsize, result, exit_point;
1074  unsigned int count, index, num_sectors, sector;
1075  int retval;
1076  const uint32_t erased = 0x00FF;
1077 
1078  if (target->state != TARGET_HALTED) {
1079  LOG_ERROR("Target not halted");
1080  return ERROR_TARGET_NOT_HALTED;
1081  }
1082 
1083  if (!(stmqspi_info->probed)) {
1084  LOG_ERROR("Flash bank not probed");
1086  }
1087 
1088  /* Abort any previous operation */
1089  retval = stmqspi_abort(bank);
1090  if (retval != ERROR_OK)
1091  return retval;
1092 
1093  /* Wait for busy to be cleared */
1094  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1095  if (retval != ERROR_OK)
1096  return retval;
1097 
1098  /* see contrib/loaders/flash/stmqspi/stmqspi_erase_check.S for src */
1099  static const uint8_t stmqspi_erase_check_code[] = {
1100  #include "../../../contrib/loaders/flash/stmqspi/stmqspi_erase_check.inc"
1101  };
1102 
1103  /* see contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S for src */
1104  static const uint8_t stmoctospi_erase_check_code[] = {
1105  #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_erase_check.inc"
1106  };
1107 
1108  if (IS_OCTOSPI) {
1109  code = stmoctospi_erase_check_code;
1110  codesize = sizeof(stmoctospi_erase_check_code);
1111  } else {
1112  code = stmqspi_erase_check_code;
1113  codesize = sizeof(stmqspi_erase_check_code);
1114  }
1115 
1116  /* This will overlay the last 4 words of stmqspi/stmoctospi_erase_check_code in target */
1117  /* for read use the saved settings (memory mapped mode) but indirect read mode */
1118  uint32_t ccr_buffer[][4] = {
1119  /* cr (not used for QSPI) *
1120  * ccr (for both QSPI and OCTOSPI) *
1121  * tcr (not used for QSPI) *
1122  * ir (not used for QSPI) */
1123  {
1126  h_to_le_32(stmqspi_info->saved_tcr),
1127  h_to_le_32(stmqspi_info->saved_ir),
1128  },
1129  };
1130 
1132  if (maxsize < codesize + sizeof(erase_check_info)) {
1133  LOG_ERROR("Not enough working area, can't do QSPI blank check");
1135  }
1136 
1137  num_sectors = (maxsize - codesize) / sizeof(erase_check_info);
1138  num_sectors = (bank->num_sectors < num_sectors) ? bank->num_sectors : num_sectors;
1139 
1141  codesize + num_sectors * sizeof(erase_check_info), &algorithm) != ERROR_OK) {
1142  LOG_ERROR("allocating working area failed");
1144  };
1145 
1146  /* prepare blank check code, excluding ccr_buffer */
1147  retval = target_write_buffer(target, algorithm->address,
1148  codesize - sizeof(ccr_buffer), code);
1149  if (retval != ERROR_OK)
1150  goto err;
1151 
1152  /* prepare QSPI/OCTOSPI_CCR register values */
1153  retval = target_write_buffer(target, algorithm->address
1154  + codesize - sizeof(ccr_buffer),
1155  sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1156  if (retval != ERROR_OK)
1157  goto err;
1158 
1159  duration_start(&bench);
1160 
1161  /* after breakpoint instruction (halfword), one nop (halfword) and
1162  * port_buffer till end of code */
1163  exit_point = algorithm->address + codesize - sizeof(uint32_t) - sizeof(ccr_buffer);
1164 
1165  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* sector count */
1166  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1167 
1168  sector = 0;
1169  while (sector < bank->num_sectors) {
1170  /* at most num_sectors sectors to handle in one run */
1171  count = bank->num_sectors - sector;
1172  if (count > num_sectors)
1173  count = num_sectors;
1174 
1175  for (index = 0; index < count; index++) {
1176  erase_check_info.offset = h_to_le_32(bank->sectors[sector + index].offset);
1177  erase_check_info.size = h_to_le_32(bank->sectors[sector + index].size);
1178  erase_check_info.result = h_to_le_32(erased);
1179 
1180  retval = target_write_buffer(target, algorithm->address
1181  + codesize + index * sizeof(erase_check_info),
1182  sizeof(erase_check_info), (uint8_t *)&erase_check_info);
1183  if (retval != ERROR_OK)
1184  goto err;
1185  }
1186 
1187  buf_set_u32(reg_params[0].value, 0, 32, count);
1188  buf_set_u32(reg_params[1].value, 0, 32, stmqspi_info->io_base);
1189 
1190  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1191  armv7m_info.core_mode = ARM_MODE_THREAD;
1192 
1193  LOG_DEBUG("checking sectors %u to %u", sector, sector + count - 1);
1194  /* check a block of sectors */
1195  retval = target_run_algorithm(target,
1196  0, NULL,
1197  ARRAY_SIZE(reg_params), reg_params,
1198  algorithm->address, exit_point,
1199  count * ((bank->sectors[sector].size >> 6) + 1) + 1000,
1200  &armv7m_info);
1201  if (retval != ERROR_OK)
1202  break;
1203 
1204  for (index = 0; index < count; index++) {
1205  retval = target_read_buffer(target, algorithm->address
1206  + codesize + index * sizeof(erase_check_info),
1207  sizeof(erase_check_info), (uint8_t *)&erase_check_info);
1208  if (retval != ERROR_OK)
1209  goto err;
1210 
1211  if ((erase_check_info.offset != h_to_le_32(bank->sectors[sector + index].offset)) ||
1212  (erase_check_info.size != 0)) {
1213  LOG_ERROR("corrupted blank check info");
1214  goto err;
1215  }
1216 
1217  /* we need le_32_to_h, but that's the same as h_to_le_32 */
1218  result = h_to_le_32(erase_check_info.result);
1219  bank->sectors[sector + index].is_erased = ((result & 0xFF) == 0xFF);
1220  LOG_DEBUG("Flash sector %u checked: 0x%04x", sector + index, result & 0xFFFFU);
1221  }
1222  keep_alive();
1223  sector += count;
1224  }
1225 
1226  destroy_reg_param(&reg_params[0]);
1227  destroy_reg_param(&reg_params[1]);
1228 
1229  duration_measure(&bench);
1230  LOG_INFO("stmqspi blank checked in %fs (%0.3f KiB/s)", duration_elapsed(&bench),
1231  duration_kbps(&bench, bank->size));
1232 
1233 err:
1234  target_free_working_area(target, algorithm);
1235 
1236  /* Switch to memory mapped mode before return to prompt */
1237  set_mm_mode(bank);
1238 
1239  return retval;
1240 }
1241 
1242 /* Verify checksum */
1243 static int qspi_verify(struct flash_bank *bank, uint8_t *buffer,
1244  uint32_t offset, uint32_t count)
1245 {
1246  struct target *target = bank->target;
1247  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1248  struct reg_param reg_params[4];
1249  struct armv7m_algorithm armv7m_info;
1250  struct working_area *algorithm;
1251  const uint8_t *code;
1252  uint32_t pagesize, codesize, crc32, result, exit_point;
1253  int retval;
1254 
1255  /* see contrib/loaders/flash/stmqspi/stmqspi_crc32.S for src */
1256  static const uint8_t stmqspi_crc32_code[] = {
1257  #include "../../../contrib/loaders/flash/stmqspi/stmqspi_crc32.inc"
1258  };
1259 
1260  /* see contrib/loaders/flash/stmqspi/stmoctospi_crc32.S for src */
1261  static const uint8_t stmoctospi_crc32_code[] = {
1262  #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_crc32.inc"
1263  };
1264 
1265  if (IS_OCTOSPI) {
1266  code = stmoctospi_crc32_code;
1267  codesize = sizeof(stmoctospi_crc32_code);
1268  } else {
1269  code = stmqspi_crc32_code;
1270  codesize = sizeof(stmqspi_crc32_code);
1271  }
1272 
1273  /* block size doesn't matter that much here */
1274  pagesize = stmqspi_info->dev.sectorsize;
1275  if (pagesize == 0)
1276  pagesize = stmqspi_info->dev.pagesize;
1277  if (pagesize == 0)
1278  pagesize = SPIFLASH_DEF_PAGESIZE;
1279 
1280  /* adjust size according to dual flash mode */
1281  pagesize = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
1282 
1283  /* This will overlay the last 4 words of stmqspi/stmoctospi_crc32_code in target */
1284  /* for read use the saved settings (memory mapped mode) but indirect read mode */
1285  uint32_t ccr_buffer[][4] = {
1286  /* cr (not used for QSPI) *
1287  * ccr (for both QSPI and OCTOSPI) *
1288  * tcr (not used for QSPI) *
1289  * ir (not used for QSPI) */
1290  {
1293  h_to_le_32(stmqspi_info->saved_tcr),
1294  h_to_le_32(stmqspi_info->saved_ir),
1295  },
1296  };
1297 
1298  if (target_alloc_working_area_try(target, codesize, &algorithm) != ERROR_OK) {
1299  LOG_ERROR("Not enough working area, can't do QSPI verify");
1301  };
1302 
1303  /* prepare verify code, excluding ccr_buffer */
1304  retval = target_write_buffer(target, algorithm->address,
1305  codesize - sizeof(ccr_buffer), code);
1306  if (retval != ERROR_OK)
1307  goto err;
1308 
1309  /* prepare QSPI/OCTOSPI_CCR register values */
1310  retval = target_write_buffer(target, algorithm->address
1311  + codesize - sizeof(ccr_buffer),
1312  sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1313  if (retval != ERROR_OK)
1314  goto err;
1315 
1316  /* after breakpoint instruction (halfword), one nop (halfword) and
1317  * port_buffer till end of code */
1318  exit_point = algorithm->address + codesize - sizeof(uint32_t) - sizeof(ccr_buffer);
1319 
1320  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* count (in), crc32 (out) */
1321  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* pagesize */
1322  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* offset into flash address */
1323  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1324 
1325  buf_set_u32(reg_params[0].value, 0, 32, count);
1326  buf_set_u32(reg_params[1].value, 0, 32, pagesize);
1327  buf_set_u32(reg_params[2].value, 0, 32, offset);
1328  buf_set_u32(reg_params[3].value, 0, 32, stmqspi_info->io_base);
1329 
1330 
1331  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1332  armv7m_info.core_mode = ARM_MODE_THREAD;
1333 
1334  retval = target_run_algorithm(target,
1335  0, NULL,
1336  ARRAY_SIZE(reg_params), reg_params,
1337  algorithm->address, exit_point,
1338  (count >> 5) + 1000,
1339  &armv7m_info);
1340  keep_alive();
1341 
1343 
1344  if (retval == ERROR_OK) {
1345  result = buf_get_u32(reg_params[0].value, 0, 32);
1346  LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
1347  offset + bank->base, count, ~crc32, result);
1348  if (~crc32 != result)
1349  retval = ERROR_FAIL;
1350  }
1351 
1352  destroy_reg_param(&reg_params[0]);
1353  destroy_reg_param(&reg_params[1]);
1354  destroy_reg_param(&reg_params[2]);
1355  destroy_reg_param(&reg_params[3]);
1356 
1357 err:
1358  target_free_working_area(target, algorithm);
1359 
1360  /* Switch to memory mapped mode before return to prompt */
1361  set_mm_mode(bank);
1362 
1363  return retval;
1364 }
1365 
1366 static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer,
1367  uint32_t offset, uint32_t count, bool write)
1368 {
1369  struct target *target = bank->target;
1370  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1371  uint32_t io_base = stmqspi_info->io_base;
1372  struct reg_param reg_params[6];
1373  struct armv7m_algorithm armv7m_info;
1374  struct working_area *algorithm;
1375  uint32_t pagesize, fifo_start, fifosize, remaining;
1376  uint32_t maxsize, codesize, exit_point;
1377  const uint8_t *code = NULL;
1378  unsigned int dual;
1379  int retval;
1380 
1381  LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
1382  __func__, offset, count);
1383 
1384  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1385 
1386  /* see contrib/loaders/flash/stmqspi/stmqspi_read.S for src */
1387  static const uint8_t stmqspi_read_code[] = {
1388 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_read.inc"
1389  };
1390 
1391  /* see contrib/loaders/flash/stmqspi/stmoctospi_read.S for src */
1392  static const uint8_t stmoctospi_read_code[] = {
1393 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_read.inc"
1394  };
1395 
1396  /* see contrib/loaders/flash/stmqspi/stmqspi_write.S for src */
1397  static const uint8_t stmqspi_write_code[] = {
1398 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc"
1399  };
1400 
1401  /* see contrib/loaders/flash/stmqspi/stmoctospi_write.S for src */
1402  static const uint8_t stmoctospi_write_code[] = {
1403 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_write.inc"
1404  };
1405 
1406  /* This will overlay the last 12 words of stmqspi/stmoctospi_read/write_code in target */
1407  /* for read use the saved settings (memory mapped mode) but indirect read mode */
1408  uint32_t ccr_buffer[][4] = {
1409  /* cr (not used for QSPI) *
1410  * ccr (for both QSPI and OCTOSPI) *
1411  * tcr (not used for QSPI) *
1412  * ir (not used for QSPI) */
1413  {
1416  h_to_le_32((stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
1417  (OPI_MODE ? (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)),
1419  },
1420  {
1423  h_to_le_32(stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK),
1425  },
1426  {
1430  h_to_le_32(write ? (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) :
1431  stmqspi_info->saved_tcr),
1432  h_to_le_32(write ? OPI_CMD(stmqspi_info->dev.pprog_cmd) : stmqspi_info->saved_ir),
1433  },
1434  };
1435 
1436  /* force reasonable defaults */
1437  fifosize = stmqspi_info->dev.sectorsize ?
1438  stmqspi_info->dev.sectorsize : stmqspi_info->dev.size_in_bytes;
1439 
1440  if (write) {
1441  if (IS_OCTOSPI) {
1442  code = stmoctospi_write_code;
1443  codesize = sizeof(stmoctospi_write_code);
1444  } else {
1445  code = stmqspi_write_code;
1446  codesize = sizeof(stmqspi_write_code);
1447  }
1448  } else {
1449  if (IS_OCTOSPI) {
1450  code = stmoctospi_read_code;
1451  codesize = sizeof(stmoctospi_read_code);
1452  } else {
1453  code = stmqspi_read_code;
1454  codesize = sizeof(stmqspi_read_code);
1455  }
1456  }
1457 
1458  /* for write, pagesize must be taken into account */
1459  /* for read, the page size doesn't matter that much */
1460  pagesize = stmqspi_info->dev.pagesize;
1461  if (pagesize == 0)
1462  pagesize = (fifosize <= SPIFLASH_DEF_PAGESIZE) ?
1463  fifosize : SPIFLASH_DEF_PAGESIZE;
1464 
1465  /* adjust sizes according to dual flash mode */
1466  pagesize <<= dual;
1467  fifosize <<= dual;
1468 
1469  /* memory buffer, we assume sectorsize to be a power of 2 times pagesize */
1471  if (maxsize < codesize + 2 * sizeof(uint32_t) + pagesize) {
1472  LOG_ERROR("not enough working area, can't do QSPI page reads/writes");
1474  }
1475 
1476  /* fifo size at most sector size, and multiple of page size */
1477  maxsize -= (codesize + 2 * sizeof(uint32_t));
1478  fifosize = ((maxsize < fifosize) ? maxsize : fifosize) & ~(pagesize - 1);
1479 
1481  codesize + 2 * sizeof(uint32_t) + fifosize, &algorithm) != ERROR_OK) {
1482  LOG_ERROR("allocating working area failed");
1484  };
1485 
1486  /* prepare flash write code, excluding ccr_buffer */
1487  retval = target_write_buffer(target, algorithm->address,
1488  codesize - sizeof(ccr_buffer), code);
1489  if (retval != ERROR_OK)
1490  goto err;
1491 
1492  /* prepare QSPI/OCTOSPI_CCR register values */
1493  retval = target_write_buffer(target, algorithm->address
1494  + codesize - sizeof(ccr_buffer),
1495  sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1496  if (retval != ERROR_OK)
1497  goto err;
1498 
1499  /* target buffer starts right after flash_write_code, i.e.
1500  * wp and rp are implicitly included in buffer!!! */
1501  fifo_start = algorithm->address + codesize + 2 * sizeof(uint32_t);
1502 
1503  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* count (in), status (out) */
1504  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* pagesize */
1505  init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT); /* offset into flash address */
1506  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1507  init_reg_param(&reg_params[4], "r8", 32, PARAM_OUT); /* fifo start */
1508  init_reg_param(&reg_params[5], "r9", 32, PARAM_OUT); /* fifo end + 1 */
1509 
1510  buf_set_u32(reg_params[0].value, 0, 32, count);
1511  buf_set_u32(reg_params[1].value, 0, 32, pagesize);
1512  buf_set_u32(reg_params[2].value, 0, 32, offset);
1513  buf_set_u32(reg_params[3].value, 0, 32, io_base);
1514  buf_set_u32(reg_params[4].value, 0, 32, fifo_start);
1515  buf_set_u32(reg_params[5].value, 0, 32, fifo_start + fifosize);
1516 
1517  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1518  armv7m_info.core_mode = ARM_MODE_THREAD;
1519 
1520  /* after breakpoint instruction (halfword), one nop (halfword) and
1521  * ccr_buffer follow till end of code */
1522  exit_point = algorithm->address + codesize
1523  - (sizeof(ccr_buffer) + sizeof(uint32_t));
1524 
1525  if (write) {
1527  0, NULL,
1528  ARRAY_SIZE(reg_params), reg_params,
1529  algorithm->address + codesize,
1530  fifosize + 2 * sizeof(uint32_t),
1531  algorithm->address, exit_point,
1532  &armv7m_info);
1533  } else {
1535  0, NULL,
1536  ARRAY_SIZE(reg_params), reg_params,
1537  algorithm->address + codesize,
1538  fifosize + 2 * sizeof(uint32_t),
1539  algorithm->address, exit_point,
1540  &armv7m_info);
1541  }
1542 
1543  remaining = buf_get_u32(reg_params[0].value, 0, 32);
1544  if ((retval == ERROR_OK) && remaining)
1546 
1547  if (retval != ERROR_OK) {
1548  offset = buf_get_u32(reg_params[2].value, 0, 32);
1549  LOG_ERROR("flash %s failed at address 0x%" PRIx32 ", remaining 0x%" PRIx32,
1550  write ? "write" : "read", offset, remaining);
1551  }
1552 
1553  destroy_reg_param(&reg_params[0]);
1554  destroy_reg_param(&reg_params[1]);
1555  destroy_reg_param(&reg_params[2]);
1556  destroy_reg_param(&reg_params[3]);
1557  destroy_reg_param(&reg_params[4]);
1558  destroy_reg_param(&reg_params[5]);
1559 
1560 err:
1561  target_free_working_area(target, algorithm);
1562 
1563  /* Switch to memory mapped mode before return to prompt */
1564  set_mm_mode(bank);
1565 
1566  return retval;
1567 }
1568 
1569 static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer,
1570  uint32_t offset, uint32_t count)
1571 {
1572  struct target *target = bank->target;
1573  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1574  int retval;
1575 
1576  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1577  __func__, offset, count);
1578 
1579  if (target->state != TARGET_HALTED) {
1580  LOG_ERROR("Target not halted");
1581  return ERROR_TARGET_NOT_HALTED;
1582  }
1583 
1584  if (!(stmqspi_info->probed)) {
1585  LOG_ERROR("Flash bank not probed");
1587  }
1588 
1589  if (offset + count > bank->size) {
1590  LOG_WARNING("Read beyond end of flash. Extra data to be ignored.");
1591  count = bank->size - offset;
1592  }
1593 
1594  /* Abort any previous operation */
1595  retval = stmqspi_abort(bank);
1596  if (retval != ERROR_OK)
1597  return retval;
1598 
1599  /* Wait for busy to be cleared */
1600  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1601  if (retval != ERROR_OK)
1602  return retval;
1603 
1604  return qspi_read_write_block(bank, buffer, offset, count, false);
1605 }
1606 
1607 static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
1608  uint32_t offset, uint32_t count)
1609 {
1610  struct target *target = bank->target;
1611  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1612  unsigned int dual, sector;
1613  bool octal_dtr;
1614  int retval;
1615 
1616  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1617  __func__, offset, count);
1618 
1619  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1620  octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
1621 
1622  if (target->state != TARGET_HALTED) {
1623  LOG_ERROR("Target not halted");
1624  return ERROR_TARGET_NOT_HALTED;
1625  }
1626 
1627  if (!(stmqspi_info->probed)) {
1628  LOG_ERROR("Flash bank not probed");
1630  }
1631 
1632  if (offset + count > bank->size) {
1633  LOG_WARNING("Write beyond end of flash. Extra data discarded.");
1634  count = bank->size - offset;
1635  }
1636 
1637  /* Check sector protection */
1638  for (sector = 0; sector < bank->num_sectors; sector++) {
1639  /* Start offset in or before this sector? */
1640  /* End offset in or behind this sector? */
1641  if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
1642  ((offset + count - 1) >= bank->sectors[sector].offset) &&
1643  bank->sectors[sector].is_protected) {
1644  LOG_ERROR("Flash sector %u protected", sector);
1645  return ERROR_FLASH_PROTECTED;
1646  }
1647  }
1648 
1649  if ((dual || octal_dtr) && ((offset & 1) != 0 || (count & 1) != 0)) {
1650  LOG_ERROR("In dual-QSPI and octal-DTR modes writes must be two byte aligned: "
1651  "%s: address=0x%08" PRIx32 " len=0x%08" PRIx32, __func__, offset, count);
1653  }
1654 
1655  /* Abort any previous operation */
1656  retval = stmqspi_abort(bank);
1657  if (retval != ERROR_OK)
1658  return retval;
1659 
1660  /* Wait for busy to be cleared */
1661  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1662  if (retval != ERROR_OK)
1663  return retval;
1664 
1665  return qspi_read_write_block(bank, (uint8_t *)buffer, offset, count, true);
1666 }
1667 
1668 static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
1669  uint32_t offset, uint32_t count)
1670 {
1671  struct target *target = bank->target;
1672  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1673  unsigned int dual;
1674  bool octal_dtr;
1675  int retval;
1676 
1677  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1678  __func__, offset, count);
1679 
1680  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1681  octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
1682 
1683  if (target->state != TARGET_HALTED) {
1684  LOG_ERROR("Target not halted");
1685  return ERROR_TARGET_NOT_HALTED;
1686  }
1687 
1688  if (!(stmqspi_info->probed)) {
1689  LOG_ERROR("Flash bank not probed");
1691  }
1692 
1693  if (offset + count > bank->size) {
1694  LOG_WARNING("Verify beyond end of flash. Extra data ignored.");
1695  count = bank->size - offset;
1696  }
1697 
1698  if ((dual || octal_dtr) && ((offset & 1) != 0 || (count & 1) != 0)) {
1699  LOG_ERROR("In dual-QSPI and octal-DTR modes reads must be two byte aligned: "
1700  "%s: address=0x%08" PRIx32 " len=0x%08" PRIx32, __func__, offset, count);
1702  }
1703 
1704  /* Abort any previous operation */
1705  retval = stmqspi_abort(bank);
1706  if (retval != ERROR_OK)
1707  return retval;
1708 
1709  /* Wait for busy to be cleared */
1710  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1711  if (retval != ERROR_OK)
1712  return retval;
1713 
1714  return qspi_verify(bank, (uint8_t *)buffer, offset, count);
1715 }
1716 
1717 /* Find appropriate dummy setting, in particular octo mode */
1718 static int find_sfdp_dummy(struct flash_bank *bank, int len)
1719 {
1720  struct target *target = bank->target;
1721  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1722  uint32_t io_base = stmqspi_info->io_base;
1723  uint8_t data;
1724  unsigned int dual, count;
1725  bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
1726  int retval;
1727  const unsigned int max_bytes = 64;
1728 
1729  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1730 
1731  LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
1732  __func__, len, dual, flash1);
1733 
1734  /* Abort any previous operation */
1735  retval = target_write_u32(target, io_base + SPI_CR,
1736  stmqspi_info->saved_cr | BIT(SPI_ABORT));
1737  if (retval != ERROR_OK)
1738  goto err;
1739 
1740  /* Wait for busy to be cleared */
1741  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1742  if (retval != ERROR_OK)
1743  goto err;
1744 
1745  /* Switch to saved_cr (had to be set accordingly before this call) */
1746  retval = target_write_u32(target, io_base + SPI_CR, stmqspi_info->saved_cr);
1747  if (retval != ERROR_OK)
1748  goto err;
1749 
1750  /* Read at most that many bytes */
1751  retval = target_write_u32(target, io_base + SPI_DLR, (max_bytes << dual) - 1);
1752  if (retval != ERROR_OK)
1753  return retval;
1754 
1755  /* Read SFDP block */
1756  if (IS_OCTOSPI)
1759  else
1761  if (retval != ERROR_OK)
1762  goto err;
1763 
1764  /* Read from start of sfdp block */
1765  retval = target_write_u32(target, io_base + SPI_AR, 0);
1766  if (retval != ERROR_OK)
1767  goto err;
1768 
1769  for (count = 0 ; count < max_bytes; count++) {
1770  if ((dual != 0) && !flash1) {
1771  /* discard even byte in dual flash-mode if flash2 */
1772  retval = target_read_u8(target, io_base + SPI_DR, &data);
1773  if (retval != ERROR_OK)
1774  goto err;
1775  }
1776 
1777  retval = target_read_u8(target, io_base + SPI_DR, &data);
1778  if (retval != ERROR_OK)
1779  goto err;
1780 
1781  if (data == 0x53) {
1782  LOG_DEBUG("start of SFDP header for flash%c after %u dummy bytes",
1783  flash1 ? '1' : '2', count);
1784  if (flash1)
1785  stmqspi_info->sfdp_dummy1 = count;
1786  else
1787  stmqspi_info->sfdp_dummy2 = count;
1788  return ERROR_OK;
1789  }
1790 
1791  if ((dual != 0) && flash1) {
1792  /* discard odd byte in dual flash-mode if flash1 */
1793  retval = target_read_u8(target, io_base + SPI_DR, &data);
1794  if (retval != ERROR_OK)
1795  goto err;
1796  }
1797  }
1798 
1799  LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
1800 
1801 err:
1802  /* Abort operation */
1803  retval = stmqspi_abort(bank);
1804 
1805  return retval;
1806 }
1807 
1808 /* Read SFDP parameter block */
1809 static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
1810  uint32_t words, uint32_t *buffer)
1811 {
1812  struct target *target = bank->target;
1813  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1814  uint32_t io_base = stmqspi_info->io_base;
1815  bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
1816  unsigned int dual, count, len, *dummy;
1817  int retval;
1818 
1819  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1820 
1821  if (IS_OCTOSPI && (((stmqspi_info->saved_ccr >> SPI_DMODE_POS) & 0x7) > 3)) {
1822  /* in OCTO mode 4-byte address and (yet) unknown number of dummy clocks */
1823  len = 4;
1824 
1825  /* in octo mode, use sfdp_dummy1 only */
1826  dummy = &stmqspi_info->sfdp_dummy1;
1827  if (*dummy == 0) {
1828  retval = find_sfdp_dummy(bank, len);
1829  if (retval != ERROR_OK)
1830  return retval;
1831  }
1832  } else {
1833  /* in all other modes 3-byte-address and 8(?) dummy clocks */
1834  len = 3;
1835 
1836  /* use sfdp_dummy1/2 according to currently selected flash */
1837  dummy = (stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH)) ?
1838  &stmqspi_info->sfdp_dummy2 : &stmqspi_info->sfdp_dummy1;
1839 
1840  /* according to SFDP standard, there should always be 8 dummy *CLOCKS*
1841  * giving 1, 2 or 4 dummy *BYTES*, however, this is apparently not
1842  * always implemented correctly, so determine the number of dummy bytes
1843  * dynamically */
1844  if (*dummy == 0) {
1845  retval = find_sfdp_dummy(bank, len);
1846  if (retval != ERROR_OK)
1847  return retval;
1848  }
1849  }
1850 
1851  LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08" PRIx32 " dummy=%u",
1852  __func__, addr, words, *dummy);
1853 
1854  /* Abort any previous operation */
1855  retval = target_write_u32(target, io_base + SPI_CR,
1856  stmqspi_info->saved_cr | BIT(SPI_ABORT));
1857  if (retval != ERROR_OK)
1858  goto err;
1859 
1860  /* Wait for busy to be cleared */
1861  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1862  if (retval != ERROR_OK)
1863  goto err;
1864 
1865  /* Switch to one flash only */
1866  retval = target_write_u32(target, io_base + SPI_CR, stmqspi_info->saved_cr);
1867  if (retval != ERROR_OK)
1868  goto err;
1869 
1870  /* Read that many words plus dummy bytes */
1871  retval = target_write_u32(target, io_base + SPI_DLR,
1872  ((*dummy + words * sizeof(uint32_t)) << dual) - 1);
1873  if (retval != ERROR_OK)
1874  goto err;
1875 
1876  /* Read SFDP block */
1877  if (IS_OCTOSPI)
1880  else
1882  if (retval != ERROR_OK)
1883  goto err;
1884 
1885  retval = target_write_u32(target, io_base + SPI_AR, addr << dual);
1886  if (retval != ERROR_OK)
1887  goto err;
1888 
1889  /* dummy clocks */
1890  for (count = *dummy << dual; count > 0; --count) {
1891  retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *)buffer);
1892  if (retval != ERROR_OK)
1893  goto err;
1894  }
1895 
1896  for ( ; words > 0; words--) {
1897  if (dual != 0) {
1898  uint32_t word1, word2;
1899 
1900  retval = target_read_u32(target, io_base + SPI_DR, &word1);
1901  if (retval != ERROR_OK)
1902  goto err;
1903  retval = target_read_u32(target, io_base + SPI_DR, &word2);
1904  if (retval != ERROR_OK)
1905  goto err;
1906 
1907  if (!flash1) {
1908  /* shift odd numbered bytes into even numbered ones */
1909  word1 >>= 8;
1910  word2 >>= 8;
1911  }
1912 
1913  /* pack even numbered bytes into one word */
1914  *buffer = (word1 & 0xFFU) | ((word1 & 0xFF0000U) >> 8) |
1915  ((word2 & 0xFFU) << 16) | ((word2 & 0xFF0000U) << 8);
1916 
1917 
1918  } else {
1919  retval = target_read_u32(target, io_base + SPI_DR, buffer);
1920  if (retval != ERROR_OK)
1921  goto err;
1922  }
1923  LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
1924 
1925  /* endian correction, sfdp data is always le uint32_t based */
1926  *buffer = le_to_h_u32((uint8_t *)buffer);
1927  buffer++;
1928  }
1929 
1930 err:
1931  return retval;
1932 }
1933 
1934 /* Return ID of flash device(s) */
1935 /* On exit, indirect mode is kept */
1936 static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
1937 {
1938  struct target *target = bank->target;
1939  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1940  uint32_t io_base = stmqspi_info->io_base;
1941  uint8_t byte;
1942  unsigned int type, count, len1, len2;
1943  int retval = ERROR_OK;
1944 
1945  /* invalidate both ids */
1946  *id1 = 0;
1947  *id2 = 0;
1948 
1949  if (target->state != TARGET_HALTED) {
1950  LOG_ERROR("Target not halted");
1951  return ERROR_TARGET_NOT_HALTED;
1952  }
1953 
1954  /* SPIFLASH_READ_MID causes device in octal mode to go berserk, so don't use in this case */
1955  for (type = (IS_OCTOSPI && OPI_MODE) ? 1 : 0; type < 2 ; type++) {
1956  /* Abort any previous operation */
1957  retval = stmqspi_abort(bank);
1958  if (retval != ERROR_OK)
1959  goto err;
1960 
1961  /* Poll WIP */
1963  if (retval != ERROR_OK)
1964  goto err;
1965 
1966  /* Wait for busy to be cleared */
1967  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1968  if (retval != ERROR_OK)
1969  goto err;
1970 
1971  /* Read at most 16 bytes per chip */
1972  count = 16;
1973  retval = target_write_u32(target, io_base + SPI_DLR,
1974  (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH) ? count * 2 : count) - 1);
1975  if (retval != ERROR_OK)
1976  goto err;
1977 
1978  /* Read id: one particular flash chip (N25Q128) switches back to SPI mode when receiving
1979  * SPI_FLASH_READ_ID in QPI mode, hence try SPIFLASH_READ_MID first */
1980  switch (type) {
1981  case 0:
1982  if (IS_OCTOSPI)
1985  else
1987  break;
1988 
1989  case 1:
1990  if (IS_OCTOSPI)
1993  else
1995  break;
1996 
1997  default:
1998  return ERROR_FAIL;
1999  }
2000 
2001  if (retval != ERROR_OK)
2002  goto err;
2003 
2004  /* Dummy address 0, only required for 8-line mode */
2005  if (IS_OCTOSPI && OPI_MODE) {
2006  retval = target_write_u32(target, io_base + SPI_AR, 0);
2007  if (retval != ERROR_OK)
2008  goto err;
2009  }
2010 
2011  /* for debugging only */
2012  uint32_t dummy;
2014 
2015  /* Read ID from Data Register */
2016  for (len1 = 0, len2 = 0; count > 0; --count) {
2017  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2019  retval = target_read_u8(target, io_base + SPI_DR, &byte);
2020  if (retval != ERROR_OK)
2021  goto err;
2022  /* collect 3 bytes without continuation codes */
2023  if ((byte != 0x7F) && (len1 < 3)) {
2024  *id1 = (*id1 >> 8) | ((uint32_t)byte) << 16;
2025  len1++;
2026  }
2027  }
2028  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2029  BIT(SPI_FSEL_FLASH))) != 0) {
2030  retval = target_read_u8(target, io_base + SPI_DR, &byte);
2031  if (retval != ERROR_OK)
2032  goto err;
2033  /* collect 3 bytes without continuation codes */
2034  if ((byte != 0x7F) && (len2 < 3)) {
2035  *id2 = (*id2 >> 8) | ((uint32_t)byte) << 16;
2036  len2++;
2037  }
2038  }
2039  }
2040 
2041  if (((*id1 != 0x000000) && (*id1 != 0xFFFFFF)) ||
2042  ((*id2 != 0x000000) && (*id2 != 0xFFFFFF)))
2043  break;
2044  }
2045 
2046  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2048  if ((*id1 == 0x000000) || (*id1 == 0xFFFFFF)) {
2049  /* no id retrieved, so id must be set manually */
2050  LOG_INFO("No id from flash1");
2051  retval = ERROR_FLASH_BANK_NOT_PROBED;
2052  }
2053  }
2054 
2055  if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
2056  if ((*id2 == 0x000000) || (*id2 == 0xFFFFFF)) {
2057  /* no id retrieved, so id must be set manually */
2058  LOG_INFO("No id from flash2");
2059  retval = ERROR_FLASH_BANK_NOT_PROBED;
2060  }
2061  }
2062 
2063 err:
2064  return retval;
2065 }
2066 
2067 static int stmqspi_probe(struct flash_bank *bank)
2068 {
2069  struct target *target = bank->target;
2070  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2071  struct flash_sector *sectors = NULL;
2072  uint32_t io_base = stmqspi_info->io_base;
2073  uint32_t id1 = 0, id2 = 0, data = 0;
2074  const struct flash_device *p;
2075  const uint32_t magic = 0xAEF1510E;
2076  unsigned int dual, fsize;
2077  bool octal_dtr;
2078  int retval;
2079 
2080  /* invalidate all flash device info */
2081  if (stmqspi_info->probed)
2082  free(bank->sectors);
2083  bank->size = 0;
2084  bank->num_sectors = 0;
2085  bank->sectors = NULL;
2086  stmqspi_info->sfdp_dummy1 = 0;
2087  stmqspi_info->sfdp_dummy2 = 0;
2088  stmqspi_info->probed = false;
2089  memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
2090  stmqspi_info->dev.name = "unknown";
2091 
2092  /* Abort any previous operation */
2093  retval = stmqspi_abort(bank);
2094  if (retval != ERROR_OK)
2095  return retval;
2096 
2097  /* Wait for busy to be cleared */
2098  retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
2099  if (retval != ERROR_OK)
2100  return retval;
2101 
2102  /* check whether QSPI_ABR is writeable and readback returns the value written */
2103  retval = target_write_u32(target, io_base + QSPI_ABR, magic);
2104  if (retval == ERROR_OK) {
2105  (void)target_read_u32(target, io_base + QSPI_ABR, &data);
2106  (void)target_write_u32(target, io_base + QSPI_ABR, 0);
2107  }
2108 
2109  if (data == magic) {
2110  LOG_DEBUG("QSPI_ABR register present");
2111  stmqspi_info->octo = false;
2112  } else {
2113  uint32_t magic_id;
2114 
2115  retval = target_read_u32(target, io_base + OCTOSPI_MAGIC, &magic_id);
2116 
2117  if (retval == ERROR_OK && magic_id == OCTO_MAGIC_ID) {
2118  LOG_DEBUG("OCTOSPI_MAGIC present");
2119  stmqspi_info->octo = true;
2120  } else {
2121  LOG_ERROR("No QSPI, no OCTOSPI at 0x%08" PRIx32, io_base);
2122  stmqspi_info->probed = false;
2123  stmqspi_info->dev.name = "none";
2124  return ERROR_FAIL;
2125  }
2126  }
2127 
2128  /* save current FSEL and DFM bits in QSPI/OCTOSPI_CR, current QSPI/OCTOSPI_CCR value */
2129  retval = target_read_u32(target, io_base + SPI_CR, &stmqspi_info->saved_cr);
2130  if (retval == ERROR_OK)
2131  retval = target_read_u32(target, io_base + SPI_CCR, &stmqspi_info->saved_ccr);
2132 
2133  if (IS_OCTOSPI) {
2134  uint32_t dcr1;
2135 
2136  retval = target_read_u32(target, io_base + OCTOSPI_DCR1, &dcr1);
2137 
2138  if (retval == ERROR_OK)
2139  retval = target_read_u32(target, io_base + OCTOSPI_TCR,
2140  &stmqspi_info->saved_tcr);
2141 
2142  if (retval == ERROR_OK)
2143  retval = target_read_u32(target, io_base + OCTOSPI_IR,
2144  &stmqspi_info->saved_ir);
2145 
2146  if (retval != ERROR_OK) {
2147  LOG_ERROR("No OCTOSPI at io_base 0x%08" PRIx32, io_base);
2148  stmqspi_info->probed = false;
2149  stmqspi_info->dev.name = "none";
2150  return ERROR_FAIL;
2151  }
2152 
2153  const uint32_t mtyp = (dcr1 & OCTOSPI_MTYP_MASK) >> OCTOSPI_MTYP_POS;
2154 
2155  if ((mtyp != 0x0) && (mtyp != 0x1)) {
2156  LOG_ERROR("Only regular SPI protocol supported in OCTOSPI");
2157  stmqspi_info->probed = false;
2158  stmqspi_info->dev.name = "none";
2159  return ERROR_FAIL;
2160  }
2161 
2162  LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
2163  PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
2164  stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
2165  } else {
2166  if (retval == ERROR_OK) {
2167  LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
2168  PRIx32 ", QSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
2169  stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
2170  if (stmqspi_info->saved_ccr & (1U << QSPI_DDRM))
2171  LOG_WARNING("DDR mode is untested and suffers from some silicon bugs");
2172  } else {
2173  LOG_ERROR("No QSPI at io_base 0x%08" PRIx32, io_base);
2174  stmqspi_info->probed = false;
2175  stmqspi_info->dev.name = "none";
2176  return ERROR_FAIL;
2177  }
2178  }
2179 
2180  dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
2181  octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
2182  if (dual || octal_dtr)
2183  bank->write_start_alignment = bank->write_end_alignment = 2;
2184  else
2185  bank->write_start_alignment = bank->write_end_alignment = 1;
2186 
2187  /* read and decode flash ID; returns in indirect mode */
2188  retval = read_flash_id(bank, &id1, &id2);
2189  LOG_DEBUG("id1 0x%06" PRIx32 ", id2 0x%06" PRIx32, id1, id2);
2190  if (retval == ERROR_FLASH_BANK_NOT_PROBED) {
2191  /* no id retrieved, so id must be set manually */
2192  LOG_INFO("No id - set flash parameters manually");
2193  retval = ERROR_OK;
2194  goto err;
2195  }
2196 
2197  if (retval != ERROR_OK)
2198  goto err;
2199 
2200  /* identify flash1 */
2201  for (p = flash_devices; id1 && p->name ; p++) {
2202  if (p->device_id == id1) {
2203  memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
2204  if (p->size_in_bytes / 4096)
2205  LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2206  " KiB", p->name, id1, p->size_in_bytes / 1024);
2207  else
2208  LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2209  " B", p->name, id1, p->size_in_bytes);
2210  break;
2211  }
2212  }
2213 
2214  if (id1 && !p->name) {
2215  /* chip not been identified by id, then try SFDP */
2216  struct flash_device temp;
2217  uint32_t saved_cr = stmqspi_info->saved_cr;
2218 
2219  /* select flash1 */
2220  stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~BIT(SPI_FSEL_FLASH);
2221  retval = spi_sfdp(bank, &temp, &read_sfdp_block);
2222 
2223  /* restore saved_cr */
2224  stmqspi_info->saved_cr = saved_cr;
2225 
2226  if (retval == ERROR_OK) {
2227  LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2228  " KiB", temp.name, id1, temp.size_in_bytes / 1024);
2229  /* save info and retrieved *good* id as spi_sfdp clears all info */
2230  memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev));
2231  stmqspi_info->dev.device_id = id1;
2232  } else {
2233  /* even not identified by SFDP, then give up */
2234  LOG_WARNING("Unknown flash1 device id = 0x%06" PRIx32
2235  " - set flash parameters manually", id1);
2236  retval = ERROR_OK;
2237  goto err;
2238  }
2239  }
2240 
2241  /* identify flash2 */
2242  for (p = flash_devices; id2 && p->name ; p++) {
2243  if (p->device_id == id2) {
2244  if (p->size_in_bytes / 4096)
2245  LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2246  " KiB", p->name, id2, p->size_in_bytes / 1024);
2247  else
2248  LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2249  " B", p->name, id2, p->size_in_bytes);
2250 
2251  if (!id1)
2252  memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
2253  else {
2254  if ((stmqspi_info->dev.read_cmd != p->read_cmd) ||
2255  (stmqspi_info->dev.qread_cmd != p->qread_cmd) ||
2256  (stmqspi_info->dev.pprog_cmd != p->pprog_cmd) ||
2257  (stmqspi_info->dev.erase_cmd != p->erase_cmd) ||
2258  (stmqspi_info->dev.chip_erase_cmd != p->chip_erase_cmd) ||
2259  (stmqspi_info->dev.sectorsize != p->sectorsize) ||
2260  (stmqspi_info->dev.size_in_bytes != p->size_in_bytes)) {
2261  LOG_ERROR("Incompatible flash1/flash2 devices");
2262  goto err;
2263  }
2264  /* page size is optional in SFDP, so accept smallest value */
2265  if (p->pagesize < stmqspi_info->dev.pagesize)
2266  stmqspi_info->dev.pagesize = p->pagesize;
2267  }
2268  break;
2269  }
2270  }
2271 
2272  if (id2 && !p->name) {
2273  /* chip not been identified by id, then try SFDP */
2274  struct flash_device temp;
2275  uint32_t saved_cr = stmqspi_info->saved_cr;
2276 
2277  /* select flash2 */
2278  stmqspi_info->saved_cr = stmqspi_info->saved_cr | BIT(SPI_FSEL_FLASH);
2279  retval = spi_sfdp(bank, &temp, &read_sfdp_block);
2280 
2281  /* restore saved_cr */
2282  stmqspi_info->saved_cr = saved_cr;
2283 
2284  if (retval == ERROR_OK)
2285  LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2286  " KiB", temp.name, id2, temp.size_in_bytes / 1024);
2287  else {
2288  /* even not identified by SFDP, then give up */
2289  LOG_WARNING("Unknown flash2 device id = 0x%06" PRIx32
2290  " - set flash parameters manually", id2);
2291  retval = ERROR_OK;
2292  goto err;
2293  }
2294 
2295  if (!id1)
2296  memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev));
2297  else {
2298  if ((stmqspi_info->dev.read_cmd != temp.read_cmd) ||
2299  (stmqspi_info->dev.qread_cmd != temp.qread_cmd) ||
2300  (stmqspi_info->dev.pprog_cmd != temp.pprog_cmd) ||
2301  (stmqspi_info->dev.erase_cmd != temp.erase_cmd) ||
2302  (stmqspi_info->dev.chip_erase_cmd != temp.chip_erase_cmd) ||
2303  (stmqspi_info->dev.sectorsize != temp.sectorsize) ||
2304  (stmqspi_info->dev.size_in_bytes != temp.size_in_bytes)) {
2305  LOG_ERROR("Incompatible flash1/flash2 devices");
2306  goto err;
2307  }
2308  /* page size is optional in SFDP, so accept smallest value */
2309  if (temp.pagesize < stmqspi_info->dev.pagesize)
2310  stmqspi_info->dev.pagesize = temp.pagesize;
2311  }
2312  }
2313 
2314  /* Set correct size value */
2315  bank->size = stmqspi_info->dev.size_in_bytes << dual;
2316 
2317  uint32_t dcr;
2318  retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
2319 
2320  if (retval != ERROR_OK)
2321  goto err;
2322 
2323  fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
2324 
2325  LOG_DEBUG("FSIZE = 0x%04x", fsize);
2326  if (bank->size == BIT((fsize + 1)))
2327  LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
2328  else if (bank->size == BIT((fsize + 0)))
2329  LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
2330  else
2331  LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
2332 
2333  /* if no sectors, then treat whole flash as single sector */
2334  if (stmqspi_info->dev.sectorsize == 0)
2335  stmqspi_info->dev.sectorsize = stmqspi_info->dev.size_in_bytes;
2336  /* if no page_size, then use sectorsize as page_size */
2337  if (stmqspi_info->dev.pagesize == 0)
2338  stmqspi_info->dev.pagesize = stmqspi_info->dev.sectorsize;
2339 
2340  /* create and fill sectors array */
2341  bank->num_sectors = stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
2342  sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2343  if (!sectors) {
2344  LOG_ERROR("not enough memory");
2345  retval = ERROR_FAIL;
2346  goto err;
2347  }
2348 
2349  for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
2350  sectors[sector].offset = sector * (stmqspi_info->dev.sectorsize << dual);
2351  sectors[sector].size = (stmqspi_info->dev.sectorsize << dual);
2352  sectors[sector].is_erased = -1;
2353  sectors[sector].is_protected = 0;
2354  }
2355 
2356  bank->sectors = sectors;
2357  stmqspi_info->probed = true;
2358 
2359 err:
2360  /* Switch to memory mapped mode before return to prompt */
2361  set_mm_mode(bank);
2362 
2363  return retval;
2364 }
2365 
2367 {
2368  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2369 
2370  if (stmqspi_info->probed)
2371  return ERROR_OK;
2373  return ERROR_OK;
2374 }
2375 
2377 {
2378  /* Nothing to do. Protection is only handled in SW. */
2379  return ERROR_OK;
2380 }
2381 
2383 {
2384  struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2385 
2386  if (!(stmqspi_info->probed)) {
2387  command_print_sameline(cmd, "\nQSPI flash bank not probed yet\n");
2389  }
2390 
2391  command_print_sameline(cmd, "flash%s%s \'%s\', device id = 0x%06" PRIx32
2392  ", flash size = %" PRIu32 "%s B\n(page size = %" PRIu32
2393  ", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
2394  ", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
2395  ", sector size = %" PRIu32 " %sB, sector_erase = 0x%02" PRIx8 ")",
2396  ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2397  BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
2398  ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2399  BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
2400  stmqspi_info->dev.name, stmqspi_info->dev.device_id,
2401  bank->size / 4096 ? bank->size / 1024 : bank->size,
2402  bank->size / 4096 ? "Ki" : "", stmqspi_info->dev.pagesize,
2403  stmqspi_info->dev.read_cmd, stmqspi_info->dev.qread_cmd,
2404  stmqspi_info->dev.pprog_cmd, stmqspi_info->dev.chip_erase_cmd,
2405  stmqspi_info->dev.sectorsize / 4096 ?
2406  stmqspi_info->dev.sectorsize / 1024 : stmqspi_info->dev.sectorsize,
2407  stmqspi_info->dev.sectorsize / 4096 ? "Ki" : "",
2408  stmqspi_info->dev.erase_cmd);
2409 
2410  return ERROR_OK;
2411 }
2412 
2413 static const struct command_registration stmqspi_exec_command_handlers[] = {
2414  {
2415  .name = "mass_erase",
2416  .handler = stmqspi_handle_mass_erase_command,
2417  .mode = COMMAND_EXEC,
2418  .usage = "bank_id",
2419  .help = "Mass erase entire flash device.",
2420  },
2421  {
2422  .name = "set",
2423  .handler = stmqspi_handle_set,
2424  .mode = COMMAND_EXEC,
2425  .usage = "bank_id name chip_size page_size read_cmd qread_cmd pprg_cmd "
2426  "[ mass_erase_cmd ] [ sector_size sector_erase_cmd ]",
2427  .help = "Set params of single flash chip",
2428  },
2429  {
2430  .name = "cmd",
2431  .handler = stmqspi_handle_cmd,
2432  .mode = COMMAND_EXEC,
2433  .usage = "bank_id num_resp cmd_byte ...",
2434  .help = "Send low-level command cmd_byte and following bytes or read num_resp.",
2435  },
2437 };
2438 
2439 static const struct command_registration stmqspi_command_handlers[] = {
2440  {
2441  .name = "stmqspi",
2442  .mode = COMMAND_ANY,
2443  .help = "stmqspi flash command group",
2444  .usage = "",
2446  },
2448 };
2449 
2450 struct flash_driver stmqspi_flash = {
2451  .name = "stmqspi",
2452  .commands = stmqspi_command_handlers,
2453  .flash_bank_command = stmqspi_flash_bank_command,
2454  .erase = stmqspi_erase,
2455  .protect = stmqspi_protect,
2456  .write = stmqspi_write,
2457  .read = stmqspi_read,
2458  .verify = stmqspi_verify,
2459  .probe = stmqspi_probe,
2460  .auto_probe = stmqspi_auto_probe,
2461  .erase_check = stmqspi_blank_check,
2462  .protect_check = stmqspi_protect_check,
2463  .info = get_stmqspi_info,
2464  .free_driver_priv = default_flash_free_driver_priv,
2465 };
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:86
enum arm_mode mode
Definition: armv4_5.c:277
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:218
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:450
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:117
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
uint8_t bank
Definition: esirisc.c:135
uint8_t type
Definition: esp_usb_jtag.c:0
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_PROTECTED
Definition: flash/common.h:37
#define ERROR_FLASH_SECTOR_INVALID
Definition: flash/common.h:29
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
Definition: flash/common.h:32
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
static uint16_t output
Definition: ftdi.c:118
int image_calculate_checksum(const uint8_t *buffer, uint32_t nbytes, uint32_t *checksum)
Definition: image.c:1254
void alive_sleep(uint64_t ms)
Definition: log.c:460
void keep_alive(void)
Definition: log.c:419
#define LOG_WARNING(expr ...)
Definition: log.h:120
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_INFO(expr ...)
Definition: log.h:117
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
uint32_t addr
Definition: nuttx.c:65
int spi_sfdp(struct flash_bank *bank, struct flash_device *dev, read_sfdp_block_t read_sfdp_block)
Definition: sfdp.c:61
const struct flash_device flash_devices[]
Definition: spi.c:24
#define SPIFLASH_READ_MID
Definition: spi.h:73
#define SPIFLASH_READ_SFDP
Definition: spi.h:80
#define SPIFLASH_READ_STATUS
Definition: spi.h:74
#define SPIFLASH_READ_ID
Definition: spi.h:72
#define SPIFLASH_WRITE_ENABLE
Definition: spi.h:75
#define SPIFLASH_WE_BIT
Definition: spi.h:69
#define SPIFLASH_DEF_PAGESIZE
Definition: spi.h:82
#define SPIFLASH_BSY_BIT
Definition: spi.h:67
#define BIT(nr)
Definition: stm32l4x.h:18
#define OCTOSPI_CCR_READ
Definition: stmqspi.c:97
#define OCTOSPI_CCR_SECTOR_ERASE
Definition: stmqspi.c:128
#define OCTOSPI_CCR_READ_STATUS
Definition: stmqspi.c:110
static int qspi_write_enable(struct flash_bank *bank)
Definition: stmqspi.c:419
#define OCTOSPI_CCR_WRITE_ENABLE
Definition: stmqspi.c:125
static int stmqspi_protect_check(struct flash_bank *bank)
Definition: stmqspi.c:2376
static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stmqspi.c:1668
static int octospi_cmd(struct flash_bank *bank, uint32_t mode, uint32_t ccr, uint32_t ir)
Definition: stmqspi.c:176
static int stmqspi_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: stmqspi.c:1048
#define OPI_MODE
Definition: stmqspi.c:91
#define QSPI_CCR_READ_STATUS
Definition: stmqspi.c:55
static int read_sfdp_block(struct flash_bank *bank, uint32_t addr, uint32_t words, uint32_t *buffer)
Definition: stmqspi.c:1809
static int stmqspi_probe(struct flash_bank *bank)
Definition: stmqspi.c:2067
static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count, bool write)
Definition: stmqspi.c:1366
COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
Definition: stmqspi.c:485
#define SPI_ADSIZE
Definition: stmqspi.c:137
#define OCTOSPI_CCR_READ_ID
Definition: stmqspi.c:114
#define OPI_CMD(cmd)
Definition: stmqspi.c:139
static int poll_busy(struct flash_bank *bank, int timeout)
Definition: stmqspi.c:234
#define QSPI_CCR_READ_SFDP
Definition: stmqspi.c:68
#define QSPI_CCR_READ
Definition: stmqspi.c:51
static int log2u(uint32_t word)
Definition: stmqspi.c:596
#define OCTOSPI_MODE
Definition: stmqspi.c:89
#define OPI_DUMMY
Definition: stmqspi.c:107
#define SPI_PROBE_TIMEOUT
Definition: stmqspi.c:152
#define QSPI_CCR_READ_MID
Definition: stmqspi.c:63
#define SPI_MASS_ERASE_TIMEOUT
Definition: stmqspi.c:154
#define QSPI_MODE
Definition: stmqspi.c:46
#define OCTOSPI_CCR_MASS_ERASE
Definition: stmqspi.c:131
#define OCTOSPI_MODE_CCR
Definition: stmqspi.c:93
static int qspi_verify(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stmqspi.c:1243
static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stmqspi.c:1607
static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
Definition: stmqspi.c:924
static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
Definition: stmqspi.c:1936
static int read_status_reg(struct flash_bank *bank, uint16_t *status)
Definition: stmqspi.c:323
#define QSPI_CCR_MASS_ERASE
Definition: stmqspi.c:80
#define SPI_CMD_TIMEOUT
Definition: stmqspi.c:151
static const struct command_registration stmqspi_exec_command_handlers[]
Definition: stmqspi.c:2413
static int set_mm_mode(struct flash_bank *bank)
Definition: stmqspi.c:277
static int stmqspi_blank_check(struct flash_bank *bank)
Definition: stmqspi.c:1063
static uint32_t h_to_le_32(uint32_t val)
Definition: stmqspi.c:142
static int wait_till_ready(struct flash_bank *bank, int timeout)
Definition: stmqspi.c:396
#define OCTOSPI_CCR_READ_MID
Definition: stmqspi.c:118
#define OCTOSPI_CCR_READ_SFDP(len)
Definition: stmqspi.c:121
FLASH_BANK_COMMAND_HANDLER(stmqspi_flash_bank_command)
Definition: stmqspi.c:205
#define QSPI_CCR_READ_ID
Definition: stmqspi.c:59
#define OCTOSPI_CCR_PAGE_PROG
Definition: stmqspi.c:134
static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stmqspi.c:1569
#define SPI_MAX_TIMEOUT
Definition: stmqspi.c:153
static const struct command_registration stmqspi_command_handlers[]
Definition: stmqspi.c:2439
static int stmqspi_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: stmqspi.c:995
static int stmqspi_auto_probe(struct flash_bank *bank)
Definition: stmqspi.c:2366
static int get_stmqspi_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: stmqspi.c:2382
#define QSPI_CCR_WRITE_ENABLE
Definition: stmqspi.c:72
struct flash_driver stmqspi_flash
Definition: stmqspi.c:2450
#define QSPI_CCR_PAGE_PROG
Definition: stmqspi.c:84
#define QSPI_CCR_SECTOR_ERASE
Definition: stmqspi.c:76
static int stmqspi_abort(struct flash_bank *bank)
Definition: stmqspi.c:261
static int find_sfdp_dummy(struct flash_bank *bank, int len)
Definition: stmqspi.c:1718
#define OCTOSPI_ADDR4
Definition: stmqspi.h:93
#define OCTOSPI_CR
Definition: stmqspi.h:58
#define OCTOSPI_CCR
Definition: stmqspi.h:67
#define OCTOSPI_DCR1
Definition: stmqspi.h:59
#define SPI_DR
Definition: stmqspi.h:111
#define OCTOSPI_READ_MODE
Definition: stmqspi.h:78
#define OCTOSPI_NO_ALTB
Definition: stmqspi.h:90
#define SPI_AR
Definition: stmqspi.h:110
#define SPI_CR
Definition: stmqspi.h:105
#define SPI_CCR
Definition: stmqspi.h:112
#define OCTOSPI_TCR
Definition: stmqspi.h:68
#define OCTOSPI_NO_ADDR
Definition: stmqspi.h:91
#define OCTOSPI_DCYC_MASK
Definition: stmqspi.h:102
#define OCTOSPI_WRITE_MODE
Definition: stmqspi.h:77
#define SPI_DMODE_POS
Definition: stmqspi.h:40
#define SPI_DUAL_FLASH
Definition: stmqspi.h:26
#define SPI_DLR
Definition: stmqspi.h:109
#define IS_OCTOSPI
Definition: stmqspi.h:104
#define QSPI_ADDR4
Definition: stmqspi.h:55
#define SPI_TCF
Definition: stmqspi.h:36
#define OCTOSPI_IR
Definition: stmqspi.h:69
#define QSPI_NO_ALTB
Definition: stmqspi.h:52
#define OCTO_MAGIC_ID
Definition: stmqspi.h:74
#define OCTOSPI_NO_DATA
Definition: stmqspi.h:89
#define OCTOSPI_DDTR
Definition: stmqspi.h:95
#define SPI_FCR
Definition: stmqspi.h:108
#define QSPI_NO_DATA
Definition: stmqspi.h:51
#define OCTOSPI_DCYC_POS
Definition: stmqspi.h:100
#define QSPI_WRITE_MODE
Definition: stmqspi.h:46
#define SPI_ADSIZE_POS
Definition: stmqspi.h:44
#define OCTOSPI_MAGIC
Definition: stmqspi.h:72
#define SPI_FSIZE_LEN
Definition: stmqspi.h:31
#define SPI_FSEL_FLASH
Definition: stmqspi.h:25
#define OCTOSPI_MM_MODE
Definition: stmqspi.h:79
#define SPI_FSIZE_POS
Definition: stmqspi.h:30
#define QSPI_CCR
Definition: stmqspi.h:19
#define OCTOSPI_MTYP_MASK
Definition: stmqspi.h:84
#define QSPI_NO_ADDR
Definition: stmqspi.h:53
#define SPI_SR
Definition: stmqspi.h:107
#define QSPI_DCYC_MASK
Definition: stmqspi.h:43
#define QSPI_ABR
Definition: stmqspi.h:21
#define SPI_BUSY
Definition: stmqspi.h:34
#define OCTOSPI_NO_DDTR
Definition: stmqspi.h:96
#define SPI_ABORT
Definition: stmqspi.h:27
#define QSPI_DDRM
Definition: stmqspi.h:39
#define QSPI_READ_MODE
Definition: stmqspi.h:47
#define OCTOSPI_MTYP_POS
Definition: stmqspi.h:82
#define SPI_DCR
Definition: stmqspi.h:106
#define QSPI_CR
Definition: stmqspi.h:14
unsigned int common_magic
Definition: armv7m.h:293
enum arm_mode core_mode
Definition: armv7m.h:295
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:229
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
uint8_t read_cmd
Definition: spi.h:22
uint32_t sectorsize
Definition: spi.h:29
uint32_t device_id
Definition: spi.h:27
uint8_t chip_erase_cmd
Definition: spi.h:26
const char * name
Definition: spi.h:21
uint32_t pagesize
Definition: spi.h:28
uint32_t size_in_bytes
Definition: spi.h:30
uint8_t pprog_cmd
Definition: spi.h:24
uint8_t erase_cmd
Definition: spi.h:25
uint8_t qread_cmd
Definition: spi.h:23
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
int is_erased
Indication of erasure status: 0 = not erased, 1 = erased, other = unknown.
Definition: nor/core.h:42
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
Definition: nor/core.h:55
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
uint32_t result
Definition: stmqspi.c:159
uint32_t offset
Definition: stmqspi.c:157
uint32_t size
Definition: stmqspi.c:158
uint32_t saved_tcr
Definition: stmqspi.c:170
uint32_t saved_ccr
Definition: stmqspi.c:169
unsigned int sfdp_dummy2
Definition: stmqspi.c:173
unsigned int sfdp_dummy1
Definition: stmqspi.c:172
uint32_t saved_cr
Definition: stmqspi.c:168
char devname[32]
Definition: stmqspi.c:164
uint32_t saved_ir
Definition: stmqspi.c:171
uint32_t io_base
Definition: stmqspi.c:167
struct flash_device dev
Definition: stmqspi.c:166
Definition: target.h:120
enum target_state state
Definition: target.h:162
Definition: psoc6.c:84
target_addr_t address
Definition: target.h:90
int target_run_read_async_algorithm(struct target *target, uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
This routine is a wrapper for asynchronous algorithms.
Definition: target.c:1156
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2408
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
Definition: target.c:2749
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2473
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2664
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2233
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2187
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:846
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2035
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:1003
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2616
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:792
@ TARGET_HALTED
Definition: target.h:55
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:796
float duration_elapsed(const struct duration *duration)
Definition: time_support.c:83
int duration_measure(struct duration *duration)
Update the duration->elapsed field to finish the duration measurement.
Definition: time_support.c:74
int duration_start(struct duration *duration)
Update the duration->start field to start the duration measurement.
Definition: time_support.c:69
float duration_kbps(const struct duration *duration, size_t count)
Definition: time_support.c:90
int64_t timeval_ms(void)
#define TARGET_ADDR_FMT
Definition: types.h:342
static void h_u32_to_le(uint8_t *buf, uint32_t val)
Definition: types.h:178
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
static uint32_t le_to_h_u32(const uint8_t *buf)
Definition: types.h:112
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t dummy[96]
Definition: vdebug.c:23
uint8_t count[4]
Definition: vdebug.c:22