OpenOCD
riscv.h File Reference
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Data Structures

struct  range_list_t
 
struct  riscv_bscan_tunneled_scan_context_t
 
struct  riscv_info
 
struct  riscv_reg_info_t
 
struct  riscv_sample_buf
 
struct  riscv_sample_config_t
 
struct  virt2phys_info_t
 

Macros

#define DEFAULT_COMMAND_TIMEOUT_SEC   2
 
#define DEFAULT_RESET_TIMEOUT_SEC   30
 
#define PG_MAX_LEVEL   4
 
#define RISCV_COMMON_MAGIC   0x52495356U
 
#define RISCV_INFO(R)   struct riscv_info *R = riscv_info(target);
 
#define RISCV_MAX_HARTS   1024
 
#define RISCV_MAX_HWBPS   16
 
#define RISCV_MAX_REGISTERS   5000
 
#define RISCV_MAX_TRIGGERS   32
 
#define RISCV_NUM_MEM_ACCESS_METHODS   3
 
#define RISCV_PGSHIFT   12
 
#define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER   0x81
 
#define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE   0x80
 
#define RISCV_SATP_MODE(xlen)   ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
 
#define RISCV_SATP_PPN(xlen)   ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
 

Typedefs

typedef uint64_t riscv_addr_t
 
typedef uint32_t riscv_insn_t
 
typedef uint64_t riscv_reg_t
 

Enumerations

enum  bscan_tunnel_type_t { BSCAN_TUNNEL_NESTED_TAP , BSCAN_TUNNEL_DATA_REGISTER }
 
enum  riscv_halt_reason {
  RISCV_HALT_INTERRUPT , RISCV_HALT_BREAKPOINT , RISCV_HALT_SINGLESTEP , RISCV_HALT_TRIGGER ,
  RISCV_HALT_UNKNOWN , RISCV_HALT_GROUP , RISCV_HALT_ERROR
}
 
enum  riscv_mem_access_method { RISCV_MEM_ACCESS_UNSPECIFIED , RISCV_MEM_ACCESS_PROGBUF , RISCV_MEM_ACCESS_SYSBUS , RISCV_MEM_ACCESS_ABSTRACT }
 

Functions

 COMMAND_HELPER (riscv_print_info_line, const char *section, const char *key, unsigned int value)
 
uint32_t dtmcontrol_scan_via_bscan (struct target *target, uint32_t out)
 
static bool is_riscv (const struct riscv_info *riscv_info)
 
void riscv_add_bscan_tunneled_scan (struct target *target, struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt)
 
int riscv_add_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
int riscv_count_harts (struct target *target)
 
int riscv_current_hartid (const struct target *target)
 
size_t riscv_debug_buffer_size (struct target *target)
 
int riscv_dmi_write_u64_bits (struct target *target)
 
int riscv_enumerate_triggers (struct target *target)
 Count triggers, and initialize trigger_count for each hart. More...
 
int riscv_execute_debug_buffer (struct target *target)
 
void riscv_fill_dmi_nop_u64 (struct target *target, char *buf)
 
void riscv_fill_dmi_read_u64 (struct target *target, char *buf, int a)
 
void riscv_fill_dmi_write_u64 (struct target *target, char *buf, int a, uint64_t d)
 
int riscv_get_register (struct target *target, riscv_reg_t *value, enum gdb_regno r)
 Get register, from the cache if it's in there. More...
 
int riscv_halt (struct target *target)
 
static struct riscv_inforiscv_info (const struct target *target) __attribute__((unused))
 
int riscv_init_registers (struct target *target)
 
bool riscv_is_halted (struct target *target)
 
int riscv_openocd_assert_reset (struct target *target)
 
int riscv_openocd_deassert_reset (struct target *target)
 
int riscv_openocd_poll (struct target *target)
 
int riscv_openocd_step (struct target *target, int current, target_addr_t address, int handle_breakpoints)
 
int riscv_read_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 Read one memory item using any memory access size that will work. More...
 
riscv_insn_t riscv_read_debug_buffer (struct target *target, int index)
 
int riscv_remove_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
int riscv_select_current_hart (struct target *target)
 
enum semihosting_result riscv_semihosting (struct target *target, int *retval)
 Check for and process a semihosting request using the ARM protocol). More...
 
void riscv_semihosting_init (struct target *target)
 Initialize RISC-V semihosting. More...
 
int riscv_set_current_hartid (struct target *target, int hartid)
 
int riscv_set_register (struct target *target, enum gdb_regno i, riscv_reg_t v)
 Set register, updating the cache. More...
 
bool riscv_supports_extension (struct target *target, char letter)
 
int riscv_write_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 Write one memory item using any memory access size that will work. More...
 
int riscv_write_debug_buffer (struct target *target, int index, riscv_insn_t insn)
 
unsigned riscv_xlen (const struct target *target)
 
int riscv_xlen_of_hart (const struct target *target)
 
void select_dmi_via_bscan (struct target *target)
 

Variables

int bscan_tunnel_ir_width
 
struct scan_fieldbscan_tunneled_select_dmi
 
uint32_t bscan_tunneled_select_dmi_num_fields
 
struct target_type riscv011_target
 
struct target_type riscv013_target
 
int riscv_command_timeout_sec
 
bool riscv_ebreakm
 
bool riscv_ebreaks
 
bool riscv_ebreaku
 
bool riscv_enable_virtual
 
int riscv_reset_timeout_sec
 
struct scan_field select_dbus
 
struct scan_field select_dtmcontrol
 
struct scan_field select_idcode
 

Macro Definition Documentation

◆ DEFAULT_COMMAND_TIMEOUT_SEC

#define DEFAULT_COMMAND_TIMEOUT_SEC   2

Definition at line 24 of file riscv.h.

◆ DEFAULT_RESET_TIMEOUT_SEC

#define DEFAULT_RESET_TIMEOUT_SEC   30

Definition at line 25 of file riscv.h.

◆ PG_MAX_LEVEL

#define PG_MAX_LEVEL   4

Definition at line 31 of file riscv.h.

◆ RISCV_COMMON_MAGIC

#define RISCV_COMMON_MAGIC   0x52495356U

Definition at line 16 of file riscv.h.

◆ RISCV_INFO

#define RISCV_INFO (   R)    struct riscv_info *R = riscv_info(target);

Definition at line 274 of file riscv.h.

◆ RISCV_MAX_HARTS

#define RISCV_MAX_HARTS   1024

Definition at line 19 of file riscv.h.

◆ RISCV_MAX_HWBPS

#define RISCV_MAX_HWBPS   16

Definition at line 22 of file riscv.h.

◆ RISCV_MAX_REGISTERS

#define RISCV_MAX_REGISTERS   5000

Definition at line 20 of file riscv.h.

◆ RISCV_MAX_TRIGGERS

#define RISCV_MAX_TRIGGERS   32

Definition at line 21 of file riscv.h.

◆ RISCV_NUM_MEM_ACCESS_METHODS

#define RISCV_NUM_MEM_ACCESS_METHODS   3

Definition at line 33 of file riscv.h.

◆ RISCV_PGSHIFT

#define RISCV_PGSHIFT   12

Definition at line 29 of file riscv.h.

◆ RISCV_SAMPLE_BUF_TIMESTAMP_AFTER

#define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER   0x81

Definition at line 68 of file riscv.h.

◆ RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE

#define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE   0x80

Definition at line 67 of file riscv.h.

◆ RISCV_SATP_MODE

#define RISCV_SATP_MODE (   xlen)    ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)

Definition at line 27 of file riscv.h.

◆ RISCV_SATP_PPN

#define RISCV_SATP_PPN (   xlen)    ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)

Definition at line 28 of file riscv.h.

Typedef Documentation

◆ riscv_addr_t

typedef uint64_t riscv_addr_t

Definition at line 43 of file riscv.h.

◆ riscv_insn_t

typedef uint32_t riscv_insn_t

Definition at line 42 of file riscv.h.

◆ riscv_reg_t

typedef uint64_t riscv_reg_t

Definition at line 41 of file riscv.h.

Enumeration Type Documentation

◆ bscan_tunnel_type_t

Enumerator
BSCAN_TUNNEL_NESTED_TAP 
BSCAN_TUNNEL_DATA_REGISTER 

Definition at line 287 of file riscv.h.

◆ riscv_halt_reason

Enumerator
RISCV_HALT_INTERRUPT 
RISCV_HALT_BREAKPOINT 
RISCV_HALT_SINGLESTEP 
RISCV_HALT_TRIGGER 
RISCV_HALT_UNKNOWN 
RISCV_HALT_GROUP 
RISCV_HALT_ERROR 

Definition at line 52 of file riscv.h.

◆ riscv_mem_access_method

Enumerator
RISCV_MEM_ACCESS_UNSPECIFIED 
RISCV_MEM_ACCESS_PROGBUF 
RISCV_MEM_ACCESS_SYSBUS 
RISCV_MEM_ACCESS_ABSTRACT 

Definition at line 45 of file riscv.h.

Function Documentation

◆ COMMAND_HELPER()

COMMAND_HELPER ( riscv_print_info_line  ,
const char *  section,
const char *  key,
unsigned int  value 
)

Definition at line 2902 of file riscv.c.

References CMD, and command_print().

◆ dtmcontrol_scan_via_bscan()

◆ is_riscv()

static bool is_riscv ( const struct riscv_info riscv_info)
inlinestatic

Definition at line 276 of file riscv.h.

References riscv_info::common_magic, and RISCV_COMMON_MAGIC.

Referenced by fespi_write().

◆ riscv_add_bscan_tunneled_scan()

◆ riscv_add_watchpoint()

int riscv_add_watchpoint ( struct target target,
struct watchpoint watchpoint 
)

Definition at line 988 of file riscv.c.

References add_trigger(), ERROR_OK, watchpoint::is_set, and trigger_from_watchpoint().

Referenced by enable_triggers(), and strict_step().

◆ riscv_count_harts()

int riscv_count_harts ( struct target target)

Definition at line 3328 of file riscv.c.

References RISCV_INFO.

Referenced by deassert_reset(), and examine().

◆ riscv_current_hartid()

int riscv_current_hartid ( const struct target target)

◆ riscv_debug_buffer_size()

size_t riscv_debug_buffer_size ( struct target target)

Definition at line 3474 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_ebreak(), riscv_program_exec(), and riscv_program_insert().

◆ riscv_dmi_write_u64_bits()

int riscv_dmi_write_u64_bits ( struct target target)

Definition at line 3517 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().

◆ riscv_enumerate_triggers()

int riscv_enumerate_triggers ( struct target target)

Count triggers, and initialize trigger_count for each hart.

trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.

Definition at line 3530 of file riscv.c.

References ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, get_field, LOG_DEBUG, LOG_INFO, MCONTROL_DMODE, MCONTROL_TYPE, riscv_get_register(), RISCV_INFO, RISCV_MAX_TRIGGERS, riscv_set_register(), riscv_xlen(), target_name(), and type.

Referenced by add_trigger(), COMMAND_HANDLER(), disable_triggers(), handle_halt(), register_set(), and remove_trigger().

◆ riscv_execute_debug_buffer()

int riscv_execute_debug_buffer ( struct target target)

Definition at line 3493 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_exec().

◆ riscv_fill_dmi_nop_u64()

void riscv_fill_dmi_nop_u64 ( struct target target,
char *  buf 
)

Definition at line 3511 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().

◆ riscv_fill_dmi_read_u64()

void riscv_fill_dmi_read_u64 ( struct target target,
char *  buf,
int  a 
)

Definition at line 3505 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read().

◆ riscv_fill_dmi_write_u64()

void riscv_fill_dmi_write_u64 ( struct target target,
char *  buf,
int  a,
uint64_t  d 
)

Definition at line 3499 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_write().

◆ riscv_get_register()

◆ riscv_halt()

◆ riscv_info()

static struct riscv_info * riscv_info ( const struct target target)
inlinestatic

◆ riscv_init_registers()

int riscv_init_registers ( struct target target)

Definition at line 3873 of file riscv.c.

References reg::arch_info, ARRAY_SIZE, reg::caller_save, cmp_csr_info(), CSR_CYCLEH, CSR_FCSR, CSR_FFLAGS, CSR_FRM, CSR_HPMCOUNTER10H, CSR_HPMCOUNTER11H, CSR_HPMCOUNTER12H, CSR_HPMCOUNTER13H, CSR_HPMCOUNTER14H, CSR_HPMCOUNTER15H, CSR_HPMCOUNTER16H, CSR_HPMCOUNTER17H, CSR_HPMCOUNTER18H, CSR_HPMCOUNTER19H, CSR_HPMCOUNTER20H, CSR_HPMCOUNTER21H, CSR_HPMCOUNTER22H, CSR_HPMCOUNTER23H, CSR_HPMCOUNTER24H, CSR_HPMCOUNTER25H, CSR_HPMCOUNTER26H, CSR_HPMCOUNTER27H, CSR_HPMCOUNTER28H, CSR_HPMCOUNTER29H, CSR_HPMCOUNTER30H, CSR_HPMCOUNTER31H, CSR_HPMCOUNTER3H, CSR_HPMCOUNTER4H, CSR_HPMCOUNTER5H, CSR_HPMCOUNTER6H, CSR_HPMCOUNTER7H, CSR_HPMCOUNTER8H, CSR_HPMCOUNTER9H, CSR_INSTRETH, CSR_MCYCLEH, CSR_MEDELEG, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MIDELEG, CSR_MINSTRETH, CSR_PMPCFG1, CSR_PMPCFG3, CSR_SATP, CSR_SCAUSE, CSR_SCOUNTEREN, CSR_SEPC, CSR_SIE, CSR_SIP, CSR_SSCRATCH, CSR_SSTATUS, CSR_STVAL, CSR_STVEC, CSR_TIMEH, CSR_VL, CSR_VLENB, CSR_VSTART, CSR_VTYPE, CSR_VXRM, CSR_VXSAT, reg::dirty, DIV_ROUND_UP, ERROR_FAIL, ERROR_OK, reg::exist, reg::feature, reg_data_type_union::fields, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2, GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6, GDB_REGNO_A7, GDB_REGNO_COUNT, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_FA0, GDB_REGNO_FA1, GDB_REGNO_FA2, GDB_REGNO_FA3, GDB_REGNO_FA4, GDB_REGNO_FA5, GDB_REGNO_FA6, GDB_REGNO_FA7, GDB_REGNO_FP, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_FS0, GDB_REGNO_FS1, GDB_REGNO_FS10, GDB_REGNO_FS11, GDB_REGNO_FS2, GDB_REGNO_FS3, GDB_REGNO_FS4, GDB_REGNO_FS5, GDB_REGNO_FS6, GDB_REGNO_FS7, GDB_REGNO_FS8, GDB_REGNO_FS9, GDB_REGNO_FT0, GDB_REGNO_FT1, GDB_REGNO_FT10, GDB_REGNO_FT11, GDB_REGNO_FT2, GDB_REGNO_FT3, GDB_REGNO_FT4, GDB_REGNO_FT5, GDB_REGNO_FT6, GDB_REGNO_FT7, GDB_REGNO_FT8, GDB_REGNO_FT9, GDB_REGNO_GP, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_RA, GDB_REGNO_S1, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4, GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8, GDB_REGNO_S9, GDB_REGNO_SP, GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_T3, GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6, GDB_REGNO_TP, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_XPR15, GDB_REGNO_XPR31, GDB_REGNO_ZERO, reg::group, range_list_t::high, info, list_empty(), list_first_entry, list_for_each_entry, list_rotate_left(), LOG_DEBUG, range_list_t::low, reg_feature::name, reg::name, reg_cache::name, csr_info::name, range_list_t::name, NULL, reg_cache::num_regs, number, reg::number, target::reg_cache, reg::reg_data_type, reg_cache::reg_list, REG_TYPE_ARCH_DEFINED, REG_TYPE_CLASS_UNION, REG_TYPE_CLASS_VECTOR, REG_TYPE_IEEE_DOUBLE, REG_TYPE_IEEE_SINGLE, REG_TYPE_UINT128, REG_TYPE_UINT16, REG_TYPE_UINT32, REG_TYPE_UINT64, REG_TYPE_UINT8, riscv_free_registers(), RISCV_INFO, riscv_reg_arch_type, riscv_supports_extension(), riscv_xlen(), reg::size, target, riscv_reg_info_t::target, reg_data_type::type, reg::type, reg::valid, and reg::value.

Referenced by examine(), and init_target().

◆ riscv_is_halted()

◆ riscv_openocd_assert_reset()

int riscv_openocd_assert_reset ( struct target target)

◆ riscv_openocd_deassert_reset()

int riscv_openocd_deassert_reset ( struct target target)

◆ riscv_openocd_poll()

◆ riscv_openocd_step()

◆ riscv_read_by_any_size()

int riscv_read_by_any_size ( struct target target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer 
)

Read one memory item using any memory access size that will work.

Read larger section of memory and pick out the required portion, if needed.

Definition at line 837 of file riscv.c.

References buffer, ERROR_FAIL, ERROR_OK, read_by_given_size(), and size.

Referenced by riscv_add_breakpoint().

◆ riscv_read_debug_buffer()

riscv_insn_t riscv_read_debug_buffer ( struct target target,
int  index 
)

Definition at line 3487 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_exec().

◆ riscv_remove_watchpoint()

int riscv_remove_watchpoint ( struct target target,
struct watchpoint watchpoint 
)

◆ riscv_select_current_hart()

◆ riscv_semihosting()

enum semihosting_result riscv_semihosting ( struct target target,
int *  retval 
)

Check for and process a semihosting request using the ARM protocol).

This is meant to be called when the target is stopped due to a debug mode entry.

Parameters
targetPointer to the target to process.
retvalPointer to a location where the return code will be stored
Returns
non-zero value if a request was processed or an error encountered

Definition at line 42 of file riscv_semihosting.c.

References riscv_semihosting_post_result(), riscv_semihosting_setup(), and semihosting_common_init().

Referenced by handle_halt(), and riscv_openocd_poll().

◆ riscv_semihosting_init()

void riscv_semihosting_init ( struct target target)

Initialize RISC-V semihosting.

Use common ARM code.

Definition at line 42 of file riscv_semihosting.c.

Referenced by riscv_init_target().

◆ riscv_set_current_hartid()

int riscv_set_current_hartid ( struct target target,
int  hartid 
)

Definition at line 3296 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, riscv_current_hartid(), and RISCV_INFO.

Referenced by examine(), and riscv_select_current_hart().

◆ riscv_set_register()

◆ riscv_supports_extension()

bool riscv_supports_extension ( struct target target,
char  letter 
)

◆ riscv_write_by_any_size()

int riscv_write_by_any_size ( struct target target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer 
)

Write one memory item using any memory access size that will work.

Utilize read-modify-write, if needed.

Definition at line 805 of file riscv.c.

References buffer, ERROR_FAIL, ERROR_OK, size, and write_by_given_size().

Referenced by riscv_add_breakpoint(), and riscv_remove_breakpoint().

◆ riscv_write_debug_buffer()

int riscv_write_debug_buffer ( struct target target,
int  index,
riscv_insn_t  insn 
)

Definition at line 3480 of file riscv.c.

References ERROR_OK, and RISCV_INFO.

Referenced by riscv_program_write().

◆ riscv_xlen()

◆ riscv_xlen_of_hart()

int riscv_xlen_of_hart ( const struct target target)

◆ select_dmi_via_bscan()

Variable Documentation

◆ bscan_tunnel_ir_width

◆ bscan_tunneled_select_dmi

struct scan_field* bscan_tunneled_select_dmi
extern

◆ bscan_tunneled_select_dmi_num_fields

uint32_t bscan_tunneled_select_dmi_num_fields
extern

◆ riscv011_target

struct target_type riscv011_target
extern

Definition at line 2371 of file riscv-011.c.

Referenced by get_target_type().

◆ riscv013_target

struct target_type riscv013_target
extern

Definition at line 4047 of file riscv-013.c.

Referenced by get_target_type().

◆ riscv_command_timeout_sec

◆ riscv_ebreakm

bool riscv_ebreakm
extern

Definition at line 209 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_ebreaks

bool riscv_ebreaks
extern

Definition at line 210 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_ebreaku

bool riscv_ebreaku
extern

Definition at line 211 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_enable_virtual

bool riscv_enable_virtual
extern

◆ riscv_reset_timeout_sec

int riscv_reset_timeout_sec
extern

Definition at line 206 of file riscv.c.

Referenced by COMMAND_HANDLER(), and deassert_reset().

◆ select_dbus

◆ select_dtmcontrol

struct scan_field select_dtmcontrol
extern

Definition at line 112 of file riscv.c.

Referenced by dtmcontrol_scan(), and riscv_init_target().

◆ select_idcode

struct scan_field select_idcode
extern

Definition at line 122 of file riscv.c.

Referenced by idcode_scan(), and riscv_init_target().