nds32.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */
 
/***************************************************************************
 *   Copyright (C) 2013 Andes Technology                                   *
 *   Hsiangkai Wang <hkwang@andestech.com>                                 *
 ***************************************************************************/
 
#ifndef OPENOCD_TARGET_NDS32_H
#define OPENOCD_TARGET_NDS32_H
 
#include <jtag/jtag.h>
#include "target.h"
#include "target_type.h"
#include "register.h"
#include "breakpoints.h"
#include "nds32_reg.h"
#include "nds32_insn.h"
#include "nds32_edm.h"
 
#define NDS32_EDM_OPERATION_MAX_NUM 64
 
#define CHECK_RETVAL(action)            \
    do {                    \
        int __retval = (action);    \
        if (__retval != ERROR_OK) { \
            LOG_DEBUG("error while calling \"%s\"", \
                # action);     \
            return __retval;    \
        }               \
    } while (0)
 
extern const char *nds32_debug_type_name[11];
 
enum nds32_debug_reason {
    NDS32_DEBUG_BREAK = 0,
    NDS32_DEBUG_BREAK_16,
    NDS32_DEBUG_INST_BREAK,
    NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE,
    NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE,
    NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE,
    NDS32_DEBUG_DEBUG_INTERRUPT,
    NDS32_DEBUG_HARDWARE_SINGLE_STEP,
    NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE,
    NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE,
    NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
};
 
#define NDS32_STRUCT_STAT_SIZE 60
#define NDS32_STRUCT_TIMEVAL_SIZE 8
 
enum nds32_syscall_id {
    NDS32_SYSCALL_UNDEFINED = 0,
    NDS32_SYSCALL_EXIT = 1,
    NDS32_SYSCALL_OPEN = 2,
    NDS32_SYSCALL_CLOSE = 3,
    NDS32_SYSCALL_READ = 4,
    NDS32_SYSCALL_WRITE = 5,
    NDS32_SYSCALL_LSEEK = 6,
    NDS32_SYSCALL_UNLINK = 7,
    NDS32_SYSCALL_RENAME = 3001,
    NDS32_SYSCALL_FSTAT = 10,
    NDS32_SYSCALL_STAT = 15,
    NDS32_SYSCALL_GETTIMEOFDAY = 19,
    NDS32_SYSCALL_ISATTY = 3002,
    NDS32_SYSCALL_SYSTEM = 3003,
    NDS32_SYSCALL_ERRNO = 6001,
};
 
#define NDS32_COMMON_MAGIC 0xADE5ADE5U
 
struct nds32_edm {
 
    int version;
 
    int breakpoint_num;
 
    bool direct_access_local_memory;
 
    bool access_control;
 
    bool support_max_stop;
};
 
struct nds32_cache {
 
    bool enable;
 
    int set;
 
    int way;
 
    int line_size;
 
    bool lock_support;
};
 
struct nds32_memory {
 
    struct nds32_cache icache;
 
    struct nds32_cache dcache;
 
    int ilm_base;
 
    int ilm_size;
 
    int ilm_align_ver;
 
    bool ilm_enable;
 
    int ilm_start;
 
    int ilm_end;
 
    int dlm_base;
 
    int dlm_size;
 
    int dlm_align_ver;
 
    bool dlm_enable;
 
    int dlm_start;
 
    int dlm_end;
 
    enum nds_memory_access access_channel;
 
    enum nds_memory_select mode;
 
    bool address_translation;
};
 
struct nds32_cpu_version {
    bool performance_extension;
    bool _16bit_extension;
    bool performance_extension_2;
    bool cop_fpu_extension;
    bool string_extension;
 
    int revision;
    int cpu_id_family;
    int cpu_id_version;
};
 
struct nds32_mmu_config {
    int memory_protection;
    int memory_protection_version;
    bool fully_associative_tlb;
    int tlb_size;
    int tlb_ways;
    int tlb_sets;
    bool _8k_page_support;
    int extra_page_size_support;
    bool tlb_lock;
    bool hardware_page_table_walker;
    bool default_endian;
    int partition_num;
    bool invisible_tlb;
    bool vlpt;
    bool ntme;
    bool drde;
    int default_min_page_size;
    bool multiple_page_size_in_use;
};
 
struct nds32_misc_config {
    bool edm;
    bool local_memory_dma;
    bool performance_monitor;
    bool high_speed_memory_port;
    bool debug_tracer;
    bool div_instruction;
    bool mac_instruction;
    int audio_isa;
    bool l2_cache;
    bool reduce_register;
    bool addr_24;
    bool interruption_level;
    int baseline_instruction;
    bool no_dx_register;
    bool implement_dependant_register;
    bool implement_dependant_sr_encoding;
    bool ifc;
    bool mcu;
    bool ex9;
    int shadow;
};
 
struct nds32 {
    unsigned int common_magic;
 
    struct reg_cache *core_cache;
 
    struct nds32_edm edm;
 
    struct nds32_memory memory;
 
    struct nds32_cpu_version cpu_version;
 
    struct nds32_mmu_config mmu_config;
 
    struct nds32_misc_config misc_config;
 
    int (*full_context)(struct nds32 *nds32);
 
    int (*register_map)(struct nds32 *nds32, int reg_no);
 
    int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason);
 
    int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 
    int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 
    int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
 
    uint32_t max_interrupt_level;
 
    uint32_t current_interrupt_level;
 
    uint32_t watched_address;
 
    bool virtual_hosting;
 
    bool hit_syscall;
 
    int virtual_hosting_errno;
 
    bool virtual_hosting_ctrl_c;
 
    int active_syscall_id;
 
    struct breakpoint syscall_break;
 
    bool global_stop;
 
    bool soft_reset_halt;
 
    bool reset_halt_as_examine;
 
    bool keep_target_edm_ctl;
 
    /* Value of $EDM_CTL before target enters debug mode */
    uint32_t backup_edm_ctl;
 
    bool word_access_mem;
 
    char *edm_passcode;
 
    int privilege_level;
 
    uint32_t boot_time;
 
    bool step_isr_enable;
 
    bool init_arch_info_after_halted;
 
    bool audio_enable;
 
    bool fpu_enable;
 
    /* Andes Core has mixed endian model. Instruction is always big-endian.
     * Data may be big or little endian. Device registers may have different
     * endian from data and instruction. */
    enum target_endianness data_endian;
 
    enum target_endianness device_reg_endian;
 
    bool auto_convert_hw_bp;
 
    /* Flag to indicate the target is attached by debugger or not */
    bool attached;
 
    struct target *target;
 
    void *arch_info;
};
 
struct nds32_reg {
    int32_t num;
    uint8_t value[8];
    struct target *target;
    struct nds32 *nds32;
    bool enable;
};
 
struct nds32_edm_operation {
    uint32_t reg_no;
    uint32_t value;
};
 
extern int nds32_config(struct nds32 *nds32);
extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
extern int nds32_full_context(struct nds32 *nds32);
extern int nds32_arch_state(struct target *target);
extern int nds32_add_software_breakpoint(struct target *target,
        struct breakpoint *breakpoint);
extern int nds32_remove_software_breakpoint(struct target *target,
        struct breakpoint *breakpoint);
 
extern int nds32_get_gdb_reg_list(struct target *target,
        struct reg **reg_list[], int *reg_list_size,
        enum target_register_class reg_class);
 
extern int nds32_write_buffer(struct target *target, uint32_t address,
        uint32_t size, const uint8_t *buffer);
extern int nds32_read_buffer(struct target *target, uint32_t address,
        uint32_t size, uint8_t *buffer);
extern int nds32_read_memory(struct target *target, uint32_t address,
        uint32_t size, uint32_t count, uint8_t *buffer);
extern int nds32_write_memory(struct target *target, uint32_t address,
        uint32_t size, uint32_t count, const uint8_t *buffer);
 
extern int nds32_init_register_table(struct nds32 *nds32);
extern int nds32_init_memory_info(struct nds32 *nds32);
extern int nds32_restore_context(struct target *target);
extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value);
extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
 
extern int nds32_edm_config(struct nds32 *nds32);
extern int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length);
extern int nds32_mmu(struct target *target, int *enabled);
extern int nds32_virtual_to_physical(struct target *target, target_addr_t address,
        target_addr_t *physical);
extern int nds32_read_phys_memory(struct target *target, target_addr_t address,
        uint32_t size, uint32_t count, uint8_t *buffer);
extern int nds32_write_phys_memory(struct target *target, target_addr_t address,
        uint32_t size, uint32_t count, const uint8_t *buffer);
extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
extern int nds32_examine_debug_reason(struct nds32 *nds32);
extern int nds32_step(struct target *target, int current,
        target_addr_t address, int handle_breakpoints);
extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
extern int nds32_halt(struct target *target);
extern int nds32_poll(struct target *target);
extern int nds32_resume(struct target *target, int current,
        target_addr_t address, int handle_breakpoints, int debug_execution);
extern int nds32_assert_reset(struct target *target);
extern int nds32_init(struct nds32 *nds32);
extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
        uint32_t size, const uint8_t *buffer);
extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
extern int nds32_reset_halt(struct nds32 *nds32);
extern int nds32_login(struct nds32 *nds32);
extern int nds32_profiling(struct target *target, uint32_t *samples,
            uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 
static inline struct nds32 *target_to_nds32(struct target *target)
{
    assert(target);
    return target->arch_info;
}
 
static inline struct aice_port_s *target_to_aice(struct target *target)
{
    assert(target);
    return target->tap->priv;
}
 
static inline bool is_nds32(struct nds32 *nds32)
{
    assert(nds32);
    return nds32->common_magic == NDS32_COMMON_MAGIC;
}
 
static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
{
    assert(nds32);
    return nds32->max_interrupt_level == nds32->current_interrupt_level;
}
 
#endif /* OPENOCD_TARGET_NDS32_H */