mips32.h File Reference
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Data Structures | |
| struct | mips32_algorithm |
| struct | mips32_common |
| struct | mips32_comparator |
| struct | mips32_core_reg |
Macros | |
| #define | KSEG0 0x80000000 |
| #define | KSEG1 0xa0000000 |
| #define | KSEG2 0xc0000000 |
| #define | KSEG3 0xe0000000 |
| #define | KSEGX(a) ((a) & 0xe0000000) |
| Returns the kernel segment base of a given address. More... | |
| #define | KUSEG 0x00000000 |
| Memory segments (32bit kernel mode addresses) These are the traditional names used in the 32-bit universe. More... | |
| #define | MIPS16_ISA_SDBBP 0xE801u |
| #define | MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP) |
| #define | MIPS32_ADDI(isa, tar, src, val) (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val)) |
| #define | MIPS32_ADDIU(isa, tar, src, val) (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val)) |
| #define | MIPS32_ADDU(isa, dst, src, tar) (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar)) |
| #define | MIPS32_AND(isa, dst, src, tar) (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar)) |
| #define | MIPS32_ANDI(isa, tar, src, val) (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val)) |
| #define | MIPS32_ARCH_REL1 0x0 |
| #define | MIPS32_ARCH_REL2 0x1 |
| #define | MIPS32_B(isa, off) (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off)) |
| #define | MIPS32_BEQ(isa, src, tar, off) (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off)) |
| #define | MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off)) |
| #define | MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off)) |
| #define | MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base)) |
| #define | MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2)) |
| Cache operations definitions Operation field is 5 bits long : 1) bits 1..0 hold cache type 2) bits 4..2 hold operation code. More... | |
| #define | MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2)) |
| #define | MIPS32_COMMON_MAGIC 0xB320B320U |
| #define | MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT) |
| #define | MIPS32_CONFIG0_AR_SHIFT 10 |
| #define | MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT) |
| #define | MIPS32_CONFIG0_K0_SHIFT 0 |
| #define | MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT) |
| #define | MIPS32_CONFIG0_K23_SHIFT 28 |
| #define | MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT) |
| #define | MIPS32_CONFIG0_KU_SHIFT 25 |
| CP0 CONFIG register fields. More... | |
| #define | MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT) |
| #define | MIPS32_CONFIG1_DL_SHIFT 10 |
| #define | MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT) |
| #define | MIPS32_CONFIG3_ISA_SHIFT 14 |
| #define | MIPS32_COP0_MF 0x00u |
| #define | MIPS32_COP0_MT 0x04u |
| #define | MIPS32_DRET(isa) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET) |
| #define | MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd)) |
| #define | MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) |
| #define | MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val) |
| #define | MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU) |
| #define | MIPS32_ISA_AND(dst, src, tar) MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND) |
| #define | MIPS32_ISA_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val) |
| #define | MIPS32_ISA_B(off) MIPS32_ISA_BEQ(0, 0, off) |
| #define | MIPS32_ISA_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off) |
| #define | MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) |
| #define | MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) |
| #define | MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) |
| #define | MIPS32_ISA_DRET 0x4200001Fu |
| #define | MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2) |
| #define | MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) |
| #define | MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off) |
| #define | MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off) |
| #define | MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) |
| #define | MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) |
| #define | MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) |
| #define | MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) |
| #define | MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) |
| #define | MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) |
| #define | MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN) |
| #define | MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) |
| #define | MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) |
| #define | MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) |
| #define | MIPS32_ISA_NOP 0 |
| #define | MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) |
| #define | MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR) |
| #define | MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) |
| #define | MIPS32_ISA_SDBBP 0x7000003Fu |
| #define | MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) |
| #define | MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL) |
| #define | MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val) |
| #define | MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU) |
| #define | MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) |
| #define | MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off) |
| #define | MIPS32_ISA_SYNC 0xFu |
| #define | MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off) |
| #define | MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */ |
| #define | MIPS32_ISA_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR) |
| #define | MIPS32_ISA_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val) |
| #define | MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar)) |
| #define | MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr)) |
| #define | MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg)) |
| #define | MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base)) |
| #define | MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base)) |
| #define | MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base)) |
| #define | MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val)) |
| #define | MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base)) |
| #define | MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel)) |
| #define | MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg)) |
| #define | MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg)) |
| #define | MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar)) |
| #define | MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel)) |
| #define | MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg)) |
| #define | MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg)) |
| #define | MIPS32_NOP 0 /* same for both isa's */ |
| #define | MIPS32_OP_ADDI 0x08u |
| #define | MIPS32_OP_ADDIU 0x09u |
| #define | MIPS32_OP_ADDU 0x21u |
| #define | MIPS32_OP_AND 0x24u |
| #define | MIPS32_OP_ANDI 0x0Cu |
| #define | MIPS32_OP_BEQ 0x04u |
| #define | MIPS32_OP_BGTZ 0x07u |
| #define | MIPS32_OP_BNE 0x05u |
| #define | MIPS32_OP_CACHE 0x2Fu |
| #define | MIPS32_OP_COP0 0x10u |
| #define | MIPS32_OP_J 0x02u |
| #define | MIPS32_OP_JR 0x08u |
| #define | MIPS32_OP_LB 0x20u |
| #define | MIPS32_OP_LBU 0x24u |
| #define | MIPS32_OP_LHU 0x25u |
| #define | MIPS32_OP_LUI 0x0Fu |
| #define | MIPS32_OP_LW 0x23u |
| #define | MIPS32_OP_MFHI 0x10u |
| #define | MIPS32_OP_MFLO 0x12u |
| #define | MIPS32_OP_MOVN 0x0Bu |
| #define | MIPS32_OP_MTHI 0x11u |
| #define | MIPS32_OP_MTLO 0x13u |
| #define | MIPS32_OP_ORI 0x0Du |
| #define | MIPS32_OP_RDHWR 0x3Bu |
| #define | MIPS32_OP_REGIMM 0x01u |
| #define | MIPS32_OP_SB 0x28u |
| #define | MIPS32_OP_SDBBP 0x3Fu |
| #define | MIPS32_OP_SH 0x29u |
| #define | MIPS32_OP_SLL 0x00u |
| #define | MIPS32_OP_SLTI 0x0Au |
| #define | MIPS32_OP_SLTU 0x2Bu |
| #define | MIPS32_OP_SPECIAL 0x00u |
| #define | MIPS32_OP_SPECIAL2 0x07u |
| #define | MIPS32_OP_SPECIAL3 0x1Fu |
| #define | MIPS32_OP_SRL 0x03u |
| #define | MIPS32_OP_SW 0x2Bu |
| #define | MIPS32_OP_SYNCI 0x1Fu |
| #define | MIPS32_OP_XOR 0x26u |
| #define | MIPS32_OP_XORI 0x0Eu |
| #define | MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val)) |
| #define | MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct)) |
| #define | MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst)) |
| #define | MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base)) |
| #define | MIPS32_SCAN_DELAY_LEGACY_MODE 2000000 |
| #define | MIPS32_SDBBP(isa) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP) |
| #define | MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base)) |
| #define | MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa)) |
| #define | MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val)) |
| #define | MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar)) |
| #define | MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off)) |
| #define | MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base)) |
| #define | MIPS32_SYNC(isa) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC) |
| #define | MIPS32_SYNCI(isa, off, base) (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base)) |
| #define | MIPS32_SYNCI_STEP 0x1 |
| #define | MIPS32_XOR(isa, reg, val1, val2) (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2)) |
| #define | MIPS32_XORI(isa, tar, src, val) (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val)) |
| #define | MMIPS16_SDBBP 0x46C0u /* POOL16C instr */ |
| #define | MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val) |
| #define | MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val) |
| #define | MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU) |
| #define | MMIPS32_AND(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND) |
| #define | MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val) |
| #define | MMIPS32_B(off) MMIPS32_BEQ(0, 0, off) |
| #define | MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off) |
| #define | MMIPS32_BGTZ(reg, off) MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off) |
| #define | MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off) |
| #define | MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) |
| #define | MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */ |
| #define | MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1)))) |
| #define | MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF) |
| #define | MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off) |
| #define | MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off) |
| #define | MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off) |
| #define | MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val) |
| #define | MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off) |
| #define | MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF) |
| #define | MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF) |
| #define | MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF) |
| #define | MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) |
| #define | MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF) |
| #define | MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF) |
| #define | MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF) |
| #define | MMIPS32_NOP 0 |
| #define | MMIPS32_OP_ADDI 0x04u |
| #define | MMIPS32_OP_ADDIU 0x0Cu |
| #define | MMIPS32_OP_ADDU 0x150u |
| #define | MMIPS32_OP_AND 0x250u |
| #define | MMIPS32_OP_ANDI 0x34u |
| #define | MMIPS32_OP_BEQ 0x25u |
| #define | MMIPS32_OP_BGTZ 0x06u |
| #define | MMIPS32_OP_BNE 0x2Du |
| #define | MMIPS32_OP_CACHE 0x06u |
| #define | MMIPS32_OP_J 0x35u |
| #define | MMIPS32_OP_JALR 0x03Cu |
| #define | MMIPS32_OP_LB 0x07u |
| #define | MMIPS32_OP_LBU 0x05u |
| #define | MMIPS32_OP_LHU 0x0Du |
| #define | MMIPS32_OP_LUI 0x0Du |
| #define | MMIPS32_OP_LW 0x3Fu |
| #define | MMIPS32_OP_MFC0 0x03u |
| #define | MMIPS32_OP_MFHI 0x035u |
| #define | MMIPS32_OP_MFLO 0x075u |
| #define | MMIPS32_OP_MOVN 0x018u |
| #define | MMIPS32_OP_MTC0 0x0Bu |
| #define | MMIPS32_OP_MTHI 0x0B5u |
| #define | MMIPS32_OP_MTLO 0x0F5u |
| #define | MMIPS32_OP_ORI 0x14u |
| #define | MMIPS32_OP_RDHWR 0x1ACu |
| #define | MMIPS32_OP_SB 0x06u |
| #define | MMIPS32_OP_SH 0x0Eu |
| #define | MMIPS32_OP_SLL 0x000u |
| #define | MMIPS32_OP_SLTI 0x24u |
| #define | MMIPS32_OP_SLTU 0x390u |
| #define | MMIPS32_OP_SRL 0x040u |
| #define | MMIPS32_OP_SW 0x3Eu |
| #define | MMIPS32_OP_SYNCI 0x10u |
| #define | MMIPS32_OP_XOR 0x310u |
| #define | MMIPS32_OP_XORI 0x1Cu |
| #define | MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val) |
| #define | MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF) |
| #define | MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off) |
| #define | MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */ |
| #define | MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off) |
| #define | MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) |
| #define | MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val) |
| #define | MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU) |
| #define | MMIPS32_SRL(reg, src, off) MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL) |
| #define | MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off) |
| #define | MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */ |
| #define | MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off) |
| #define | MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */ |
| #define | MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) |
| #define | MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val) |
| #define | POOL32A 0X00u |
| #define | POOL32AXF 0x3Cu |
| #define | POOL32B 0x08u |
| #define | POOL32I 0x10u |
Enumerations | |
| enum | { MIPS32_PC = 37 , MIPS32_FIR = 71 , MIPS32NUMCOREREGS } |
| enum | mips32_isa_imp { MIPS32_ONLY = 0 , MMIPS32_ONLY = 1 , MIPS32_MIPS16 = 2 , MIPS32_MMIPS32 = 3 } |
| enum | mips32_isa_mode { MIPS32_ISA_MIPS32 = 0 , MIPS32_ISA_MIPS16E = 1 , MIPS32_ISA_MMIPS32 = 3 } |
Functions | |
| int | mips32_arch_state (struct target *target) |
| int | mips32_blank_check_memory (struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value) |
| Checks whether a memory region is erased. More... | |
| struct reg_cache * | mips32_build_reg_cache (struct target *target) |
| int | mips32_checksum_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum) |
| int | mips32_configure_break_unit (struct target *target) |
| int | mips32_enable_interrupts (struct target *target, int enable) |
| int | mips32_examine (struct target *target) |
| int | mips32_get_gdb_reg_list (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class) |
| int | mips32_init_arch_info (struct target *target, struct mips32_common *mips32, struct jtag_tap *tap) |
| int | mips32_read_config_regs (struct target *target) |
| int | mips32_register_commands (struct command_context *cmd_ctx) |
| int | mips32_restore_context (struct target *target) |
| int | mips32_run_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info) |
| int | mips32_save_context (struct target *target) |
| static struct mips32_common * | target_to_mips32 (struct target *target) |
Variables | |
| const struct command_registration | mips32_command_handlers [] |
Macro Definition Documentation
◆ KSEG0
◆ KSEG1
◆ KSEG2
◆ KSEG3
◆ KSEGX
| #define KSEGX | ( | a | ) | ((a) & 0xe0000000) |
◆ KUSEG
| #define KUSEG 0x00000000 |
◆ MIPS16_ISA_SDBBP
◆ MIPS16_SDBBP
| #define MIPS16_SDBBP | ( | isa | ) | (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP) |
◆ MIPS32_ADDI
| #define MIPS32_ADDI | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val)) |
◆ MIPS32_ADDIU
| #define MIPS32_ADDIU | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val)) |
◆ MIPS32_ADDU
| #define MIPS32_ADDU | ( | isa, | |
| dst, | |||
| src, | |||
| tar | |||
| ) | (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar)) |
◆ MIPS32_AND
| #define MIPS32_AND | ( | isa, | |
| dst, | |||
| src, | |||
| tar | |||
| ) | (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar)) |
◆ MIPS32_ANDI
| #define MIPS32_ANDI | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val)) |
◆ MIPS32_ARCH_REL1
◆ MIPS32_ARCH_REL2
◆ MIPS32_B
| #define MIPS32_B | ( | isa, | |
| off | |||
| ) | (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off)) |
◆ MIPS32_BEQ
| #define MIPS32_BEQ | ( | isa, | |
| src, | |||
| tar, | |||
| off | |||
| ) | (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off)) |
◆ MIPS32_BGTZ
| #define MIPS32_BGTZ | ( | isa, | |
| reg, | |||
| off | |||
| ) | (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off)) |
◆ MIPS32_BNE
| #define MIPS32_BNE | ( | isa, | |
| src, | |||
| tar, | |||
| off | |||
| ) | (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off)) |
◆ MIPS32_CACHE
| #define MIPS32_CACHE | ( | isa, | |
| op, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base)) |
◆ MIPS32_CACHE_D_HIT_WRITEBACK
| #define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2)) |
◆ MIPS32_CACHE_I_HIT_INVALIDATE
| #define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2)) |
◆ MIPS32_COMMON_MAGIC
◆ MIPS32_CONFIG0_AR_MASK
| #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT) |
◆ MIPS32_CONFIG0_AR_SHIFT
◆ MIPS32_CONFIG0_K0_MASK
| #define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT) |
◆ MIPS32_CONFIG0_K0_SHIFT
◆ MIPS32_CONFIG0_K23_MASK
| #define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT) |
◆ MIPS32_CONFIG0_K23_SHIFT
◆ MIPS32_CONFIG0_KU_MASK
| #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT) |
◆ MIPS32_CONFIG0_KU_SHIFT
| #define MIPS32_CONFIG0_KU_SHIFT 25 |
◆ MIPS32_CONFIG1_DL_MASK
| #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT) |
◆ MIPS32_CONFIG1_DL_SHIFT
◆ MIPS32_CONFIG3_ISA_MASK
| #define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT) |
◆ MIPS32_CONFIG3_ISA_SHIFT
◆ MIPS32_COP0_MF
◆ MIPS32_COP0_MT
◆ MIPS32_DRET
| #define MIPS32_DRET | ( | isa | ) | (isa ? MMIPS32_DRET : MIPS32_ISA_DRET) |
◆ MIPS32_I_INST
| #define MIPS32_I_INST | ( | opcode, | |
| rs, | |||
| rt, | |||
| immd | |||
| ) | (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd)) |
◆ MIPS32_ISA_ADDI
| #define MIPS32_ISA_ADDI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) |
◆ MIPS32_ISA_ADDIU
| #define MIPS32_ISA_ADDIU | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val) |
◆ MIPS32_ISA_ADDU
| #define MIPS32_ISA_ADDU | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU) |
◆ MIPS32_ISA_AND
| #define MIPS32_ISA_AND | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND) |
◆ MIPS32_ISA_ANDI
| #define MIPS32_ISA_ANDI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val) |
◆ MIPS32_ISA_B
| #define MIPS32_ISA_B | ( | off | ) | MIPS32_ISA_BEQ(0, 0, off) |
◆ MIPS32_ISA_BEQ
| #define MIPS32_ISA_BEQ | ( | src, | |
| tar, | |||
| off | |||
| ) | MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off) |
◆ MIPS32_ISA_BGTZ
| #define MIPS32_ISA_BGTZ | ( | reg, | |
| off | |||
| ) | MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) |
◆ MIPS32_ISA_BNE
| #define MIPS32_ISA_BNE | ( | src, | |
| tar, | |||
| off | |||
| ) | MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) |
◆ MIPS32_ISA_CACHE
| #define MIPS32_ISA_CACHE | ( | op, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) |
◆ MIPS32_ISA_DRET
◆ MIPS32_ISA_J
| #define MIPS32_ISA_J | ( | tar | ) | MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2) |
◆ MIPS32_ISA_JR
| #define MIPS32_ISA_JR | ( | reg | ) | MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) |
◆ MIPS32_ISA_LB
| #define MIPS32_ISA_LB | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_LB, base, reg, off) |
◆ MIPS32_ISA_LBU
| #define MIPS32_ISA_LBU | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off) |
◆ MIPS32_ISA_LHU
| #define MIPS32_ISA_LHU | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) |
◆ MIPS32_ISA_LUI
| #define MIPS32_ISA_LUI | ( | reg, | |
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) |
◆ MIPS32_ISA_LW
| #define MIPS32_ISA_LW | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) |
◆ MIPS32_ISA_MFC0
| #define MIPS32_ISA_MFC0 | ( | gpr, | |
| cpr, | |||
| sel | |||
| ) | MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) |
◆ MIPS32_ISA_MFHI
| #define MIPS32_ISA_MFHI | ( | reg | ) | MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) |
◆ MIPS32_ISA_MFLO
| #define MIPS32_ISA_MFLO | ( | reg | ) | MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) |
◆ MIPS32_ISA_MOVN
| #define MIPS32_ISA_MOVN | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN) |
◆ MIPS32_ISA_MTC0
| #define MIPS32_ISA_MTC0 | ( | gpr, | |
| cpr, | |||
| sel | |||
| ) | MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) |
◆ MIPS32_ISA_MTHI
| #define MIPS32_ISA_MTHI | ( | reg | ) | MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) |
◆ MIPS32_ISA_MTLO
| #define MIPS32_ISA_MTLO | ( | reg | ) | MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) |
◆ MIPS32_ISA_NOP
◆ MIPS32_ISA_ORI
| #define MIPS32_ISA_ORI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) |
◆ MIPS32_ISA_RDHWR
| #define MIPS32_ISA_RDHWR | ( | tar, | |
| dst | |||
| ) | MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR) |
◆ MIPS32_ISA_SB
| #define MIPS32_ISA_SB | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) |
◆ MIPS32_ISA_SDBBP
◆ MIPS32_ISA_SH
| #define MIPS32_ISA_SH | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) |
◆ MIPS32_ISA_SLL
| #define MIPS32_ISA_SLL | ( | dst, | |
| src, | |||
| sa | |||
| ) | MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL) |
◆ MIPS32_ISA_SLTI
| #define MIPS32_ISA_SLTI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val) |
◆ MIPS32_ISA_SLTU
| #define MIPS32_ISA_SLTU | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU) |
◆ MIPS32_ISA_SRL
| #define MIPS32_ISA_SRL | ( | reg, | |
| src, | |||
| off | |||
| ) | MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) |
◆ MIPS32_ISA_SW
| #define MIPS32_ISA_SW | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_SW, base, reg, off) |
◆ MIPS32_ISA_SYNC
◆ MIPS32_ISA_SYNCI
| #define MIPS32_ISA_SYNCI | ( | off, | |
| base | |||
| ) | MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off) |
◆ MIPS32_ISA_SYNCI_STEP
◆ MIPS32_ISA_XOR
| #define MIPS32_ISA_XOR | ( | reg, | |
| val1, | |||
| val2 | |||
| ) | MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR) |
◆ MIPS32_ISA_XORI
| #define MIPS32_ISA_XORI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val) |
◆ MIPS32_J
| #define MIPS32_J | ( | isa, | |
| tar | |||
| ) | (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar)) |
◆ MIPS32_J_INST
◆ MIPS32_JR
| #define MIPS32_JR | ( | isa, | |
| reg | |||
| ) | (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg)) |
◆ MIPS32_LB
| #define MIPS32_LB | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base)) |
◆ MIPS32_LBU
| #define MIPS32_LBU | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base)) |
◆ MIPS32_LHU
| #define MIPS32_LHU | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base)) |
◆ MIPS32_LUI
| #define MIPS32_LUI | ( | isa, | |
| reg, | |||
| val | |||
| ) | (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val)) |
◆ MIPS32_LW
| #define MIPS32_LW | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base)) |
◆ MIPS32_MFC0
| #define MIPS32_MFC0 | ( | isa, | |
| gpr, | |||
| cpr, | |||
| sel | |||
| ) | (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel)) |
◆ MIPS32_MFHI
| #define MIPS32_MFHI | ( | isa, | |
| reg | |||
| ) | (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg)) |
◆ MIPS32_MFLO
| #define MIPS32_MFLO | ( | isa, | |
| reg | |||
| ) | (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg)) |
◆ MIPS32_MOVN
| #define MIPS32_MOVN | ( | isa, | |
| dst, | |||
| src, | |||
| tar | |||
| ) | (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar)) |
◆ MIPS32_MTC0
| #define MIPS32_MTC0 | ( | isa, | |
| gpr, | |||
| cpr, | |||
| sel | |||
| ) | (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel)) |
◆ MIPS32_MTHI
| #define MIPS32_MTHI | ( | isa, | |
| reg | |||
| ) | (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg)) |
◆ MIPS32_MTLO
| #define MIPS32_MTLO | ( | isa, | |
| reg | |||
| ) | (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg)) |
◆ MIPS32_NOP
◆ MIPS32_OP_ADDI
◆ MIPS32_OP_ADDIU
◆ MIPS32_OP_ADDU
◆ MIPS32_OP_AND
◆ MIPS32_OP_ANDI
◆ MIPS32_OP_BEQ
◆ MIPS32_OP_BGTZ
◆ MIPS32_OP_BNE
◆ MIPS32_OP_CACHE
◆ MIPS32_OP_COP0
◆ MIPS32_OP_J
◆ MIPS32_OP_JR
◆ MIPS32_OP_LB
◆ MIPS32_OP_LBU
◆ MIPS32_OP_LHU
◆ MIPS32_OP_LUI
◆ MIPS32_OP_LW
◆ MIPS32_OP_MFHI
◆ MIPS32_OP_MFLO
◆ MIPS32_OP_MOVN
◆ MIPS32_OP_MTHI
◆ MIPS32_OP_MTLO
◆ MIPS32_OP_ORI
◆ MIPS32_OP_RDHWR
◆ MIPS32_OP_REGIMM
◆ MIPS32_OP_SB
◆ MIPS32_OP_SDBBP
◆ MIPS32_OP_SH
◆ MIPS32_OP_SLL
◆ MIPS32_OP_SLTI
◆ MIPS32_OP_SLTU
◆ MIPS32_OP_SPECIAL
◆ MIPS32_OP_SPECIAL2
◆ MIPS32_OP_SPECIAL3
◆ MIPS32_OP_SRL
◆ MIPS32_OP_SW
◆ MIPS32_OP_SYNCI
◆ MIPS32_OP_XOR
◆ MIPS32_OP_XORI
◆ MIPS32_ORI
| #define MIPS32_ORI | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val)) |
◆ MIPS32_R_INST
| #define MIPS32_R_INST | ( | opcode, | |
| rs, | |||
| rt, | |||
| rd, | |||
| shamt, | |||
| funct | |||
| ) | (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct)) |
◆ MIPS32_RDHWR
| #define MIPS32_RDHWR | ( | isa, | |
| tar, | |||
| dst | |||
| ) | (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst)) |
◆ MIPS32_SB
| #define MIPS32_SB | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base)) |
◆ MIPS32_SCAN_DELAY_LEGACY_MODE
◆ MIPS32_SDBBP
| #define MIPS32_SDBBP | ( | isa | ) | (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP) |
◆ MIPS32_SH
| #define MIPS32_SH | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base)) |
◆ MIPS32_SLL
| #define MIPS32_SLL | ( | isa, | |
| dst, | |||
| src, | |||
| sa | |||
| ) | (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa)) |
◆ MIPS32_SLTI
| #define MIPS32_SLTI | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val)) |
◆ MIPS32_SLTU
| #define MIPS32_SLTU | ( | isa, | |
| dst, | |||
| src, | |||
| tar | |||
| ) | (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar)) |
◆ MIPS32_SRL
| #define MIPS32_SRL | ( | isa, | |
| reg, | |||
| src, | |||
| off | |||
| ) | (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off)) |
◆ MIPS32_SW
| #define MIPS32_SW | ( | isa, | |
| reg, | |||
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base)) |
◆ MIPS32_SYNC
| #define MIPS32_SYNC | ( | isa | ) | (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC) |
◆ MIPS32_SYNCI
| #define MIPS32_SYNCI | ( | isa, | |
| off, | |||
| base | |||
| ) | (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base)) |
◆ MIPS32_SYNCI_STEP
◆ MIPS32_XOR
| #define MIPS32_XOR | ( | isa, | |
| reg, | |||
| val1, | |||
| val2 | |||
| ) | (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2)) |
◆ MIPS32_XORI
| #define MIPS32_XORI | ( | isa, | |
| tar, | |||
| src, | |||
| val | |||
| ) | (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val)) |
◆ MMIPS16_SDBBP
◆ MMIPS32_ADDI
| #define MMIPS32_ADDI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val) |
◆ MMIPS32_ADDIU
| #define MMIPS32_ADDIU | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val) |
◆ MMIPS32_ADDU
| #define MMIPS32_ADDU | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU) |
◆ MMIPS32_AND
| #define MMIPS32_AND | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND) |
◆ MMIPS32_ANDI
| #define MMIPS32_ANDI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val) |
◆ MMIPS32_B
| #define MMIPS32_B | ( | off | ) | MMIPS32_BEQ(0, 0, off) |
◆ MMIPS32_BEQ
| #define MMIPS32_BEQ | ( | src, | |
| tar, | |||
| off | |||
| ) | MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off) |
◆ MMIPS32_BGTZ
| #define MMIPS32_BGTZ | ( | reg, | |
| off | |||
| ) | MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off) |
◆ MMIPS32_BNE
| #define MMIPS32_BNE | ( | src, | |
| tar, | |||
| off | |||
| ) | MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off) |
◆ MMIPS32_CACHE
| #define MMIPS32_CACHE | ( | op, | |
| off, | |||
| base | |||
| ) | MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) |
◆ MMIPS32_DRET
| #define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */ |
◆ MMIPS32_J
| #define MMIPS32_J | ( | tar | ) | MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1)))) |
◆ MMIPS32_JR
| #define MMIPS32_JR | ( | reg | ) | MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF) |
◆ MMIPS32_LB
| #define MMIPS32_LB | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off) |
◆ MMIPS32_LBU
| #define MMIPS32_LBU | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off) |
◆ MMIPS32_LHU
| #define MMIPS32_LHU | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off) |
◆ MMIPS32_LUI
| #define MMIPS32_LUI | ( | reg, | |
| val | |||
| ) | MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val) |
◆ MMIPS32_LW
| #define MMIPS32_LW | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off) |
◆ MMIPS32_MFC0
| #define MMIPS32_MFC0 | ( | gpr, | |
| cpr, | |||
| sel | |||
| ) | MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF) |
◆ MMIPS32_MFHI
| #define MMIPS32_MFHI | ( | reg | ) | MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF) |
◆ MMIPS32_MFLO
| #define MMIPS32_MFLO | ( | reg | ) | MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF) |
◆ MMIPS32_MOVN
| #define MMIPS32_MOVN | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) |
◆ MMIPS32_MTC0
| #define MMIPS32_MTC0 | ( | gpr, | |
| cpr, | |||
| sel | |||
| ) | MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF) |
◆ MMIPS32_MTHI
| #define MMIPS32_MTHI | ( | reg | ) | MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF) |
◆ MMIPS32_MTLO
| #define MMIPS32_MTLO | ( | reg | ) | MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF) |
◆ MMIPS32_NOP
◆ MMIPS32_OP_ADDI
◆ MMIPS32_OP_ADDIU
◆ MMIPS32_OP_ADDU
◆ MMIPS32_OP_AND
◆ MMIPS32_OP_ANDI
◆ MMIPS32_OP_BEQ
◆ MMIPS32_OP_BGTZ
◆ MMIPS32_OP_BNE
◆ MMIPS32_OP_CACHE
◆ MMIPS32_OP_J
◆ MMIPS32_OP_JALR
◆ MMIPS32_OP_LB
◆ MMIPS32_OP_LBU
◆ MMIPS32_OP_LHU
◆ MMIPS32_OP_LUI
◆ MMIPS32_OP_LW
◆ MMIPS32_OP_MFC0
◆ MMIPS32_OP_MFHI
◆ MMIPS32_OP_MFLO
◆ MMIPS32_OP_MOVN
◆ MMIPS32_OP_MTC0
◆ MMIPS32_OP_MTHI
◆ MMIPS32_OP_MTLO
◆ MMIPS32_OP_ORI
◆ MMIPS32_OP_RDHWR
◆ MMIPS32_OP_SB
◆ MMIPS32_OP_SH
◆ MMIPS32_OP_SLL
◆ MMIPS32_OP_SLTI
◆ MMIPS32_OP_SLTU
◆ MMIPS32_OP_SRL
◆ MMIPS32_OP_SW
◆ MMIPS32_OP_SYNCI
◆ MMIPS32_OP_XOR
◆ MMIPS32_OP_XORI
◆ MMIPS32_ORI
| #define MMIPS32_ORI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val) |
◆ MMIPS32_RDHWR
| #define MMIPS32_RDHWR | ( | tar, | |
| dst | |||
| ) | MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF) |
◆ MMIPS32_SB
| #define MMIPS32_SB | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off) |
◆ MMIPS32_SDBBP
| #define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */ |
◆ MMIPS32_SH
| #define MMIPS32_SH | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off) |
◆ MMIPS32_SLL
| #define MMIPS32_SLL | ( | dst, | |
| src, | |||
| sa | |||
| ) | MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) |
◆ MMIPS32_SLTI
| #define MMIPS32_SLTI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val) |
◆ MMIPS32_SLTU
| #define MMIPS32_SLTU | ( | dst, | |
| src, | |||
| tar | |||
| ) | MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU) |
◆ MMIPS32_SRL
| #define MMIPS32_SRL | ( | reg, | |
| src, | |||
| off | |||
| ) | MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL) |
◆ MMIPS32_SW
| #define MMIPS32_SW | ( | reg, | |
| off, | |||
| base | |||
| ) | MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off) |
◆ MMIPS32_SYNC
| #define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */ |
◆ MMIPS32_SYNCI
| #define MMIPS32_SYNCI | ( | off, | |
| base | |||
| ) | MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off) |
◆ MMIPS32_SYNCI_STEP
◆ MMIPS32_XOR
| #define MMIPS32_XOR | ( | reg, | |
| val1, | |||
| val2 | |||
| ) | MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) |
◆ MMIPS32_XORI
| #define MMIPS32_XORI | ( | tar, | |
| src, | |||
| val | |||
| ) | MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val) |
◆ POOL32A
◆ POOL32AXF
◆ POOL32B
◆ POOL32I
Enumeration Type Documentation
◆ anonymous enum
| anonymous enum |
◆ mips32_isa_imp
| enum mips32_isa_imp |
◆ mips32_isa_mode
| enum mips32_isa_mode |
Function Documentation
◆ mips32_arch_state()
| int mips32_arch_state | ( | struct target * | target | ) |
Definition at line 280 of file mips32.c.
References buf_get_u32(), mips32_common::core_cache, debug_reason_name(), ERROR_OK, mips32_common::isa_mode, LOG_USER, MIPS32_PC, mips_isa_strings, reg_cache::reg_list, target_to_mips32(), and reg::value.
◆ mips32_blank_check_memory()
| int mips32_blank_check_memory | ( | struct target * | target, |
| struct target_memory_check_block * | blocks, | ||
| int | num_blocks, | ||
| uint8_t | erased_value | ||
| ) |
Checks whether a memory region is erased.
Definition at line 823 of file mips32.c.
References working_area::address, ARRAY_SIZE, buf_get_u32(), buf_set_u32(), mips32_algorithm::common_magic, destroy_reg_param(), mips32_common::ejtag_info, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, init_reg_param(), mips_ejtag::isa, mips32_algorithm::isa_mode, LOG_ERROR, MIPS32_ADDIU, MIPS32_AND, MIPS32_BNE, MIPS32_COMMON_MAGIC, MIPS32_ISA_MIPS32, MIPS32_ISA_MMIPS32, MIPS32_LB, MIPS32_SDBBP, NEG16, NULL, PARAM_IN_OUT, PARAM_OUT, pracc_swap16_array(), target_memory_check_block::result, size, target_alloc_working_area(), target_buffer_set_u32_array(), target_free_working_area(), target_run_algorithm(), target_to_mips32(), and target_write_buffer().
◆ mips32_build_reg_cache()
Definition at line 297 of file mips32.c.
References reg::arch_info, reg::caller_save, mips32_common::core_cache, reg::dirty, reg::exist, feature, reg::feature, flag, reg::group, LOG_ERROR, mips32_core_reg::mips32_common, MIPS32_GDB_DUMMY_FP_REG, mips32_gdb_dummy_fp_value, MIPS32_NUM_REGS, mips32_reg_type, mips32_regs, reg::name, reg_cache::name, reg_cache::next, NULL, mips32_core_reg::num, reg_cache::num_regs, reg::number, target::reg_cache, reg::reg_data_type, reg_cache::reg_list, register_get_last_cache_p(), register_init_dummy(), reg::size, target, mips32_core_reg::target, target_to_mips32(), reg_data_type::type, reg::type, reg::valid, and reg::value.
Referenced by mips_m4k_init_target().
◆ mips32_checksum_memory()
| int mips32_checksum_memory | ( | struct target * | target, |
| target_addr_t | address, | ||
| uint32_t | count, | ||
| uint32_t * | checksum | ||
| ) |
Definition at line 740 of file mips32.c.
References working_area::address, ARRAY_SIZE, buf_get_u32(), buf_set_u32(), mips32_algorithm::common_magic, count, destroy_reg_param(), mips32_common::ejtag_info, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, init_reg_param(), mips_ejtag::isa, mips32_algorithm::isa_mode, MIPS32_ADDI, MIPS32_ADDIU, MIPS32_ADDU, MIPS32_BEQ, MIPS32_BNE, MIPS32_COMMON_MAGIC, MIPS32_ISA_MIPS32, MIPS32_ISA_MMIPS32, MIPS32_LB, MIPS32_LUI, MIPS32_MOVN, MIPS32_ORI, MIPS32_SDBBP, MIPS32_SLL, MIPS32_SLTI, MIPS32_XOR, NEG16, NULL, PARAM_IN_OUT, PARAM_OUT, pracc_swap16_array(), target_alloc_working_area(), target_buffer_set_u32_array(), target_free_working_area(), target_run_algorithm(), target_to_mips32(), and target_write_buffer().
◆ mips32_configure_break_unit()
| int mips32_configure_break_unit | ( | struct target * | target | ) |
Definition at line 606 of file mips32.c.
References mips32_common::bp_scanned, mips_ejtag::debug_caps, EJTAG_DCR, EJTAG_DCR_DB, EJTAG_DCR_ENM, EJTAG_DCR_IB, mips32_common::ejtag_info, EJTAG_V20_IMP_NODB, EJTAG_V20_IMP_NOIB, mips_ejtag::ejtag_version, EJTAG_VERSION_20, target::endianness, ERROR_OK, mips_ejtag::impcode, LOG_DEBUG, LOG_WARNING, mips32_configure_dbs(), mips32_configure_ibs(), mips32_common::num_data_bpoints, mips32_common::num_inst_bpoints, TARGET_BIG_ENDIAN, TARGET_LITTLE_ENDIAN, target_read_u32(), and target_to_mips32().
Referenced by mips_m4k_debug_entry().
◆ mips32_enable_interrupts()
| int mips32_enable_interrupts | ( | struct target * | target, |
| int | enable | ||
| ) |
Definition at line 662 of file mips32.c.
References EJTAG_DCR, EJTAG_DCR_INTE, ERROR_OK, target_read_u32(), and target_write_u32().
Referenced by mips_m4k_internal_restore(), mips_m4k_single_step_core(), and mips_m4k_step().
◆ mips32_examine()
| int mips32_examine | ( | struct target * | target | ) |
Definition at line 534 of file mips32.c.
References mips32_common::bp_scanned, ERROR_OK, mips32_common::num_data_bpoints, mips32_common::num_data_bpoints_avail, mips32_common::num_inst_bpoints, mips32_common::num_inst_bpoints_avail, target_set_examined(), target_to_mips32(), and target_was_examined().
Referenced by mips_m4k_examine().
◆ mips32_get_gdb_reg_list()
| int mips32_get_gdb_reg_list | ( | struct target * | target, |
| struct reg ** | reg_list[], | ||
| int * | reg_list_size, | ||
| enum target_register_class | reg_class | ||
| ) |
Definition at line 225 of file mips32.c.
References mips32_common::core_cache, ERROR_OK, MIPS32_NUM_REGS, reg_cache::reg_list, and target_to_mips32().
◆ mips32_init_arch_info()
| int mips32_init_arch_info | ( | struct target * | target, |
| struct mips32_common * | mips32, | ||
| struct jtag_tap * | tap | ||
| ) |
Definition at line 362 of file mips32.c.
References target::arch_info, mips32_common::bp_scanned, mips32_common::common_magic, mips_ejtag::config_regs, mips32_common::data_break_list, mips32_common::ejtag_info, mips_ejtag::endianness, target::endianness, ERROR_OK, mips32_common::fast_data_area, mips_ejtag::isa, mips32_common::isa_imp, MIPS32_COMMON_MAGIC, MIPS32_ONLY, mips32_read_core_reg(), MIPS32_SCAN_DELAY_LEGACY_MODE, mips32_write_core_reg(), mips_ejtag::mode, NULL, mips32_common::read_core_reg, mips_ejtag::scan_delay, mips_ejtag::tap, TARGET_BIG_ENDIAN, and mips32_common::write_core_reg.
Referenced by mips_m4k_init_arch_info().
◆ mips32_read_config_regs()
| int mips32_read_config_regs | ( | struct target * | target | ) |
Definition at line 697 of file mips32.c.
References mips_ejtag::config, mips_ejtag::config_regs, EJTAG_IMP_MIPS16, mips32_common::ejtag_info, ERROR_OK, mips_ejtag::impcode, mips32_common::isa_imp, LOG_DEBUG, LOG_ERROR, LOG_USER, MIPS32_CONFIG3_ISA_MASK, MIPS32_CONFIG3_ISA_SHIFT, mips32_cp0_read(), MIPS32_MIPS16, MIPS32_MMIPS32, MIPS32_ONLY, MMIPS32_ONLY, and target_to_mips32().
Referenced by mips_m4k_debug_entry().
◆ mips32_register_commands()
| int mips32_register_commands | ( | struct command_context * | cmd_ctx | ) |
◆ mips32_restore_context()
| int mips32_restore_context | ( | struct target * | target | ) |
Definition at line 261 of file mips32.c.
References mips32_common::core_cache, mips32_common::core_regs, reg::dirty, mips32_common::ejtag_info, ERROR_OK, MIPS32_NUM_REGS, mips32_pracc_write_regs(), reg_cache::reg_list, target_to_mips32(), and mips32_common::write_core_reg.
Referenced by mips_m4k_internal_restore(), and mips_m4k_step().
◆ mips32_run_algorithm()
| int mips32_run_algorithm | ( | struct target * | target, |
| int | num_mem_params, | ||
| struct mem_param * | mem_params, | ||
| int | num_reg_params, | ||
| struct reg_param * | reg_params, | ||
| target_addr_t | entry_point, | ||
| target_addr_t | exit_point, | ||
| int | timeout_ms, | ||
| void * | arch_info | ||
| ) |
Definition at line 418 of file mips32.c.
References buf_get_u32(), buf_set_u32(), mips32_common::common_magic, mips32_common::core_cache, direction, reg::dirty, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, ERROR_TARGET_INVALID, ERROR_TARGET_NOT_HALTED, mips32_common::isa_mode, mips32_algorithm::isa_mode, LOG_DEBUG, LOG_ERROR, LOG_WARNING, MIPS32_COMMON_MAGIC, MIPS32_NUM_REGS, mips32_run_and_wait(), mips32_set_core_reg(), reg::name, PARAM_IN, PARAM_OUT, mips32_common::read_core_reg, reg_cache::reg_list, reg_param::reg_name, register_get_by_name(), size, reg_param::size, reg::size, target::state, TARGET_HALTED, target_read_buffer(), target_to_mips32(), target_write_buffer(), reg::valid, and reg::value.
◆ mips32_save_context()
| int mips32_save_context | ( | struct target * | target | ) |
Definition at line 242 of file mips32.c.
References mips32_common::core_cache, mips32_common::core_regs, mips32_common::ejtag_info, ERROR_OK, MIPS32_NUM_REGS, mips32_pracc_read_regs(), mips32_common::read_core_reg, reg_cache::reg_list, target_to_mips32(), and reg::valid.
Referenced by mips_m4k_debug_entry().
◆ target_to_mips32()
|
inlinestatic |
Definition at line 111 of file mips32.h.
References target::arch_info.
Referenced by ath79_spi_bitbang_chunk(), COMMAND_HANDLER(), mips32_arch_state(), mips32_blank_check_memory(), mips32_build_reg_cache(), mips32_checksum_memory(), mips32_configure_break_unit(), mips32_configure_dbs(), mips32_configure_ibs(), mips32_examine(), mips32_get_core_reg(), mips32_get_gdb_reg_list(), mips32_read_config_regs(), mips32_read_core_reg(), mips32_restore_context(), mips32_run_algorithm(), mips32_save_context(), mips32_write_core_reg(), mips_m4k_add_breakpoint(), mips_m4k_add_watchpoint(), mips_m4k_bulk_write_memory(), mips_m4k_debug_entry(), mips_m4k_examine_debug_reason(), mips_m4k_halt(), mips_m4k_internal_restore(), mips_m4k_poll(), mips_m4k_read_memory(), mips_m4k_remove_breakpoint(), mips_m4k_remove_watchpoint(), mips_m4k_set_breakpoint(), mips_m4k_set_watchpoint(), mips_m4k_single_step_core(), mips_m4k_step(), mips_m4k_unset_breakpoint(), mips_m4k_unset_watchpoint(), and mips_m4k_write_memory().
Variable Documentation
◆ mips32_command_handlers
|
extern |
