OpenOCD
etm.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005, 2007 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2007 by Vincent Palatin *
8  * vincent.palatin_openocd@m4x.org *
9  ***************************************************************************/
10 
11 #ifndef OPENOCD_TARGET_ETM_H
12 #define OPENOCD_TARGET_ETM_H
13 
14 #include "trace.h"
15 #include "arm_jtag.h"
16 
17 struct image;
18 
19 /* ETM registers (JTAG protocol) */
20 enum {
21  ETM_CTRL = 0x00,
22  ETM_CONFIG = 0x01,
24  ETM_ASIC_CTRL = 0x03,
25  ETM_STATUS = 0x04,
31  /* optional FIFOFULL */
34  /* viewdata support */
37  ETM_VIEWDATA_CTRL2 = 0x0e, /* optional */
39  /* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
42  /* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
45  /* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
50  /* 6 sequencer event transitions */
53  /* N triggered outputs */
55  /* N task contexts */
58  ETM_ID = 0x79,
59 };
60 
61 struct etm_reg {
62  uint8_t value[4];
63  const struct etm_reg_info *reg_info;
65 };
66 
67 /* Subset of ETM_CTRL bit assignments. Many of these
68  * control the configuration of trace output, which
69  * hooks up either to ETB or to an external device.
70  *
71  * NOTE that these have evolved since the ~v1.3 defns ...
72  */
73 enum {
74  ETM_CTRL_POWERDOWN = (1 << 0),
76 
77  /* bits 3:2 == trace type */
78  ETM_CTRL_TRACE_DATA = (1 << 2),
79  ETM_CTRL_TRACE_ADDR = (2 << 2),
80  ETM_CTRL_TRACE_MASK = (3 << 2),
81 
82  /* Port width (bits 21 and 6:4) */
83  ETM_PORT_4BIT = 0x00,
84  ETM_PORT_8BIT = 0x10,
90  ETM_PORT_1BIT = 0x00 | (1 << 21),
91  ETM_PORT_2BIT = 0x10 | (1 << 21),
92  ETM_PORT_WIDTH_MASK = 0x70 | (1 << 21),
93 
96  ETM_CTRL_DBGRQ = (1 << 9),
97  ETM_CTRL_ETM_PROG = (1 << 10),
98  ETM_CTRL_ETMEN = (1 << 11),
100 
101  /* Clocking modes -- up to v2.1, bit 13 */
102  ETM_PORT_FULL_CLOCK = (0 << 13),
103  ETM_PORT_HALF_CLOCK = (1 << 13),
104  ETM_PORT_CLOCK_MASK = (1 << 13),
105 
106  /* bits 15:14 == context ID size used in tracing */
108  ETM_CTRL_CONTEXTID_8 = (1 << 14),
112 
113  /* Port modes -- bits 17:16, tied to clocking mode */
114  ETM_PORT_NORMAL = (0 << 16),
115  ETM_PORT_MUXED = (1 << 16),
116  ETM_PORT_DEMUXED = (2 << 16),
117  ETM_PORT_MODE_MASK = (3 << 16),
118 
119  /* bits 31:18 defined in v3.0 and later (e.g. ARM11+) */
120 };
121 
122 /* forward-declare ETM context */
123 struct etm_context;
124 
126  const char *name;
128  int (*init)(struct etm_context *etm_ctx);
129  trace_status_t (*status)(struct etm_context *etm_ctx);
130  int (*read_trace)(struct etm_context *etm_ctx);
131  int (*start_capture)(struct etm_context *etm_ctx);
132  int (*stop_capture)(struct etm_context *etm_ctx);
133 };
134 
135 enum {
138 };
139 
141  uint8_t pipestat; /* bits 0-2 pipeline status */
142  uint16_t packet; /* packet data (4, 8 or 16 bit) */
143  int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
144 };
145 
146 /* describe a trace context
147  * if support for ETMv2 or ETMv3 is to be implemented,
148  * this will have to be split into version independent elements
149  * and a version specific part
150  */
151 struct etm_context {
152  struct target *target; /* target this ETM is connected to */
153  struct reg_cache *reg_cache; /* ETM register cache */
154  struct etm_capture_driver *capture_driver; /* driver used to access ETM data */
155  void *capture_driver_priv; /* capture driver private data */
156  trace_status_t capture_status; /* current state of capture run */
157  struct etmv1_trace_data *trace_data; /* trace data */
158  uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
159  uint32_t control; /* shadow of ETM_CTRL */
160  int /*arm_state*/ core_state; /* current core state */
161  struct image *image; /* source for target opcodes */
162  uint32_t pipe_index; /* current trace cycle */
163  uint32_t data_index; /* cycle holding next data packet */
164  bool data_half; /* port half on a 16 bit port */
165  bool pc_ok; /* full PC has been acquired */
166  bool ptr_ok; /* whether last_ptr is valid */
167  uint8_t bcd_vers; /* e.g. 0x13 == ETMv1.3 */
168  uint32_t config; /* cache of ETM_CONFIG value */
169  uint32_t id; /* cache of ETM_ID value, or 0 */
170  uint32_t current_pc; /* current program counter */
171  uint32_t last_branch; /* last branch address output */
172  uint32_t last_branch_reason; /* type of last branch encountered */
173  uint32_t last_ptr; /* address of the last data access */
174  uint32_t last_instruction; /* index of last executed (to calc timings) */
175 };
176 
177 /* PIPESTAT values */
178 typedef enum {
179  STAT_IE = 0x0,
180  STAT_ID = 0x1,
181  STAT_IN = 0x2,
182  STAT_WT = 0x3,
183  STAT_BE = 0x4,
184  STAT_BD = 0x5,
185  STAT_TR = 0x6,
186  STAT_TD = 0x7
188 
189 /* branch reason values */
190 typedef enum {
191  BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
192  BR_ENABLE = 0x1, /* Trace has been enabled */
193  BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
194  BR_NODEBUG = 0x3, /* ARM has exited for debug state */
195  BR_PERIOD = 0x4, /* Periodic synchronization point (ETM >= v1.2)*/
196  BR_RSVD5 = 0x5, /* reserved */
197  BR_RSVD6 = 0x6, /* reserved */
198  BR_RSVD7 = 0x7, /* reserved */
200 
202  struct arm_jtag *jtag_info, struct etm_context *etm_ctx);
203 
204 int etm_setup(struct target *target);
205 
206 extern const struct command_registration etm_command_handlers[];
207 
208 #define ERROR_ETM_INVALID_DRIVER (-1300)
209 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
210 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
211 #define ERROR_ETM_ANALYSIS_FAILED (-1303)
212 
213 #endif /* OPENOCD_TARGET_ETM_H */
struct reg_cache * etm_build_reg_cache(struct target *target, struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
Definition: etm.c:278
@ ETMV1_TRIGGER_CYCLE
Definition: etm.h:137
@ ETMV1_TRACESYNC_CYCLE
Definition: etm.h:136
int etm_setup(struct target *target)
Definition: etm.c:417
@ ETM_VIEWDATA_CTRL3
Definition: etm.h:38
@ ETM_STATUS
Definition: etm.h:25
@ ETM_SEQUENCER_STATE
Definition: etm.h:52
@ ETM_VIEWDATA_CTRL2
Definition: etm.h:37
@ ETM_SEQUENCER_EVENT
Definition: etm.h:51
@ ETM_ASIC_CTRL
Definition: etm.h:24
@ ETM_DATA_COMPARATOR_MASK
Definition: etm.h:44
@ ETM_TRACE_EN_EVENT
Definition: etm.h:29
@ ETM_CONFIG
Definition: etm.h:22
@ ETM_TRIG_EVENT
Definition: etm.h:23
@ ETM_EXTERNAL_OUTPUT
Definition: etm.h:54
@ ETM_VIEWDATA_CTRL1
Definition: etm.h:36
@ ETM_TRACE_RESOURCE_CTRL
Definition: etm.h:27
@ ETM_TRACE_EN_CTRL2
Definition: etm.h:28
@ ETM_FIFOFULL_REGION
Definition: etm.h:32
@ ETM_TRACE_EN_CTRL1
Definition: etm.h:30
@ ETM_COUNTER_ENABLE
Definition: etm.h:47
@ ETM_COUNTER_RELOAD_EVENT
Definition: etm.h:48
@ ETM_FIFOFULL_LEVEL
Definition: etm.h:33
@ ETM_CTRL
Definition: etm.h:21
@ ETM_ID
Definition: etm.h:58
@ ETM_ADDR_ACCESS_TYPE
Definition: etm.h:41
@ ETM_VIEWDATA_EVENT
Definition: etm.h:35
@ ETM_DATA_COMPARATOR_VALUE
Definition: etm.h:43
@ ETM_CONTEXTID_COMPARATOR_MASK
Definition: etm.h:57
@ ETM_COUNTER_RELOAD_VALUE
Definition: etm.h:46
@ ETM_ADDR_COMPARATOR_VALUE
Definition: etm.h:40
@ ETM_CONTEXTID_COMPARATOR_VALUE
Definition: etm.h:56
@ ETM_COUNTER_VALUE
Definition: etm.h:49
@ ETM_SYS_CONFIG
Definition: etm.h:26
etmv1_branch_reason_t
Definition: etm.h:190
@ BR_RSVD6
Definition: etm.h:197
@ BR_RSVD5
Definition: etm.h:196
@ BR_ENABLE
Definition: etm.h:192
@ BR_PERIOD
Definition: etm.h:195
@ BR_RSVD7
Definition: etm.h:198
@ BR_NODEBUG
Definition: etm.h:194
@ BR_NORMAL
Definition: etm.h:191
@ BR_RESTART
Definition: etm.h:193
const struct command_registration etm_command_handlers[]
Definition: etm.c:2008
@ ETM_PORT_FULL_CLOCK
Definition: etm.h:102
@ ETM_PORT_4BIT
Definition: etm.h:83
@ ETM_PORT_8BIT
Definition: etm.h:84
@ ETM_CTRL_CONTEXTID_NONE
Definition: etm.h:107
@ ETM_PORT_64BIT
Definition: etm.h:89
@ ETM_PORT_MODE_MASK
Definition: etm.h:117
@ ETM_PORT_HALF_CLOCK
Definition: etm.h:103
@ ETM_PORT_CLOCK_MASK
Definition: etm.h:104
@ ETM_CTRL_CONTEXTID_16
Definition: etm.h:109
@ ETM_CTRL_MONITOR_CPRT
Definition: etm.h:75
@ ETM_CTRL_TRACE_DATA
Definition: etm.h:78
@ ETM_PORT_NORMAL
Definition: etm.h:114
@ ETM_PORT_16BIT
Definition: etm.h:85
@ ETM_PORT_48BIT
Definition: etm.h:88
@ ETM_CTRL_ETMEN
Definition: etm.h:98
@ ETM_CTRL_DBGRQ
Definition: etm.h:96
@ ETM_CTRL_CONTEXTID_8
Definition: etm.h:108
@ ETM_PORT_1BIT
Definition: etm.h:90
@ ETM_PORT_24BIT
Definition: etm.h:86
@ ETM_CTRL_BRANCH_OUTPUT
Definition: etm.h:95
@ ETM_CTRL_CONTEXTID_MASK
Definition: etm.h:111
@ ETM_PORT_32BIT
Definition: etm.h:87
@ ETM_CTRL_TRACE_ADDR
Definition: etm.h:79
@ ETM_PORT_WIDTH_MASK
Definition: etm.h:92
@ ETM_PORT_DEMUXED
Definition: etm.h:116
@ ETM_CTRL_FIFOFULL_STALL
Definition: etm.h:94
@ ETM_PORT_2BIT
Definition: etm.h:91
@ ETM_CTRL_POWERDOWN
Definition: etm.h:74
@ ETM_CTRL_CYCLE_ACCURATE
Definition: etm.h:99
@ ETM_CTRL_ETM_PROG
Definition: etm.h:97
@ ETM_CTRL_TRACE_MASK
Definition: etm.h:80
@ ETM_CTRL_CONTEXTID_32
Definition: etm.h:110
@ ETM_PORT_MUXED
Definition: etm.h:115
etmv1_pipestat_t
Definition: etm.h:178
@ STAT_BD
Definition: etm.h:184
@ STAT_BE
Definition: etm.h:183
@ STAT_ID
Definition: etm.h:180
@ STAT_WT
Definition: etm.h:182
@ STAT_TD
Definition: etm.h:186
@ STAT_TR
Definition: etm.h:185
@ STAT_IN
Definition: etm.h:181
@ STAT_IE
Definition: etm.h:179
int(* stop_capture)(struct etm_context *etm_ctx)
Definition: etm.h:132
int(* init)(struct etm_context *etm_ctx)
Definition: etm.h:128
int(* start_capture)(struct etm_context *etm_ctx)
Definition: etm.h:131
const char * name
Definition: etm.h:126
int(* read_trace)(struct etm_context *etm_ctx)
Definition: etm.h:130
trace_status_t(* status)(struct etm_context *etm_ctx)
Definition: etm.h:129
const struct command_registration * commands
Definition: etm.h:127
struct etm_capture_driver * capture_driver
Definition: etm.h:154
uint32_t last_instruction
Definition: etm.h:174
struct etmv1_trace_data * trace_data
Definition: etm.h:157
uint32_t trace_depth
Definition: etm.h:158
uint32_t control
Definition: etm.h:159
bool ptr_ok
Definition: etm.h:166
bool pc_ok
Definition: etm.h:165
uint32_t last_branch_reason
Definition: etm.h:172
uint32_t id
Definition: etm.h:169
uint32_t current_pc
Definition: etm.h:170
int core_state
Definition: etm.h:160
uint32_t config
Definition: etm.h:168
uint32_t last_branch
Definition: etm.h:171
trace_status_t capture_status
Definition: etm.h:156
struct target * target
Definition: etm.h:152
void * capture_driver_priv
Definition: etm.h:155
bool data_half
Definition: etm.h:164
uint32_t pipe_index
Definition: etm.h:162
uint32_t data_index
Definition: etm.h:163
struct image * image
Definition: etm.h:161
uint32_t last_ptr
Definition: etm.h:173
struct reg_cache * reg_cache
Definition: etm.h:153
uint8_t bcd_vers
Definition: etm.h:167
Definition: etm.h:61
struct arm_jtag * jtag_info
Definition: etm.h:64
const struct etm_reg_info * reg_info
Definition: etm.h:63
uint8_t value[4]
Definition: etm.h:62
uint8_t pipestat
Definition: etm.h:141
uint16_t packet
Definition: etm.h:142
Definition: image.h:48
Definition: target.h:120
enum trace_status trace_status_t