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at91sam9.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /*
4  * Copyright (C) 2009 by Dean Glazeski
5  * dnglaze@gmail.com
6  */
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include <target/arm.h>
13 #include <helper/log.h>
14 #include "imp.h"
15 #include "arm_io.h"
16 
17 #define AT91C_PIOX_SODR (0x30)
18 #define AT91C_PIOX_CODR (0x34)
19 #define AT91C_PIOX_PDSR (0x3C)
20 #define AT91C_ECCX_CR (0x00)
21 #define AT91C_ECCX_SR (0x08)
22 #define AT91C_ECCX_PR (0x0C)
23 #define AT91C_ECCX_NPR (0x10)
28 struct at91sam9_pin {
30  uint32_t pioc;
31 
33  uint32_t num;
34 };
35 
39 struct at91sam9_nand {
41  uint32_t ecc;
42 
44  uint32_t data;
45 
47  uint32_t cmd;
48 
50  uint32_t addr;
51 
53  struct arm_nand_data io;
54 
56  struct at91sam9_pin busy;
57 
59  struct at91sam9_pin ce;
60 };
61 
69 static int at91sam9_halted(struct target *target, const char *label)
70 {
71  if (target->state == TARGET_HALTED)
72  return true;
73 
74  LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
75  return false;
76 }
77 
84 static int at91sam9_init(struct nand_device *nand)
85 {
86  struct target *target = nand->target;
87 
88  if (!at91sam9_halted(target, "init"))
90 
91  return ERROR_OK;
92 }
93 
100 static int at91sam9_enable(struct nand_device *nand)
101 {
102  struct at91sam9_nand *info = nand->controller_priv;
103  struct target *target = nand->target;
104 
105  return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
106 }
107 
114 static int at91sam9_disable(struct nand_device *nand)
115 {
116  struct at91sam9_nand *info = nand->controller_priv;
117  struct target *target = nand->target;
118 
119  return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
120 }
121 
129 static int at91sam9_command(struct nand_device *nand, uint8_t command)
130 {
131  struct at91sam9_nand *info = nand->controller_priv;
132  struct target *target = nand->target;
133 
134  if (!at91sam9_halted(target, "command"))
136 
137  at91sam9_enable(nand);
138 
139  return target_write_u8(target, info->cmd, command);
140 }
141 
148 static int at91sam9_reset(struct nand_device *nand)
149 {
150  if (!at91sam9_halted(nand->target, "reset"))
152 
153  return at91sam9_disable(nand);
154 }
155 
163 static int at91sam9_address(struct nand_device *nand, uint8_t address)
164 {
165  struct at91sam9_nand *info = nand->controller_priv;
166  struct target *target = nand->target;
167 
168  if (!at91sam9_halted(nand->target, "address"))
170 
171  return target_write_u8(target, info->addr, address);
172 }
173 
182 static int at91sam9_read_data(struct nand_device *nand, void *data)
183 {
184  struct at91sam9_nand *info = nand->controller_priv;
185  struct target *target = nand->target;
186 
187  if (!at91sam9_halted(nand->target, "read data"))
189 
190  return target_read_u8(target, info->data, data);
191 }
192 
201 static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
202 {
203  struct at91sam9_nand *info = nand->controller_priv;
204  struct target *target = nand->target;
205 
206  if (!at91sam9_halted(target, "write data"))
208 
209  return target_write_u8(target, info->data, data);
210 }
211 
219 static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
220 {
221  struct at91sam9_nand *info = nand->controller_priv;
222  struct target *target = nand->target;
223  uint32_t status;
224 
225  if (!at91sam9_halted(target, "nand ready"))
226  return 0;
227 
228  do {
230 
231  if (status & (1 << info->busy.num))
232  return 1;
233 
234  alive_sleep(1);
235  } while (timeout-- > 0);
236 
237  return 0;
238 }
239 
249 static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
250 {
251  struct at91sam9_nand *info = nand->controller_priv;
252  struct arm_nand_data *io = &info->io;
253  int status;
254 
255  if (!at91sam9_halted(nand->target, "read block"))
257 
258  io->chunk_size = nand->page_size;
259  status = arm_nandread(io, data, size);
260 
261  return status;
262 }
263 
273 static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
274 {
275  struct at91sam9_nand *info = nand->controller_priv;
276  struct arm_nand_data *io = &info->io;
277  int status;
278 
279  if (!at91sam9_halted(nand->target, "write block"))
281 
282  io->chunk_size = nand->page_size;
283  status = arm_nandwrite(io, data, size);
284 
285  return status;
286 }
287 
295 static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
296 {
297  if (!info->ecc) {
298  LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
300  }
301 
302  /* reset ECC parity registers */
303  return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
304 }
305 
316 static uint8_t *at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
317 {
318  if (!oob) {
319  /* user doesn't want OOB, allocate it */
320  if (nand->page_size == 512)
321  *size = 16;
322  else if (nand->page_size == 2048)
323  *size = 64;
324 
325  oob = malloc(*size);
326  if (!oob) {
327  LOG_ERROR("Unable to allocate space for OOB");
328  return NULL;
329  }
330 
331  memset(oob, 0xFF, *size);
332  }
333 
334  return oob;
335 }
336 
350 static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
351  uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
352 {
353  int retval;
354  struct at91sam9_nand *info = nand->controller_priv;
355  struct target *target = nand->target;
356  uint8_t *oob_data;
357  uint32_t status;
358 
359  retval = at91sam9_ecc_init(target, info);
360  if (retval != ERROR_OK)
361  return retval;
362 
363  retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
364  if (retval != ERROR_OK)
365  return retval;
366 
367  if (data) {
368  retval = nand_read_data_page(nand, data, data_size);
369  if (retval != ERROR_OK)
370  return retval;
371  }
372 
373  oob_data = at91sam9_oob_init(nand, oob, &oob_size);
374  retval = nand_read_data_page(nand, oob_data, oob_size);
375  if (retval == ERROR_OK && data) {
377  if (status & 1) {
378  LOG_ERROR("Error detected!");
379  if (status & 4)
380  LOG_ERROR("Multiple errors encountered; unrecoverable!");
381  else {
382  /* attempt recovery */
383  uint32_t parity;
384 
386  info->ecc + AT91C_ECCX_PR,
387  &parity);
388  uint32_t word = (parity & 0x0000FFF0) >> 4;
389  uint32_t bit = parity & 0x0F;
390 
391  data[word] ^= (0x1) << bit;
392  LOG_INFO("Data word %d, bit %d corrected.",
393  (unsigned) word,
394  (unsigned) bit);
395  }
396  }
397 
398  if (status & 2) {
399  /* we could write back correct ECC data */
400  LOG_ERROR("Error in ECC bytes detected");
401  }
402  }
403 
404  if (!oob) {
405  /* if it wasn't asked for, free it */
406  free(oob_data);
407  }
408 
409  return retval;
410 }
411 
425 static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
426  uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
427 {
428  struct at91sam9_nand *info = nand->controller_priv;
429  struct target *target = nand->target;
430  int retval;
431  uint8_t *oob_data = oob;
432  uint32_t parity, nparity;
433 
434  retval = at91sam9_ecc_init(target, info);
435  if (retval != ERROR_OK)
436  return retval;
437 
438  retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
439  if (retval != ERROR_OK)
440  return retval;
441 
442  if (data) {
443  retval = nand_write_data_page(nand, data, data_size);
444  if (retval != ERROR_OK) {
445  LOG_ERROR("Unable to write data to NAND device");
446  return retval;
447  }
448  }
449 
450  oob_data = at91sam9_oob_init(nand, oob, &oob_size);
451 
452  if (!oob) {
453  /* no OOB given, so read in the ECC parity from the ECC controller */
455  target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
456 
457  oob_data[0] = (uint8_t) parity;
458  oob_data[1] = (uint8_t) (parity >> 8);
459  oob_data[2] = (uint8_t) nparity;
460  oob_data[3] = (uint8_t) (nparity >> 8);
461  }
462 
463  retval = nand_write_data_page(nand, oob_data, oob_size);
464 
465  if (!oob)
466  free(oob_data);
467 
468  if (retval != ERROR_OK) {
469  LOG_ERROR("Unable to write OOB data to NAND");
470  return retval;
471  }
472 
473  retval = nand_write_finish(nand);
474 
475  return retval;
476 }
477 
483 NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
484 {
485  unsigned long chip = 0, ecc = 0;
486  struct at91sam9_nand *info = NULL;
487 
488  LOG_DEBUG("AT91SAM9 NAND Device Command");
489 
490  if (CMD_ARGC < 3 || CMD_ARGC > 4) {
491  LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
493  }
494 
495  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
496  if (chip == 0) {
497  LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
499  }
500 
501  if (CMD_ARGC == 4) {
502  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
503  if (ecc == 0) {
504  LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
506  }
507  }
508 
509  info = calloc(1, sizeof(*info));
510  if (!info) {
511  LOG_ERROR("unable to allocate space for controller private data");
513  }
514 
515  info->data = chip;
516  info->cmd = chip | (1 << 22);
517  info->addr = chip | (1 << 21);
518  info->ecc = ecc;
519 
520  nand->controller_priv = info;
521  info->io.target = nand->target;
522  info->io.data = info->data;
523  info->io.op = ARM_NAND_NONE;
524 
525  return ERROR_OK;
526 }
527 
532 COMMAND_HANDLER(handle_at91sam9_cle_command)
533 {
534  struct nand_device *nand = NULL;
535  struct at91sam9_nand *info = NULL;
536  unsigned num, address_line;
537 
538  if (CMD_ARGC != 2) {
539  command_print(CMD, "incorrect number of arguments for 'at91sam9 cle' command");
540  return ERROR_OK;
541  }
542 
543  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
544  nand = get_nand_device_by_num(num);
545  if (!nand) {
546  command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
547  return ERROR_OK;
548  }
549 
550  info = nand->controller_priv;
551 
552  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
553  info->cmd = info->data | (1 << address_line);
554 
555  return ERROR_OK;
556 }
557 
562 COMMAND_HANDLER(handle_at91sam9_ale_command)
563 {
564  struct nand_device *nand = NULL;
565  struct at91sam9_nand *info = NULL;
566  unsigned num, address_line;
567 
568  if (CMD_ARGC != 2)
570 
571  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
572  nand = get_nand_device_by_num(num);
573  if (!nand) {
574  command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
576  }
577 
578  info = nand->controller_priv;
579 
580  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
581  info->addr = info->data | (1 << address_line);
582 
583  return ERROR_OK;
584 }
585 
590 COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
591 {
592  struct nand_device *nand = NULL;
593  struct at91sam9_nand *info = NULL;
594  unsigned num, base_pioc, pin_num;
595 
596  if (CMD_ARGC != 3)
598 
599  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
600  nand = get_nand_device_by_num(num);
601  if (!nand) {
602  command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
604  }
605 
606  info = nand->controller_priv;
607 
608  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
609  info->busy.pioc = base_pioc;
610 
611  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
612  info->busy.num = pin_num;
613 
614  return ERROR_OK;
615 }
616 
621 COMMAND_HANDLER(handle_at91sam9_ce_command)
622 {
623  struct nand_device *nand = NULL;
624  struct at91sam9_nand *info = NULL;
625  unsigned num, base_pioc, pin_num;
626 
627  if (CMD_ARGC != 3)
629 
630  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
631  nand = get_nand_device_by_num(num);
632  if (!nand) {
633  command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
635  }
636 
637  info = nand->controller_priv;
638 
639  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
640  info->ce.pioc = base_pioc;
641 
642  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
643  info->ce.num = pin_num;
644 
645  return ERROR_OK;
646 }
647 
648 static const struct command_registration at91sam9_sub_command_handlers[] = {
649  {
650  .name = "cle",
651  .handler = handle_at91sam9_cle_command,
652  .mode = COMMAND_CONFIG,
653  .help = "set command latch enable address line (default is 22)",
654  .usage = "bank_id address_line",
655  },
656  {
657  .name = "ale",
658  .handler = handle_at91sam9_ale_command,
659  .mode = COMMAND_CONFIG,
660  .help = "set address latch enable address line (default is 21)",
661  .usage = "bank_id address_line",
662  },
663  {
664  .name = "rdy_busy",
665  .handler = handle_at91sam9_rdy_busy_command,
666  .mode = COMMAND_CONFIG,
667  .help = "set the GPIO input pin connected to "
668  "the RDY/~BUSY signal (no default)",
669  .usage = "bank_id pio_base_addr pin_num",
670  },
671  {
672  .name = "ce",
673  .handler = handle_at91sam9_ce_command,
674  .mode = COMMAND_CONFIG,
675  .help = "set the GPIO output pin connected to "
676  "the chip enable signal (no default)",
677  .usage = "bank_id pio_base_addr pin_num",
678  },
680 };
681 
682 static const struct command_registration at91sam9_command_handler[] = {
683  {
684  .name = "at91sam9",
685  .mode = COMMAND_ANY,
686  .help = "AT91SAM9 NAND flash controller commands",
687  .usage = "",
689  },
691 };
692 
697  .name = "at91sam9",
698  .nand_device_command = at91sam9_nand_device_command,
699  .commands = at91sam9_command_handler,
700  .init = at91sam9_init,
701  .command = at91sam9_command,
702  .reset = at91sam9_reset,
703  .address = at91sam9_address,
704  .read_data = at91sam9_read_data,
705  .write_data = at91sam9_write_data,
706  .nand_ready = at91sam9_nand_ready,
707  .read_block_data = at91sam9_read_block_data,
708  .write_block_data = at91sam9_write_block_data,
709  .read_page = at91sam9_read_page,
710  .write_page = at91sam9_write_page,
711 };
Holds the interface to ARM cores.
const char * label
Definition: arm_cti.c:164
int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
ARM-specific bulk write from buffer to address of 8-bit wide NAND.
Definition: arm_io.c:80
int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
Uses an on-chip algorithm for an ARM device to read from a NAND device and store the data into the ho...
Definition: arm_io.c:190
@ ARM_NAND_NONE
No operation performed.
Definition: arm_io.h:13
static int at91sam9_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC controller on chip.
Definition: at91sam9.c:350
static int at91sam9_read_data(struct nand_device *nand, void *data)
Read data directly from the NAND device attached to an AT91SAM9 NAND controller.
Definition: at91sam9.c:182
static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
Determine if the NAND device is ready by looking at the ready/~busy pin.
Definition: at91sam9.c:219
static int at91sam9_command(struct nand_device *nand, uint8_t command)
Send a command to the NAND device.
Definition: at91sam9.c:129
static int at91sam9_enable(struct nand_device *nand)
Enable NAND device attached to a controller.
Definition: at91sam9.c:100
COMMAND_HANDLER(handle_at91sam9_cle_command)
Handle the AT91SAM9 CLE command for specifying the address line to use for writing commands to a NAND...
Definition: at91sam9.c:532
struct nand_flash_controller at91sam9_nand_controller
Structure representing the AT91SAM9 NAND controller.
Definition: at91sam9.c:696
static int at91sam9_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Write a page of data including 1-bit ECC information to a NAND device attached to an AT91SAM9 control...
Definition: at91sam9.c:425
static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
Read a block of data from the NAND device attached to an AT91SAM9.
Definition: at91sam9.c:249
static int at91sam9_halted(struct target *target, const char *label)
Checks if the target is halted and prints an error message if it isn't.
Definition: at91sam9.c:69
static const struct command_registration at91sam9_sub_command_handlers[]
Definition: at91sam9.c:648
static int at91sam9_reset(struct nand_device *nand)
Reset the AT91SAM9 NAND controller.
Definition: at91sam9.c:148
#define AT91C_ECCX_SR
Offset to ECC SR.
Definition: at91sam9.c:21
static int at91sam9_disable(struct nand_device *nand)
Disable NAND device attached to a controller.
Definition: at91sam9.c:114
static uint8_t * at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
Initialize an area for the OOB based on whether a user is requesting the OOB data.
Definition: at91sam9.c:316
static const struct command_registration at91sam9_command_handler[]
Definition: at91sam9.c:682
static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
Initialize the ECC controller on the AT91SAM9.
Definition: at91sam9.c:295
static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
Write a block of data to a NAND device attached to an AT91SAM9.
Definition: at91sam9.c:273
static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
Write data directly to the NAND device attached to an AT91SAM9 NAND controller.
Definition: at91sam9.c:201
#define AT91C_ECCX_PR
Offset to ECC PR.
Definition: at91sam9.c:22
static int at91sam9_address(struct nand_device *nand, uint8_t address)
Send an address to the NAND device attached to an AT91SAM9 NAND controller.
Definition: at91sam9.c:163
#define AT91C_ECCX_NPR
Offset to ECC NPR.
Definition: at91sam9.c:23
static int at91sam9_init(struct nand_device *nand)
Initialize the AT91SAM9 NAND controller.
Definition: at91sam9.c:84
#define AT91C_PIOX_SODR
Offset to PIO SODR.
Definition: at91sam9.c:17
NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
Handle the initial NAND device command for AT91SAM9 controllers.
Definition: at91sam9.c:483
#define AT91C_ECCX_CR
Offset to ECC CR.
Definition: at91sam9.c:20
#define AT91C_PIOX_CODR
Offset to PIO CODR.
Definition: at91sam9.c:18
#define AT91C_PIOX_PDSR
Offset to PIO PDSR.
Definition: at91sam9.c:19
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:387
@ COMMAND_CONFIG
Definition: command.h:41
@ COMMAND_ANY
Definition: command.h:42
ecc
Definition: davinci.c:22
int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
int nand_write_finish(struct nand_device *nand)
struct nand_device * get_nand_device_by_num(int num)
int nand_page_command(struct nand_device *nand, uint32_t page, uint8_t cmd, bool oob_only)
void alive_sleep(uint64_t ms)
Definition: log.c:460
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_INFO(expr ...)
Definition: log.h:117
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
#define ERROR_NAND_OPERATION_FAILED
Definition: nand/core.h:214
@ NAND_CMD_SEQIN
Definition: nand/core.h:148
@ NAND_CMD_READ0
Definition: nand/core.h:140
static uint32_t bit(uint32_t value, unsigned int b)
Definition: opcodes.h:15
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
The arm_nand_data struct is used for defining NAND I/O operations on an ARM core.
Definition: arm_io.h:22
unsigned chunk_size
The chunk size is the page size or ECC chunk.
Definition: arm_io.h:30
uint32_t data
Where data is read from or written to.
Definition: arm_io.h:33
Private data for the controller that is stored in the NAND device structure.
Definition: at91sam9.c:39
struct at91sam9_pin ce
Pin representing the chip enable.
Definition: at91sam9.c:59
uint32_t data
Address data is written to.
Definition: at91sam9.c:44
uint32_t cmd
Address commands are written to.
Definition: at91sam9.c:47
uint32_t ecc
Address of the ECC controller for NAND.
Definition: at91sam9.c:41
struct at91sam9_pin busy
Pin representing the ready/~busy line.
Definition: at91sam9.c:56
uint32_t addr
Address addresses are written to.
Definition: at91sam9.c:50
struct arm_nand_data io
I/O structure for hosted reads/writes.
Definition: at91sam9.c:53
Representation of a pin on an AT91SAM9 chip.
Definition: at91sam9.c:28
uint32_t pioc
Address of the PIO controller.
Definition: at91sam9.c:30
uint32_t num
Pin number.
Definition: at91sam9.c:33
const char * name
Definition: command.h:229
void * controller_priv
Definition: nand/core.h:51
int page_size
Definition: nand/core.h:56
struct target * target
Definition: nand/core.h:49
Interface for NAND flash controllers.
Definition: nand/driver.h:23
const char * name
Driver name that is used to select it from configuration files.
Definition: nand/driver.h:25
Definition: target.h:120
enum target_state state
Definition: target.h:162
Definition: psoc6.c:84
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
Definition: target.c:2749
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2664
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2616
@ TARGET_HALTED
Definition: target.h:55
static struct ublast_lowlevel_priv info
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
static unsigned int parity(unsigned int v)
Definition: xscale.c:623