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armv8_opcodes.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /*
4  * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com>
5  */
6 
7 #ifdef HAVE_CONFIG_H
8 #include "config.h"
9 #endif
10 
11 #include <stdint.h>
12 #include <stdbool.h>
13 
14 #include "armv8.h"
15 #include "armv8_opcodes.h"
16 
17 static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
29  [ARMV8_OPC_DCPS] = ARMV8_DCPS(0, 11),
35  [ARMV8_OPC_HLT] = ARMV8_HLT(11),
42 };
43 
44 static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
45  [READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
46  [READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
47  [READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
48  [READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
49  [WRITE_REG_CSSELR] = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
50  [READ_REG_MPIDR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
51  [READ_REG_DTRRX] = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
52  [WRITE_REG_DTRTX] = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
59  [ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
60  [ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
61  [ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
69 };
70 
71 void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
72 {
73  if (state_is_aarch64)
74  armv8->opcodes = &a64_opcodes[0];
75  else
76  armv8->opcodes = &t32_opcodes[0];
77 }
78 
79 uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode code)
80 {
81  if ((int)code >= ARMV8_OPC_NUM)
82  return -1;
83 
84  return *(armv8->opcodes + code);
85 }
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:198
static const uint32_t a64_opcodes[ARMV8_OPC_NUM]
Definition: armv8_opcodes.c:17
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
Definition: armv8_opcodes.c:71
static const uint32_t t32_opcodes[ARMV8_OPC_NUM]
Definition: armv8_opcodes.c:44
uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode code)
Definition: armv8_opcodes.c:79
#define ARMV8_HLT_T1(im)
#define SYSTEM_CSSELR
Definition: armv8_opcodes.h:68
#define ARMV8_LDRW_IP_T3(rd, rn)
#define ARMV8_STRW_IP_T3(rd, rn)
#define ARMV8_MSR_GP(system, rt)
#define ARMV8_ISB
#define SYSTEM_ICIVAU
Definition: armv8_opcodes.h:74
#define ARMV8_MCR_DSPSR(rt)
#define SYSTEM_DCCIVAC
Definition: armv8_opcodes.h:76
#define SYSTEM_CLIDR
Definition: armv8_opcodes.h:67
#define ARMV8_LDRH_IP(rd, rn)
#define ARMV8_DRPS
#define ARMV8_ERET_T1
#define ARMV8_LDRB_IP_T3(rd, rn)
#define ARMV8_STRB_IP(rd, rn)
#define ARMV8_MRS_DSPSR(rt)
#define ARMV8_ISB_SY_T1
#define ARMV8_MRS(system, rt)
#define ARMV8_DCPS_T1(el)
#define ARMV8_STRB_IP_T3(rd, rn)
#define ARMV8_HLT(im)
#define ARMV8_SYS(system, rt)
#define SYSTEM_CTR
Definition: armv8_opcodes.h:70
#define SYSTEM_CCSIDR
Definition: armv8_opcodes.h:66
#define ARMV8_LDRW_IP(rd, rn)
#define ARMV8_LDRH_IP_T3(rd, rn)
#define ARMV8_DSB_SY
#define ARMV8_DCPS(el, im)
#define ARMV8_MSR_DSPSR(rt)
#define ARMV8_STRW_IP(rd, rn)
#define ARMV8_LDRB_IP(rd, rn)
armv8_opcode
@ ARMV8_OPC_DCCISW
@ READ_REG_CCSIDR
@ ARMV8_OPC_LDRW_IP
@ ARMV8_OPC_ISB_SY
@ WRITE_REG_DSPSR
@ ARMV8_OPC_LDRB_IP
@ WRITE_REG_DTRTX
@ READ_REG_CTR
@ READ_REG_DSPSR
@ READ_REG_MPIDR
@ ARMV8_OPC_LDRH_IP
@ WRITE_REG_CSSELR
@ READ_REG_DTRRX
@ ARMV8_OPC_DCPS
@ ARMV8_OPC_STRH_IP
@ ARMV8_OPC_HLT
@ ARMV8_OPC_STRW_IP
@ READ_REG_CLIDR
@ ARMV8_OPC_DCCIVAC
@ ARMV8_OPC_STRB_IP
@ ARMV8_OPC_NUM
@ ARMV8_OPC_DRPS
@ ARMV8_OPC_DSB_SY
@ ARMV8_OPC_ICIVAU
@ READ_REG_CSSELR
#define ARMV8_STRH_IP(rd, rn)
#define ARMV8_MRC_DSPSR(rt)
#define SYSTEM_MPIDR
Definition: armv8_opcodes.h:78
#define ARMV8_STRH_IP_T3(rd, rn)
#define ARMV8_DSB_SY_T1
#define SYSTEM_DBG_DTRTX_EL0
Definition: armv8_opcodes.h:63
#define SYSTEM_DCCISW
Definition: armv8_opcodes.h:72
#define SYSTEM_DBG_DTRRX_EL0
Definition: armv8_opcodes.h:62
const uint32_t * opcodes
Definition: armv8.h:191