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riscv-013_reg.c File Reference
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Enumerations

enum  misa_mxl { MISA_MXL_INVALID = 0 , MISA_MXL_32 = 1 , MISA_MXL_64 = 2 , MISA_MXL_128 = 3 }
 

Functions

static int assume_reg_exist (struct target *target, uint32_t regno)
 Some registers are optional (e.g. More...
 
static int check_misa_mxl (const struct target *target)
 
static int examine_misa (struct target *target)
 
static int examine_mtopi (struct target *target)
 
static int examine_vlenb (struct target *target)
 
static int examine_xlen (struct target *target)
 
static int init_cache_entry (struct target *target, uint32_t regno)
 
unsigned int mxl_to_xlen (enum misa_mxl mxl)
 
static const struct reg_arch_type * riscv013_gdb_regno_reg_type (uint32_t regno)
 
int riscv013_reg_examine_all (struct target *target)
 This function assumes target's DM to be initialized (target is able to access DMs registers, execute program buffer, etc.) More...
 
static int riscv013_reg_get (struct reg *reg)
 
int riscv013_reg_save (struct target *target, enum gdb_regno regid)
 This function is used to save the value of a register in cache. More...
 
static int riscv013_reg_set (struct reg *reg, uint8_t *buf)
 

Enumeration Type Documentation

◆ misa_mxl

enum misa_mxl
Enumerator
MISA_MXL_INVALID 
MISA_MXL_32 
MISA_MXL_64 
MISA_MXL_128 

Definition at line 165 of file riscv-013_reg.c.

Function Documentation

◆ assume_reg_exist()

static int assume_reg_exist ( struct target *  target,
uint32_t  regno 
)
static

Some registers are optional (e.g.

"misa"). For such registers it is first assumed they exist (via "assume_reg_exist()"), then the read is attempted (via the usual "riscv_reg_get()") and if the read fails, the register is marked as non-existing (via "riscv_reg_impl_set_exist()").

Definition at line 101 of file riscv-013_reg.c.

References riscv013_gdb_regno_reg_type(), and riscv_reg_impl_init_cache_entry().

Referenced by examine_mtopi(), and examine_vlenb().

◆ check_misa_mxl()

static int check_misa_mxl ( const struct target *  target)
static

◆ examine_misa()

static int examine_misa ( struct target *  target)
static

◆ examine_mtopi()

static int examine_mtopi ( struct target *  target)
static

◆ examine_vlenb()

◆ examine_xlen()

◆ init_cache_entry()

static int init_cache_entry ( struct target *  target,
uint32_t  regno 
)
static

◆ mxl_to_xlen()

unsigned int mxl_to_xlen ( enum misa_mxl  mxl)

Definition at line 172 of file riscv-013_reg.c.

References MISA_MXL_128, MISA_MXL_32, MISA_MXL_64, and MISA_MXL_INVALID.

Referenced by check_misa_mxl().

◆ riscv013_gdb_regno_reg_type()

static const struct reg_arch_type* riscv013_gdb_regno_reg_type ( uint32_t  regno)
static

Definition at line 76 of file riscv-013_reg.c.

References reg_arch_type::get, riscv013_reg_get(), and riscv013_reg_set().

Referenced by assume_reg_exist(), and init_cache_entry().

◆ riscv013_reg_examine_all()

int riscv013_reg_examine_all ( struct target *  target)

This function assumes target's DM to be initialized (target is able to access DMs registers, execute program buffer, etc.)

This file describes additional register cache interface available to the RISC-V Debug Specification v0.13+ targets.

Definition at line 296 of file riscv-013_reg.c.

References ERROR_OK, examine_misa(), examine_mtopi(), examine_vlenb(), examine_xlen(), GDB_REGNO_S0, GDB_REGNO_S1, init_cache_entry(), init_shared_reg_info(), reg_cache::num_regs, target::reg_cache, riscv_reg_impl_expose_csrs(), riscv_reg_impl_hide_csrs(), riscv_reg_impl_init_cache(), riscv_reg_impl_init_vector_reg_type(), target::state, and TARGET_HALTED.

Referenced by examine().

◆ riscv013_reg_get()

◆ riscv013_reg_save()

◆ riscv013_reg_set()