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Functions | |
| static const struct reg_arch_type * | riscv011_gdb_regno_reg_type (uint32_t regno) |
| static int | riscv011_reg_get (struct reg *reg) |
| int | riscv011_reg_init_all (struct target *target) |
| This file describes additional register cache interface available to the RISC-V Debug Specification v0.11 targets. More... | |
| static int | riscv011_reg_set (struct reg *reg, uint8_t *buf) |
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Definition at line 30 of file riscv-011_reg.c.
References reg_arch_type::get, riscv011_reg_get(), and riscv011_reg_set().
Referenced by riscv011_reg_init_all().
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Definition at line 12 of file riscv-011_reg.c.
References buf_set_u64(), ERROR_OK, reg::number, riscv011_get_register(), riscv_reg_impl_get_target(), reg::size, and reg::value.
Referenced by riscv011_gdb_regno_reg_type().
| int riscv011_reg_init_all | ( | struct target * | target | ) |
This file describes additional register cache interface available to the RISC-V Debug Specification v0.11 targets.
Initialize register cache. After this function all registers can be safely accessed via functions described here and in riscv_reg.h.
Definition at line 40 of file riscv-011_reg.c.
References ARRAY_SIZE, ERROR_FAIL, ERROR_OK, GDB_REGNO_MTOPEI, GDB_REGNO_MTOPI, GDB_REGNO_VLENB, init_shared_reg_info(), reg_cache::num_regs, target::reg_cache, riscv011_gdb_regno_reg_type(), RISCV_INFO, riscv_reg_impl_cache_entry(), riscv_reg_impl_expose_csrs(), riscv_reg_impl_gdb_regno_exist(), riscv_reg_impl_hide_csrs(), riscv_reg_impl_init_cache(), riscv_reg_impl_init_cache_entry(), and riscv_reg_impl_is_initialized().
Referenced by examine(), and init_target().
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Definition at line 23 of file riscv-011_reg.c.
References buf_get_u64(), reg::number, riscv011_set_register(), riscv_reg_impl_get_target(), and reg::size.
Referenced by riscv011_gdb_regno_reg_type().