OpenOCD
niietcm4.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by Bogdan Kolbov *
5  * kolbov@niiet.ru *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "imp.h"
13 #include <helper/binarybuffer.h>
14 #include <target/algorithm.h>
15 #include <target/armv7m.h>
16 
17 #define FLASH_DRIVER_VER 0x00010000
18 #define CHIPID_ADDR 0xF0000000
19 #define K1921VK01T_ID 0x00000000
20 
21 /*==============================================================================
22  * FLASH CONTROL REGS
23  *==============================================================================
24  */
25 
26 #define MAIN_MEM_TYPE 0
27 #define INFO_MEM_TYPE 1
28 #define SERVICE_MODE_ERASE_ADDR 0x80030164
29 #define MAGIC_KEY 0xA442
30 
31 /*-- BOOTFLASH ---------------------------------------------------------------*/
32 #define BOOTFLASH_BASE 0xA001C000
33 #define FMA (BOOTFLASH_BASE + 0x00)
34 #define FMD1 (BOOTFLASH_BASE + 0x04)
35 #define FMC (BOOTFLASH_BASE + 0x08)
36 #define FCIS (BOOTFLASH_BASE + 0x0C)
37 #define FCIM (BOOTFLASH_BASE + 0x10)
38 #define FCIC (BOOTFLASH_BASE + 0x14)
39 #define FMD2 (BOOTFLASH_BASE + 0x50)
40 #define FMD3 (BOOTFLASH_BASE + 0x54)
41 #define FMD4 (BOOTFLASH_BASE + 0x58)
42 
43 
44 /*---- FMC: Command register */
45 #define FMC_WRITE (1<<0) /* Writing in main region */
46 #define FMC_PAGE_ERASE (1<<1) /* Page erase the main region */
47 #define FMC_FULL_ERASE (1<<2) /* Erase full flash */
48 #define FMC_WRITE_IFB (1<<4) /* Writing in info region */
49 #define FMC_PAGEERASE_IFB (1<<5) /* Erase page of info region */
50 #define FMC_MAGIC_KEY (MAGIC_KEY<<16) /* Operation run command */
51 
52 /*---- FCIS: Status register */
53 #define FCIS_OP_CMLT (1<<0) /* Completion flag operation */
54 #define FCIS_OP_ERROR (1<<1) /* Flag operation error */
55 
56 /*---- FCIC: CLear status register */
57 #define FCIC_CLR_OPCMLT (1<<0) /* Clear completion flag in register FCIS */
58 #define FCIC_CLR_OPERROR (1<<1) /* Clear error flag in register FCIS */
59 
60 /*-- USERFLASH ---------------------------------------------------------------*/
61 #define USERFLASH_PAGE_SIZE 256
62 #define USERFLASH_PAGE_TOTALNUM 256
63 
64 #define USERFLASH_BASE 0xA0022000
65 #define UFMA (USERFLASH_BASE + 0x00)
66 #define UFMD (USERFLASH_BASE + 0x04)
67 #define UFMC (USERFLASH_BASE + 0x08)
68 #define UFCIS (USERFLASH_BASE + 0x0C)
69 #define UFCIM (USERFLASH_BASE + 0x10)
70 #define UFCIC (USERFLASH_BASE + 0x14)
71 
72 /*---- UFMC: Command register */
73 #define UFMC_WRITE (1<<0) /* Writing in main region */
74 #define UFMC_PAGE_ERASE (1<<1) /* Paged erase the main region */
75 #define UFMC_FULL_ERASE (1<<2) /* Erase full flash */
76 #define UFMC_READ (1<<3) /* Reading from main region */
77 #define UFMC_WRITE_IFB (1<<4) /* Writing in info region */
78 #define UFMC_PAGEERASE_IFB (1<<5) /* Erase page of info region */
79 #define UFMC_READ_IFB (1<<6) /* Reading from info region */
80 #define UFMC_MAGIC_KEY (MAGIC_KEY<<16) /* Operation run command */
81 
82 /*---- UFCIS: Status register */
83 #define UFCIS_OP_CMLT (1<<0) /* Completion flag operation */
84 #define UFCIS_OP_ERROR (1<<1) /* Flag operation error */
85 
86 /*---- UFCIC: CLear status register */
87 #define UFCIC_CLR_OPCMLT (1<<0) /* Clear completion flag in register FCIS */
88 #define UFCIC_CLR_OPERROR (1<<1) /* Clear error flag in register FCIS */
89 
90 /*---- In info userflash address space */
91 #define INFOWORD0_ADDR 0x00
92 #define INFOWORD0_BOOTFROM_IFB (1<<0) /* Boot from bootflash or bootflash_ifb */
93 #define INFOWORD0_EN_GPIO (1<<1) /* Remap to 0x00000000 extmem or bootflash */
94 #define INFOWORD0_BOOTFROM_IFB_POS 0
95 #define INFOWORD0_EN_GPIO_POS 1
96 #define INFOWORD0_EXTMEM_SEL_POS 3 /* Choose altfunc of gpio to work with extmem */
97 
98 #define INFOWORD1_ADDR 0x01
99 #define INFOWORD1_PINNUM_POS 0 /* Choose gpio pin number to control extmem boot */
100 #define INFOWORD1_PORTNUM_POS 4 /* Choose gpio port to control extmem boot */
101 
102 #define INFOWORD2_ADDR 0x02
103 #define INFOWORD2_LOCK_IFB_BF (1<<0) /* Protect info part of bootflash */
104 
105 #define INFOWORD3_ADDR 0x03
106 #define INFOWORD3_LOCK_IFB_UF (1<<0) /* Protect info part of userflash */
107 
108 #define BF_LOCK_ADDR 0x40
109 #define UF_LOCK_ADDR 0x80
110 
114 struct niietcm4_flash_bank {
115  /* target params */
116  bool probed;
117  uint32_t chipid;
118  char *chip_name;
119  char chip_brief[4096];
120  /* not mapped userflash params */
121  uint32_t uflash_width;
122  uint32_t uflash_size;
123  uint32_t uflash_pagetotal;
124  uint32_t uflash_info_size;
125  uint32_t uflash_info_pagetotal;
126  /* boot params */
127  bool bflash_info_remap;
128  char *extmem_boot_port;
129  uint32_t extmem_boot_pin;
130  uint32_t extmem_boot_altfunc;
131  bool extmem_boot;
132 };
133 
134 /*==============================================================================
135  * HELPER FUNCTIONS
136  *==============================================================================
137  */
138 
142 static int niietcm4_opstatus_check(struct flash_bank *bank)
143 {
144  struct target *target = bank->target;
145  int retval;
146  int timeout = 5000;
147 
148  uint32_t flash_status;
149  retval = target_read_u32(target, FCIS, &flash_status);
150  if (retval != ERROR_OK)
151  return retval;
152 
153  while (flash_status == 0x00) {
154  retval = target_read_u32(target, FCIS, &flash_status);
155  if (retval != ERROR_OK)
156  return retval;
157  if (timeout-- <= 0) {
158  LOG_ERROR("Bootflash operation timeout");
159  return ERROR_FLASH_OPERATION_FAILED;
160  }
161  busy_sleep(1); /* can use busy sleep for short times. */
162  }
163  if (flash_status == FCIS_OP_ERROR) {
164  LOG_ERROR("Bootflash operation error");
165  return ERROR_FLASH_OPERATION_FAILED;
166  }
167  /* clear status */
168  uint32_t flash_cmd = FCIC_CLR_OPCMLT | FCIC_CLR_OPERROR;
169  retval = target_write_u32(target, FCIC, flash_cmd);
170  if (retval != ERROR_OK)
171  return retval;
172 
173  return retval;
174 }
175 
179 static int niietcm4_uopstatus_check(struct flash_bank *bank)
180 {
181  struct target *target = bank->target;
182  int retval;
183  int timeout = 5000;
184 
185  uint32_t uflash_status;
186  retval = target_read_u32(target, UFCIS, &uflash_status);
187  if (retval != ERROR_OK)
188  return retval;
189 
190  while (uflash_status == 0x00) {
191  retval = target_read_u32(target, UFCIS, &uflash_status);
192  if (retval != ERROR_OK)
193  return retval;
194  if (timeout-- <= 0) {
195  LOG_ERROR("Userflash operation timeout");
196  return ERROR_FLASH_OPERATION_FAILED;
197  }
198  busy_sleep(1); /* can use busy sleep for short times. */
199  }
200  if (uflash_status == UFCIS_OP_ERROR) {
201  LOG_ERROR("Userflash operation error");
202  return ERROR_FLASH_OPERATION_FAILED;
203  }
204  /* clear status */
205  uint32_t uflash_cmd = UFCIC_CLR_OPCMLT | UFCIC_CLR_OPERROR;
206  retval = target_write_u32(target, UFCIC, uflash_cmd);
207  if (retval != ERROR_OK)
208  return retval;
209 
210  return retval;
211 }
212 
219 static int niietcm4_dump_uflash_page(struct flash_bank *bank, uint32_t *dump, int page_num, int mem_type)
220 {
221  struct target *target = bank->target;
222  int i;
223  int retval = ERROR_OK;
224 
225  uint32_t uflash_cmd;
226  if (mem_type == INFO_MEM_TYPE)
227  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
228  else
229  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ;
230 
231  int first = page_num*USERFLASH_PAGE_SIZE;
232  int last = first + USERFLASH_PAGE_SIZE;
233 
234  for (i = first; i < last; i++) {
235  retval = target_write_u32(target, UFMA, i);
236  if (retval != ERROR_OK)
237  return retval;
238  retval = target_write_u32(target, UFMC, uflash_cmd);
239  if (retval != ERROR_OK)
240  return retval;
241  retval = niietcm4_uopstatus_check(bank);
242  if (retval != ERROR_OK)
243  return retval;
244  retval = target_read_u32(target, UFMD, &dump[i]);
245  if (retval != ERROR_OK)
246  return retval;
247  }
248 
249  return retval;
250 }
251 
255 static int niietcm4_load_uflash_page(struct flash_bank *bank, uint32_t *dump, int page_num, int mem_type)
256 {
257  struct target *target = bank->target;
258  int i;
259  int retval = ERROR_OK;
260 
261  uint32_t uflash_cmd;
262  if (mem_type == INFO_MEM_TYPE)
263  uflash_cmd = UFMC_MAGIC_KEY | UFMC_WRITE_IFB;
264  else
265  uflash_cmd = UFMC_MAGIC_KEY | UFMC_WRITE;
266 
267  int first = page_num*USERFLASH_PAGE_SIZE;
268  int last = first + USERFLASH_PAGE_SIZE;
269 
270  for (i = first; i < last; i++) {
271  retval = target_write_u32(target, UFMA, i);
272  if (retval != ERROR_OK)
273  return retval;
274  retval = target_write_u32(target, UFMD, dump[i]);
275  if (retval != ERROR_OK)
276  return retval;
277  retval = target_write_u32(target, UFMC, uflash_cmd);
278  if (retval != ERROR_OK)
279  return retval;
280  retval = niietcm4_uopstatus_check(bank);
281  if (retval != ERROR_OK)
282  return retval;
283  }
284 
285  return retval;
286 }
287 
291 static int niietcm4_uflash_page_erase(struct flash_bank *bank, int page_num, int mem_type)
292 {
293  struct target *target = bank->target;
294  int retval;
295 
296  uint32_t uflash_cmd;
297  if (mem_type == INFO_MEM_TYPE)
298  uflash_cmd = UFMC_MAGIC_KEY | UFMC_PAGEERASE_IFB;
299  else
300  uflash_cmd = UFMC_MAGIC_KEY | UFMC_PAGE_ERASE;
301 
302  retval = target_write_u32(target, UFMA, page_num*USERFLASH_PAGE_SIZE);
303  if (retval != ERROR_OK)
304  return retval;
305  retval = target_write_u32(target, UFMD, 0xFF);
306  if (retval != ERROR_OK)
307  return retval;
308  retval = target_write_u32(target, UFMC, uflash_cmd);
309  if (retval != ERROR_OK)
310  return retval;
311  /* status check */
312  retval = niietcm4_uopstatus_check(bank);
313  if (retval != ERROR_OK)
314  return retval;
315 
316  return retval;
317 }
318 
322 static int niietcm4_uflash_protect(struct flash_bank *bank, int mem_type,
323  int set, unsigned int first, unsigned int last)
324 {
325  int retval;
326  if (mem_type == INFO_MEM_TYPE) {
327  /* read dump */
328  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
329  retval = niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
330  if (retval != ERROR_OK)
331  return retval;
332  /* modify dump */
333  if (set)
334  uflash_dump[INFOWORD2_ADDR] &= ~INFOWORD3_LOCK_IFB_UF;
335  else
336  uflash_dump[INFOWORD2_ADDR] |= INFOWORD3_LOCK_IFB_UF;
337  /* erase page 0 userflash */
338  retval = niietcm4_uflash_page_erase(bank, 0, 1);
339  if (retval != ERROR_OK)
340  return retval;
341  /* write dump to userflash */
342  retval = niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
343  if (retval != ERROR_OK)
344  return retval;
345  } else {
346  /* read dump */
347  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
348  retval = niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
349  if (retval != ERROR_OK)
350  return retval;
351  /* modify dump */
352  for (unsigned int i = first; i <= last; i++) {
353  uint32_t reg_num = i/8;
354  uint32_t bit_num = i%8;
355  if (set)
356  uflash_dump[UF_LOCK_ADDR+reg_num] &= ~(1<<bit_num);
357  else
358  uflash_dump[UF_LOCK_ADDR+reg_num] |= (1<<bit_num);
359  }
360  /* erase page 0 info userflash */
361  retval = niietcm4_uflash_page_erase(bank, 0, 1);
362  if (retval != ERROR_OK)
363  return retval;
364  /* write dump to userflash */
365  retval = niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
366  if (retval != ERROR_OK)
367  return retval;
368  }
369 
370  return retval;
371 }
372 
373 /*==============================================================================
374  * FLASH COMMANDS
375  *==============================================================================
376  */
377 COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command)
378 {
379  if (CMD_ARGC < 3)
380  return ERROR_COMMAND_SYNTAX_ERROR;
381 
382  struct flash_bank *bank;
383  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
384  if (retval != ERROR_OK)
385  return retval;
386  struct target *target = bank->target;
387 
388  /* skip over flash bank */
389  CMD_ARGC--;
390  CMD_ARGV++;
391 
392  uint32_t uflash_addr;
393  uint32_t uflash_cmd;
394  uint32_t uflash_data;
395 
396  if (strcmp("info", CMD_ARGV[0]) == 0)
397  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
398  else if (strcmp("main", CMD_ARGV[0]) == 0)
399  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ;
400  else
401  return ERROR_COMMAND_SYNTAX_ERROR;
402 
403  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], uflash_addr);
404 
405  retval = target_write_u32(target, UFMA, uflash_addr);
406  if (retval != ERROR_OK)
407  return retval;
408  retval = target_write_u32(target, UFMC, uflash_cmd);
409  if (retval != ERROR_OK)
410  return retval;
411  /* status check */
412  retval = niietcm4_uopstatus_check(bank);
413  if (retval != ERROR_OK)
414  return retval;
415  retval = target_read_u32(target, UFMD, &uflash_data);
416  if (retval != ERROR_OK)
417  return retval;
418  command_print(CMD, "Read userflash %s region:\n"
419  "address = 0x%04" PRIx32 ",\n"
420  "value = 0x%02" PRIx32 ".", CMD_ARGV[0], uflash_addr, uflash_data);
421  return retval;
422 }
423 
424 COMMAND_HANDLER(niietcm4_handle_uflash_write_byte_command)
425 {
426  if (CMD_ARGC < 4)
427  return ERROR_COMMAND_SYNTAX_ERROR;
428 
429  struct flash_bank *bank;
430  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
431  if (retval != ERROR_OK)
432  return retval;
433  struct target *target = bank->target;
434 
435  if (target->state != TARGET_HALTED) {
436  LOG_ERROR("Target not halted");
437  return ERROR_TARGET_NOT_HALTED;
438  }
439 
440  /* skip over flash bank */
441  CMD_ARGC--;
442  CMD_ARGV++;
443 
444  uint32_t uflash_addr;
445  uint32_t uflash_data;
446  int mem_type;
447 
448  if (strcmp("info", CMD_ARGV[0]) == 0)
449  mem_type = 1;
450  else if (strcmp("main", CMD_ARGV[0]) == 0)
451  mem_type = 0;
452  else
453  return ERROR_COMMAND_SYNTAX_ERROR;
454 
455  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], uflash_addr);
456  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], uflash_data);
457 
458  int page_num = uflash_addr/USERFLASH_PAGE_SIZE;
459 
460  command_print(CMD, "Write userflash %s region:\n"
461  "address = 0x%04" PRIx32 ",\n"
462  "value = 0x%02" PRIx32 ".\n"
463  "Please wait ... ", CMD_ARGV[0], uflash_addr, uflash_data);
464  /* dump */
465  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
466  niietcm4_dump_uflash_page(bank, uflash_dump, page_num, mem_type);
467 
468  /* modify dump */
469  uflash_dump[uflash_addr%USERFLASH_PAGE_SIZE] = uflash_data;
470 
471  /* erase page userflash */
472  niietcm4_uflash_page_erase(bank, page_num, mem_type);
473 
474  /* write dump to userflash */
475  niietcm4_load_uflash_page(bank, uflash_dump, page_num, mem_type);
476  command_print(CMD, "done!");
477  return retval;
478 }
479 
480 COMMAND_HANDLER(niietcm4_handle_uflash_full_erase_command)
481 {
482  if (CMD_ARGC < 1)
483  return ERROR_COMMAND_SYNTAX_ERROR;
484 
485  struct flash_bank *bank;
486  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
487  if (retval != ERROR_OK)
488  return retval;
489  struct target *target = bank->target;
490 
491  if (target->state != TARGET_HALTED) {
492  LOG_ERROR("Target not halted");
493  return ERROR_TARGET_NOT_HALTED;
494  }
495 
496  uint32_t uflash_addr = 0;
497  uint32_t uflash_data = 0xFF;
498  uint32_t uflash_cmd = UFMC_MAGIC_KEY | UFMC_FULL_ERASE;
499 
500  retval = target_write_u32(target, UFMA, uflash_addr);
501  if (retval != ERROR_OK)
502  return retval;
503  retval = target_write_u32(target, UFMD, uflash_data);
504  if (retval != ERROR_OK)
505  return retval;
506  retval = target_write_u32(target, UFMC, uflash_cmd);
507  if (retval != ERROR_OK)
508  return retval;
509  /* status check */
510  retval = niietcm4_uopstatus_check(bank);
511  if (retval != ERROR_OK)
512  return retval;
513  command_print(CMD, "Userflash full erase done!");
514 
515  return retval;
516 }
517 
518 COMMAND_HANDLER(niietcm4_handle_uflash_erase_command)
519 {
520  if (CMD_ARGC < 4)
521  return ERROR_COMMAND_SYNTAX_ERROR;
522 
523  struct flash_bank *bank;
524  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
525  if (retval != ERROR_OK)
526  return retval;
527  struct target *target = bank->target;
528 
529  if (target->state != TARGET_HALTED) {
530  LOG_ERROR("Target not halted");
531  return ERROR_TARGET_NOT_HALTED;
532  }
533 
534  /* skip over flash bank */
535  CMD_ARGC--;
536  CMD_ARGV++;
537 
538  unsigned int first, last;
539  int mem_type;
540 
541  if (strcmp("info", CMD_ARGV[0]) == 0)
542  mem_type = 1;
543  else if (strcmp("main", CMD_ARGV[0]) == 0)
544  mem_type = 0;
545  else
546  return ERROR_COMMAND_SYNTAX_ERROR;
547 
548  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], first);
549  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], last);
550  for (unsigned int i = first; i <= last; i++) {
551  retval = niietcm4_uflash_page_erase(bank, i, mem_type);
552  if (retval != ERROR_OK)
553  return retval;
554  }
555 
556  command_print(CMD, "Erase %s userflash pages %u through %u done!", CMD_ARGV[0], first, last);
557 
558  return retval;
559 }
560 
561 COMMAND_HANDLER(niietcm4_handle_uflash_protect_check_command)
562 {
563  if (CMD_ARGC < 2)
564  return ERROR_COMMAND_SYNTAX_ERROR;
565 
566  struct flash_bank *bank;
567  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
568  if (retval != ERROR_OK)
569  return retval;
570 
571  struct target *target = bank->target;
572  if (target->state != TARGET_HALTED) {
573  LOG_ERROR("Target not halted");
574  return ERROR_TARGET_NOT_HALTED;
575  }
576 
577  /* skip over flash bank */
578  CMD_ARGC--;
579  CMD_ARGV++;
580 
581  int mem_type;
582  if (strcmp("info", CMD_ARGV[0]) == 0)
583  mem_type = 1;
584  else if (strcmp("main", CMD_ARGV[0]) == 0)
585  mem_type = 0;
586  else
587  return ERROR_COMMAND_SYNTAX_ERROR;
588 
589  int i, j;
590  uint32_t uflash_addr;
591  uint32_t uflash_cmd;
592  uint32_t uflash_data;
593 
594  /* chose between main userflash and info userflash */
595  if (mem_type == INFO_MEM_TYPE) {
596  uflash_addr = INFOWORD3_ADDR;
597  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
598  retval = target_write_u32(target, UFMA, uflash_addr);
599  if (retval != ERROR_OK)
600  return retval;
601  retval = target_write_u32(target, UFMC, uflash_cmd);
602  if (retval != ERROR_OK)
603  return retval;
604 
605  /* status check */
606  retval = niietcm4_uopstatus_check(bank);
607  if (retval != ERROR_OK)
608  return retval;
609  retval = target_read_u32(target, UFMD, &uflash_data);
610  if (retval != ERROR_OK)
611  return retval;
612 
613  if (uflash_data & INFOWORD3_LOCK_IFB_UF)
614  command_print(CMD, "All sectors of info userflash are not protected!");
615  else
616  command_print(CMD, "All sectors of info userflash are protected!");
617  } else {
618  uflash_addr = UF_LOCK_ADDR;
619  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
620  for (i = 0; i < USERFLASH_PAGE_TOTALNUM/8; i++) {
621  retval = target_write_u32(target, UFMA, uflash_addr);
622  if (retval != ERROR_OK)
623  return retval;
624  retval = target_write_u32(target, UFMC, uflash_cmd);
625  if (retval != ERROR_OK)
626  return retval;
627 
628  /* status check */
629  retval = niietcm4_uopstatus_check(bank);
630  if (retval != ERROR_OK)
631  return retval;
632  retval = target_read_u32(target, UFMD, &uflash_data);
633  if (retval != ERROR_OK)
634  return retval;
635 
636  for (j = 0; j < 8; j++) {
637  if (uflash_data & 0x1)
638  command_print(CMD, "Userflash sector #%03d: 0x%04x (0x100) is not protected!",
639  i*8+j, (i*8+j)*USERFLASH_PAGE_SIZE);
640  else
641  command_print(CMD, "Userflash sector #%03d: 0x%04x (0x100) is protected!",
642  i*8+j, (i*8+j)*USERFLASH_PAGE_SIZE);
643  uflash_data = uflash_data >> 1;
644  }
645  uflash_addr++;
646  }
647  }
648 
649  return retval;
650 }
651 
652 COMMAND_HANDLER(niietcm4_handle_uflash_protect_command)
653 {
654  if (CMD_ARGC < 5)
655  return ERROR_COMMAND_SYNTAX_ERROR;
656 
657  struct flash_bank *bank;
658  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
659  if (retval != ERROR_OK)
660  return retval;
661  struct target *target = bank->target;
662 
663  if (target->state != TARGET_HALTED) {
664  LOG_ERROR("Target not halted");
665  return ERROR_TARGET_NOT_HALTED;
666  }
667 
668  /* skip over flash bank */
669  CMD_ARGC--;
670  CMD_ARGV++;
671 
672  int mem_type;
673  if (strcmp("info", CMD_ARGV[0]) == 0)
674  mem_type = 1;
675  else if (strcmp("main", CMD_ARGV[0]) == 0)
676  mem_type = 0;
677  else
678  return ERROR_COMMAND_SYNTAX_ERROR;
679 
680  unsigned int first, last;
681  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], first);
682  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], last);
683 
684  int set;
685  if (strcmp("on", CMD_ARGV[3]) == 0) {
686  command_print(CMD, "Try to enable %s userflash sectors %u through %u protection. Please wait ... ",
687  CMD_ARGV[0], first, last);
688  set = 1;
689  } else if (strcmp("off", CMD_ARGV[3]) == 0) {
690  command_print(CMD, "Try to disable %s userflash sectors %u through %u protection. Please wait ... ",
691  CMD_ARGV[0], first, last);
692  set = 0;
693  } else
694  return ERROR_COMMAND_SYNTAX_ERROR;
695 
696  retval = niietcm4_uflash_protect(bank, mem_type, set, first, last);
697  if (retval != ERROR_OK)
698  return retval;
699 
700  command_print(CMD, "done!");
701  return retval;
702 }
703 
704 COMMAND_HANDLER(niietcm4_handle_bflash_info_remap_command)
705 {
706  if (CMD_ARGC < 2)
707  return ERROR_COMMAND_SYNTAX_ERROR;
708 
709  struct flash_bank *bank;
710  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
711  if (retval != ERROR_OK)
712  return retval;
713  struct target *target = bank->target;
714 
715  if (target->state != TARGET_HALTED) {
716  LOG_ERROR("Target not halted");
717  return ERROR_TARGET_NOT_HALTED;
718  }
719 
720  /* skip over flash bank */
721  CMD_ARGC--;
722  CMD_ARGV++;
723 
724  int set;
725  if (strcmp("on", CMD_ARGV[0]) == 0) {
726  command_print(CMD, "Try to enable bootflash info region remap. Please wait ...");
727  set = 1;
728  } else if (strcmp("off", CMD_ARGV[0]) == 0) {
729  command_print(CMD, "Try to disable bootflash info region remap. Please wait ...");
730  set = 0;
731  } else
732  return ERROR_COMMAND_SYNTAX_ERROR;
733 
734  /* dump */
735  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
736  niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
737 
738  /* modify dump */
739  if (set)
740  uflash_dump[INFOWORD0_ADDR] &= ~INFOWORD0_BOOTFROM_IFB;
741  else
742  uflash_dump[INFOWORD0_ADDR] |= INFOWORD0_BOOTFROM_IFB;
743 
744  /* erase page userflash */
745  niietcm4_uflash_page_erase(bank, 0, 1);
746 
747  /* write dump to userflash */
748  niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
749  command_print(CMD, "done!");
750 
751  return retval;
752 }
753 
754 COMMAND_HANDLER(niietcm4_handle_extmem_cfg_command)
755 {
756  if (CMD_ARGC < 4)
757  return ERROR_COMMAND_SYNTAX_ERROR;
758 
759  struct flash_bank *bank;
760  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
761  if (retval != ERROR_OK)
762  return retval;
763  struct target *target = bank->target;
764 
765  if (target->state != TARGET_HALTED) {
766  LOG_ERROR("Target not halted");
767  return ERROR_TARGET_NOT_HALTED;
768  }
769 
770  /* skip over flash bank */
771  CMD_ARGC--;
772  CMD_ARGV++;
773 
774  uint32_t port;
775  if (strcmp("gpioa", CMD_ARGV[0]) == 0)
776  port = 8;
777  else if (strcmp("gpiob", CMD_ARGV[0]) == 0)
778  port = 9;
779  else if (strcmp("gpioc", CMD_ARGV[0]) == 0)
780  port = 10;
781  else if (strcmp("gpiod", CMD_ARGV[0]) == 0)
782  port = 11;
783  else if (strcmp("gpioe", CMD_ARGV[0]) == 0)
784  port = 12;
785  else if (strcmp("gpiof", CMD_ARGV[0]) == 0)
786  port = 13;
787  else if (strcmp("gpiog", CMD_ARGV[0]) == 0)
788  port = 14;
789  else if (strcmp("gpioh", CMD_ARGV[0]) == 0)
790  port = 15;
791  else
792  return ERROR_COMMAND_SYNTAX_ERROR;
793 
794  uint32_t pin;
795  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pin);
796  if (pin > 15)
797  return ERROR_COMMAND_SYNTAX_ERROR;
798 
799  uint32_t func;
800  if (strcmp("func1", CMD_ARGV[2]) == 0)
801  func = 0;
802  else if (strcmp("func3", CMD_ARGV[2]) == 0)
803  func = 3;
804  else
805  return ERROR_COMMAND_SYNTAX_ERROR;
806 
807  command_print(CMD, "Try to configure external memory boot interface:\n"
808  "port = %s\n"
809  "pin = %s\n"
810  "func = %s\n"
811  "Please wait ...", CMD_ARGV[0], CMD_ARGV[1], CMD_ARGV[2]);
812  /* dump */
813  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
814  niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
815 
816  /* modify dump */
817  uflash_dump[INFOWORD0_ADDR] &= ~(3<<INFOWORD0_EXTMEM_SEL_POS);
818  uflash_dump[INFOWORD0_ADDR] |= func<<INFOWORD0_EXTMEM_SEL_POS;
819  uflash_dump[INFOWORD1_ADDR] = (port<<INFOWORD1_PORTNUM_POS) | (pin<<INFOWORD1_PINNUM_POS);
820 
821  /* erase page userflash */
822  niietcm4_uflash_page_erase(bank, 0, 1);
823 
824  /* write dump to userflash */
825  niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
826  command_print(CMD, "done!");
827 
828  return retval;
829 }
830 
831 COMMAND_HANDLER(niietcm4_handle_extmem_boot_command)
832 {
833  if (CMD_ARGC < 2)
834  return ERROR_COMMAND_SYNTAX_ERROR;
835 
836  struct flash_bank *bank;
837  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
838  if (retval != ERROR_OK)
839  return retval;
840  struct target *target = bank->target;
841 
842  if (target->state != TARGET_HALTED) {
843  LOG_ERROR("Target not halted");
844  return ERROR_TARGET_NOT_HALTED;
845  }
846 
847  /* skip over flash bank */
848  CMD_ARGC--;
849  CMD_ARGV++;
850 
851  int set;
852 
853  if (strcmp("on", CMD_ARGV[0]) == 0) {
854  command_print(CMD, "Try to enable boot from external memory. Please wait ...");
855  set = 1;
856  } else if (strcmp("off", CMD_ARGV[0]) == 0) {
857  command_print(CMD, "Try to disable boot from external memory. Please wait ...");
858  set = 0;
859  } else
860  return ERROR_COMMAND_SYNTAX_ERROR;
861 
862  /* dump */
863  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
864  niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
865 
866  /* modify dump */
867  if (set)
868  uflash_dump[INFOWORD0_ADDR] &= ~INFOWORD0_EN_GPIO;
869  else
870  uflash_dump[INFOWORD0_ADDR] |= INFOWORD0_EN_GPIO;
871 
872  /* erase page userflash */
873  niietcm4_uflash_page_erase(bank, 0, 1);
874 
875  /* write dump to userflash */
876  niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
877  command_print(CMD, "done!");
878 
879  return retval;
880 }
881 
882 COMMAND_HANDLER(niietcm4_handle_service_mode_erase_command)
883 {
884  if (CMD_ARGC < 1)
885  return ERROR_COMMAND_SYNTAX_ERROR;
886 
887  struct flash_bank *bank;
888  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
889  if (retval != ERROR_OK)
890  return retval;
891  struct target *target = bank->target;
892 
893  command_print(CMD, "Try to perform service mode erase. Please wait ...");
894 
895  retval = target_write_u32(target, SERVICE_MODE_ERASE_ADDR, 1);
896  if (retval != ERROR_OK)
897  return retval;
898 
899  int timeout = 500;
900  uint32_t status;
901 
902  retval = target_read_u32(target, SERVICE_MODE_ERASE_ADDR, &status);
903  if (retval != ERROR_OK)
904  return retval;
905 
906  while (status != 0x03) {
907  retval = target_read_u32(target, SERVICE_MODE_ERASE_ADDR, &status);
908  if (retval != ERROR_OK)
909  return retval;
910  if (timeout-- <= 0) {
911  LOG_ERROR("Service mode erase timeout");
912  return ERROR_FLASH_OPERATION_FAILED;
913  }
914  busy_sleep(1); /* can use busy sleep for short times. */
915  }
916  command_print(CMD, "done! All data erased.");
917 
918  return retval;
919 }
920 
921 COMMAND_HANDLER(niietcm4_handle_driver_info_command)
922 {
923  if (CMD_ARGC < 1)
924  return ERROR_COMMAND_SYNTAX_ERROR;
925 
926  struct flash_bank *bank;
927  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
928  if (retval != ERROR_OK)
929  return retval;
930 
931  command_print(CMD, "niietcm4 flash driver\n"
932  "version: %d.%d\n"
933  "author: Bogdan Kolbov\n"
934  "mail: kolbov@niiet.ru",
935  FLASH_DRIVER_VER>>16,
936  FLASH_DRIVER_VER&0xFFFF);
937 
938  return retval;
939 }
940 
941 static const struct command_registration niietcm4_exec_command_handlers[] = {
942  {
943  .name = "uflash_read_byte",
944  .handler = niietcm4_handle_uflash_read_byte_command,
945  .mode = COMMAND_EXEC,
946  .usage = "bank_id ('main'|'info') address",
947  .help = "Read byte from main or info userflash region",
948  },
949  {
950  .name = "uflash_write_byte",
951  .handler = niietcm4_handle_uflash_write_byte_command,
952  .mode = COMMAND_EXEC,
953  .usage = "bank_id ('main'|'info') address value",
954  .help = "Write byte to main or info userflash region",
955  },
956  {
957  .name = "uflash_full_erase",
958  .handler = niietcm4_handle_uflash_full_erase_command,
959  .mode = COMMAND_EXEC,
960  .usage = "bank_id",
961  .help = "Erase all userflash including info region",
962  },
963  {
964  .name = "uflash_erase",
965  .handler = niietcm4_handle_uflash_erase_command,
966  .mode = COMMAND_EXEC,
967  .usage = "bank_id ('main'|'info') first_sector_num last_sector_num",
968  .help = "Erase sectors of main or info userflash region, starting at sector first up to and including last.",
969  },
970  {
971  .name = "uflash_protect_check",
972  .handler = niietcm4_handle_uflash_protect_check_command,
973  .mode = COMMAND_EXEC,
974  .usage = "bank_id ('main'|'info')",
975  .help = "Check sectors protect.",
976  },
977  {
978  .name = "uflash_protect",
979  .handler = niietcm4_handle_uflash_protect_command,
980  .mode = COMMAND_EXEC,
981  .usage = "bank_id ('main'|'info') first_sector_num last_sector_num ('on'|'off')",
982  .help = "Protect sectors of main or info userflash region, starting at sector first up to and including last.",
983  },
984  {
985  .name = "bflash_info_remap",
986  .handler = niietcm4_handle_bflash_info_remap_command,
987  .mode = COMMAND_EXEC,
988  .usage = "bank_id ('on'|'off')",
989  .help = "Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).",
990  },
991  {
992  .name = "extmem_cfg",
993  .handler = niietcm4_handle_extmem_cfg_command,
994  .mode = COMMAND_EXEC,
995  .usage = "bank_id ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')",
996  .help = "Configure external memory interface for boot.",
997  },
998  {
999  .name = "extmem_boot",
1000  .handler = niietcm4_handle_extmem_boot_command,
1001  .mode = COMMAND_EXEC,
1002  .usage = "bank_id ('on'|'off')",
1003  .help = "Enable boot from external memory.",
1004  },
1005  {
1006  .name = "service_mode_erase",
1007  .handler = niietcm4_handle_service_mode_erase_command,
1008  .mode = COMMAND_EXEC,
1009  .usage = "bank_id",
1010  .help = "Perform emergency erase of all flash (bootflash and userflash).",
1011  },
1012  {
1013  .name = "driver_info",
1014  .handler = niietcm4_handle_driver_info_command,
1015  .mode = COMMAND_EXEC,
1016  .usage = "bank_id",
1017  .help = "Show information about flash driver.",
1018  },
1019  COMMAND_REGISTRATION_DONE
1020 };
1021 
1022 static const struct command_registration niietcm4_command_handlers[] = {
1023  {
1024  .name = "niietcm4",
1025  .mode = COMMAND_ANY,
1026  .help = "niietcm4 flash command group",
1027  .usage = "",
1028  .chain = niietcm4_exec_command_handlers,
1029  },
1030  COMMAND_REGISTRATION_DONE
1031 };
1032 
1033 /*==============================================================================
1034  * FLASH INTERFACE
1035  *==============================================================================
1036  */
1037 
1038 FLASH_BANK_COMMAND_HANDLER(niietcm4_flash_bank_command)
1039 {
1040  struct niietcm4_flash_bank *niietcm4_info;
1041 
1042  if (CMD_ARGC < 6)
1043  return ERROR_COMMAND_SYNTAX_ERROR;
1044 
1045  niietcm4_info = malloc(sizeof(struct niietcm4_flash_bank));
1046 
1047  bank->driver_priv = niietcm4_info;
1048 
1049  /* information will be updated by probing */
1050  niietcm4_info->probed = false;
1051  niietcm4_info->chipid = 0;
1052  niietcm4_info->chip_name = NULL;
1053  niietcm4_info->uflash_width = 0;
1054  niietcm4_info->uflash_size = 0;
1055  niietcm4_info->uflash_pagetotal = 0;
1056  niietcm4_info->uflash_info_size = 0;
1057  niietcm4_info->uflash_info_pagetotal = 0;
1058  niietcm4_info->bflash_info_remap = false;
1059  niietcm4_info->extmem_boot_port = NULL;
1060  niietcm4_info->extmem_boot_pin = 0;
1061  niietcm4_info->extmem_boot_altfunc = 0;
1062  niietcm4_info->extmem_boot = false;
1063 
1064  return ERROR_OK;
1065 }
1066 
1067 static int niietcm4_protect_check(struct flash_bank *bank)
1068 {
1069  struct target *target = bank->target;
1070  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1071 
1072  int retval = ERROR_FLASH_OPERATION_FAILED;
1073  int set;
1074  uint32_t uflash_addr;
1075  uint32_t uflash_cmd;
1076  uint32_t uflash_data;
1077  /* chose between main bootflash and info bootflash */
1078  if (niietcm4_info->bflash_info_remap) {
1079  uflash_addr = INFOWORD2_ADDR;
1080  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
1081  retval = target_write_u32(target, UFMA, uflash_addr);
1082  if (retval != ERROR_OK)
1083  return retval;
1084  retval = target_write_u32(target, UFMC, uflash_cmd);
1085  if (retval != ERROR_OK)
1086  return retval;
1087 
1088  /* status check */
1089  retval = niietcm4_uopstatus_check(bank);
1090  if (retval != ERROR_OK)
1091  return retval;
1092  retval = target_read_u32(target, UFMD, &uflash_data);
1093  if (retval != ERROR_OK)
1094  return retval;
1095 
1096  if (uflash_data & INFOWORD2_LOCK_IFB_BF)
1097  set = 0;
1098  else
1099  set = 1;
1100  bank->sectors[0].is_protected = set;
1101  } else {
1102  uflash_addr = BF_LOCK_ADDR;
1103  uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
1104  for (unsigned int i = 0; i < bank->num_sectors/8; i++) {
1105  retval = target_write_u32(target, UFMA, uflash_addr);
1106  if (retval != ERROR_OK)
1107  return retval;
1108  retval = target_write_u32(target, UFMC, uflash_cmd);
1109  if (retval != ERROR_OK)
1110  return retval;
1111 
1112  /* status check */
1113  retval = niietcm4_uopstatus_check(bank);
1114  if (retval != ERROR_OK)
1115  return retval;
1116  retval = target_read_u32(target, UFMD, &uflash_data);
1117  if (retval != ERROR_OK)
1118  return retval;
1119 
1120  for (int j = 0; j < 8; j++) {
1121  if (uflash_data & 0x1)
1122  set = 0;
1123  else
1124  set = 1;
1125  bank->sectors[i*8+j].is_protected = set;
1126  uflash_data = uflash_data >> 1;
1127  }
1128  uflash_addr++;
1129  }
1130  }
1131 
1132  return retval;
1133 }
1134 
1135 static int niietcm4_mass_erase(struct flash_bank *bank)
1136 {
1137  struct target *target = bank->target;
1138 
1139  int retval;
1140  uint32_t flash_cmd;
1141 
1142  /* start mass erase */
1143  flash_cmd = FMC_MAGIC_KEY | FMC_FULL_ERASE;
1144  retval = target_write_u32(target, FMC, flash_cmd);
1145  if (retval != ERROR_OK)
1146  return retval;
1147 
1148  /* status check */
1149  retval = niietcm4_opstatus_check(bank);
1150  if (retval != ERROR_OK)
1151  return retval;
1152 
1153  return retval;
1154 }
1155 
1156 static int niietcm4_erase(struct flash_bank *bank, unsigned int first,
1157  unsigned int last)
1158 {
1159  struct target *target = bank->target;
1160  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1161  int retval = ERROR_FLASH_OPERATION_FAILED;
1162 
1163  if (bank->target->state != TARGET_HALTED) {
1164  LOG_ERROR("Target not halted");
1165  return ERROR_TARGET_NOT_HALTED;
1166  }
1167 
1168  if (first == 0 && last == (bank->num_sectors - 1))
1169  return niietcm4_mass_erase(bank);
1170 
1171  /* chose between main bootflash and info bootflash */
1172  uint32_t flash_cmd, flash_addr;
1173  if (niietcm4_info->bflash_info_remap)
1174  flash_cmd = FMC_MAGIC_KEY | FMC_PAGEERASE_IFB;
1175  else
1176  flash_cmd = FMC_MAGIC_KEY | FMC_PAGE_ERASE;
1177 
1178  /* erasing pages */
1179  unsigned int page_size = bank->size / bank->num_sectors;
1180  for (unsigned int i = first; i <= last; i++) {
1181  /* current page addr */
1182  flash_addr = i*page_size;
1183  retval = target_write_u32(target, FMA, flash_addr);
1184  if (retval != ERROR_OK)
1185  return retval;
1186 
1187  /* start erase */
1188  retval = target_write_u32(target, FMC, flash_cmd);
1189  if (retval != ERROR_OK)
1190  return retval;
1191 
1192  /* status check */
1193  retval = niietcm4_opstatus_check(bank);
1194  if (retval != ERROR_OK)
1195  return retval;
1196  }
1197 
1198  return retval;
1199 }
1200 
1201 static int niietcm4_protect(struct flash_bank *bank, int set,
1202  unsigned int first, unsigned int last)
1203 {
1204  struct target *target = bank->target;
1205  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1206 
1207  int retval;
1208 
1209  if (target->state != TARGET_HALTED) {
1210  LOG_ERROR("Target not halted");
1211  return ERROR_TARGET_NOT_HALTED;
1212  }
1213 
1214  LOG_INFO("Please wait ..."); /* it`s quite a long process */
1215  /* chose between main bootflash and info bootflash */
1216  if (niietcm4_info->bflash_info_remap) {
1217  /* dump */
1218  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
1219  retval = niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
1220  if (retval != ERROR_OK)
1221  return retval;
1222  /* modify dump */
1223  if (set)
1224  uflash_dump[INFOWORD2_ADDR] &= ~INFOWORD2_LOCK_IFB_BF;
1225  else
1226  uflash_dump[INFOWORD2_ADDR] |= INFOWORD2_LOCK_IFB_BF;
1227  /* erase page 0 userflash */
1228  retval = niietcm4_uflash_page_erase(bank, 0, 1);
1229  if (retval != ERROR_OK)
1230  return retval;
1231  /* write dump to userflash */
1232  retval = niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
1233  if (retval != ERROR_OK)
1234  return retval;
1235  } else {
1236  /* read dump*/
1237  uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
1238  retval = niietcm4_dump_uflash_page(bank, uflash_dump, 0, 1);
1239  if (retval != ERROR_OK)
1240  return retval;
1241  /* modify dump */
1242  for (unsigned int i = first; i <= last; i++) {
1243  uint32_t reg_num = i/8;
1244  uint32_t bit_num = i%8;
1245  if (set)
1246  uflash_dump[BF_LOCK_ADDR+reg_num] &= ~(1<<bit_num);
1247  else
1248  uflash_dump[BF_LOCK_ADDR+reg_num] |= (1<<bit_num);
1249  }
1250  /* erase page 0 info userflash */
1251  retval = niietcm4_uflash_page_erase(bank, 0, 1);
1252  if (retval != ERROR_OK)
1253  return retval;
1254  /* write dump to userflash */
1255  retval = niietcm4_load_uflash_page(bank, uflash_dump, 0, 1);
1256  if (retval != ERROR_OK)
1257  return retval;
1258  }
1259 
1260  return retval;
1261 }
1262 
1263 static int niietcm4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1264  uint32_t offset, uint32_t count)
1265 {
1266  struct target *target = bank->target;
1267  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1268  uint32_t buffer_size = 32768 + 8; /* 8 bytes for rp and wp */
1269  struct working_area *write_algorithm;
1270  struct working_area *source;
1271  uint32_t address = bank->base + offset;
1272  struct reg_param reg_params[5];
1273  struct armv7m_algorithm armv7m_info;
1274  int retval = ERROR_OK;
1275 
1276  /* see contrib/loaders/flash/k1921vk01t.S for src */
1277  static const uint8_t niietcm4_flash_write_code[] = {
1278  0x14, 0x4f, 0x16, 0x68, 0x00, 0x2e, 0x23, 0xd0, 0x55, 0x68, 0xb5, 0x42, 0xf9, 0xd0, 0x2e, 0x68,
1279  0x7e, 0x60, 0x04, 0x35, 0x2e, 0x68, 0x3e, 0x65, 0x04, 0x35, 0x2e, 0x68, 0x7e, 0x65, 0x04, 0x35,
1280  0x2e, 0x68, 0xbe, 0x65, 0x04, 0x35, 0x3c, 0x60, 0x10, 0x34, 0xb8, 0x60, 0xfe, 0x68, 0x00, 0x2e,
1281  0xfc, 0xd0, 0x02, 0x2e, 0x0a, 0xd0, 0x01, 0x26, 0x7e, 0x61, 0x9d, 0x42, 0x01, 0xd3, 0x15, 0x46,
1282  0x08, 0x35, 0x55, 0x60, 0x01, 0x39, 0x00, 0x29, 0x02, 0xd0, 0xda, 0xe7, 0x00, 0x20, 0x50, 0x60,
1283  0x30, 0x46, 0x00, 0xbe, 0x00, 0xc0, 0x01, 0xa0
1284  };
1285 
1286  /* flash write code */
1287  if (target_alloc_working_area(target, sizeof(niietcm4_flash_write_code),
1288  &write_algorithm) != ERROR_OK) {
1289  LOG_WARNING("no working area available, can't do block memory writes");
1290  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1291  }
1292 
1293  retval = target_write_buffer(target, write_algorithm->address,
1294  sizeof(niietcm4_flash_write_code), niietcm4_flash_write_code);
1295  if (retval != ERROR_OK)
1296  return retval;
1297 
1298  /* memory buffer */
1299  while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
1300  buffer_size /= 2;
1301  buffer_size &= ~15UL; /* Make sure it's 16 byte aligned */
1302  buffer_size += 8; /* And 8 bytes for WP and RP */
1303  if (buffer_size <= 256) {
1304  /* we already allocated the writing code, but failed to get a
1305  * buffer, free the algorithm */
1306  target_free_working_area(target, write_algorithm);
1307 
1308  LOG_WARNING("no large enough working area available, can't do block memory writes");
1309  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1310  }
1311  }
1312 
1313  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* write_cmd base (in), status (out) */
1314  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (128bit) */
1315  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
1316  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
1317  init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
1318 
1319  uint32_t flash_cmd;
1320  if (niietcm4_info->bflash_info_remap)
1321  flash_cmd = FMC_MAGIC_KEY | FMC_WRITE_IFB;
1322  else
1323  flash_cmd = FMC_MAGIC_KEY | FMC_WRITE;
1324 
1325  buf_set_u32(reg_params[0].value, 0, 32, flash_cmd);
1326  buf_set_u32(reg_params[1].value, 0, 32, count);
1327  buf_set_u32(reg_params[2].value, 0, 32, source->address);
1328  buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1329  buf_set_u32(reg_params[4].value, 0, 32, address);
1330 
1331  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1332  armv7m_info.core_mode = ARM_MODE_THREAD;
1333 
1334  retval = target_run_flash_async_algorithm(target, buffer, count, 16,
1335  0, NULL,
1336  5, reg_params,
1337  source->address, source->size,
1338  write_algorithm->address, 0,
1339  &armv7m_info);
1340 
1341  if (retval == ERROR_FLASH_OPERATION_FAILED)
1342  LOG_ERROR("flash write failed at address 0x%"PRIx32,
1343  buf_get_u32(reg_params[4].value, 0, 32));
1344 
1345  target_free_working_area(target, source);
1346  target_free_working_area(target, write_algorithm);
1347 
1348  destroy_reg_param(&reg_params[0]);
1349  destroy_reg_param(&reg_params[1]);
1350  destroy_reg_param(&reg_params[2]);
1351  destroy_reg_param(&reg_params[3]);
1352  destroy_reg_param(&reg_params[4]);
1353 
1354  return retval;
1355 }
1356 
1357 static int niietcm4_write(struct flash_bank *bank, const uint8_t *buffer,
1358  uint32_t offset, uint32_t count)
1359 {
1360  struct target *target = bank->target;
1361  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1362  uint8_t *new_buffer = NULL;
1363 
1364  if (bank->target->state != TARGET_HALTED) {
1365  LOG_ERROR("Target not halted");
1366  return ERROR_TARGET_NOT_HALTED;
1367  }
1368 
1369  if (offset & 0xF) {
1370  LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-word alignment", offset);
1371  return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1372  }
1373 
1374  /* If there's an odd number of words, the data has to be padded. Duplicate
1375  * the buffer and use the normal code path with a single block write since
1376  * it's probably cheaper than to special case the last odd write using
1377  * discrete accesses. */
1378 
1379  int rem = count % 16;
1380  if (rem) {
1381  new_buffer = malloc(count + 16 - rem);
1382  if (!new_buffer) {
1383  LOG_ERROR("Odd number of words to write and no memory for padding buffer");
1384  return ERROR_FAIL;
1385  }
1386  LOG_INFO("Odd number of words to write, padding with 0xFFFFFFFF");
1387  buffer = memcpy(new_buffer, buffer, count);
1388  while (rem < 16) {
1389  new_buffer[count++] = 0xff;
1390  rem++;
1391  }
1392  }
1393 
1394  int retval;
1395 
1396  /* try using block write */
1397  retval = niietcm4_write_block(bank, buffer, offset, count/16);
1398  uint32_t flash_addr, flash_cmd, flash_data;
1399 
1400  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1401  /* if block write failed (no sufficient working area),
1402  * we use normal (slow) single halfword accesses */
1403  LOG_WARNING("Can't use block writes, falling back to single memory accesses");
1404  LOG_INFO("Please wait ..."); /* it`s quite a long process */
1405 
1406  /* chose between main bootflash and info bootflash */
1407  if (niietcm4_info->bflash_info_remap)
1408  flash_cmd = FMC_MAGIC_KEY | FMC_WRITE_IFB;
1409  else
1410  flash_cmd = FMC_MAGIC_KEY | FMC_WRITE;
1411 
1412  /* write 16 bytes per try */
1413  for (unsigned int i = 0; i < count; i += 16) {
1414  /* current addr */
1415  LOG_INFO("%u byte of %" PRIu32, i, count);
1416  flash_addr = offset + i;
1417  retval = target_write_u32(target, FMA, flash_addr);
1418  if (retval != ERROR_OK)
1419  goto free_buffer;
1420 
1421  /* Prepare data (4 words) */
1422  uint32_t value[4];
1423  memcpy(&value, buffer + i*16, 4*sizeof(uint32_t));
1424 
1425  /* place in reg 16 bytes of data */
1426  flash_data = value[0];
1427  retval = target_write_u32(target, FMD1, flash_data);
1428  if (retval != ERROR_OK)
1429  goto free_buffer;
1430  flash_data = value[1];
1431  retval = target_write_u32(target, FMD2, flash_data);
1432  if (retval != ERROR_OK)
1433  goto free_buffer;
1434  flash_data = value[2];
1435  retval = target_write_u32(target, FMD3, flash_data);
1436  if (retval != ERROR_OK)
1437  goto free_buffer;
1438  flash_data = value[3];
1439  retval = target_write_u32(target, FMD4, flash_data);
1440  if (retval != ERROR_OK)
1441  goto free_buffer;
1442 
1443  /* write start */
1444  retval = target_write_u32(target, FMC, flash_cmd);
1445  if (retval != ERROR_OK)
1446  goto free_buffer;
1447 
1448  /* status check */
1449  retval = niietcm4_opstatus_check(bank);
1450  if (retval != ERROR_OK)
1451  goto free_buffer;
1452  }
1453 
1454  }
1455 
1456 free_buffer:
1457  free(new_buffer);
1458  return retval;
1459 }
1460 
1461 static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
1462 {
1463  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1464  struct target *target = bank->target;
1465  int retval;
1466 
1467  niietcm4_info->chip_name = "K1921VK01T";
1468 
1469  /* check if we in service mode */
1470  uint32_t service_mode;
1471  retval = target_read_u32(target, 0x80017000, &service_mode);
1472  if (retval != ERROR_OK)
1473  return retval;
1474  service_mode = (service_mode>>2) & 0x1;
1475 
1476  if (!service_mode) {
1477  niietcm4_info->uflash_width = 8;
1478  niietcm4_info->uflash_size = 0x10000;
1479  niietcm4_info->uflash_pagetotal = 256;
1480  niietcm4_info->uflash_info_size = 0x200;
1481  niietcm4_info->uflash_info_pagetotal = 2;
1482 
1483  uint32_t uflash_data[2];
1484  uint32_t uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
1485  for (int i = 0; i < 2; i++) {
1486  retval = target_write_u32(target, UFMA, i);
1487  if (retval != ERROR_OK)
1488  return retval;
1489  retval = target_write_u32(target, UFMC, uflash_cmd);
1490  if (retval != ERROR_OK)
1491  return retval;
1492  /* status check */
1493  retval = niietcm4_uopstatus_check(bank);
1494  if (retval != ERROR_OK)
1495  return retval;
1496  retval = target_read_u32(target, UFMD, &uflash_data[i]);
1497  if (retval != ERROR_OK)
1498  return retval;
1499  }
1500 
1501  int boot_from_ifb = (uflash_data[0]>>INFOWORD0_BOOTFROM_IFB_POS) & 0x1;
1502  int en_gpio = (uflash_data[0]>>INFOWORD0_EN_GPIO_POS) & 0x1;
1503  int extmem_sel = (uflash_data[0]>>INFOWORD0_EXTMEM_SEL_POS) & 0x3;
1504  int pinnum = (uflash_data[1]>>INFOWORD1_PINNUM_POS) & 0xF;
1505  int portnum = (uflash_data[1]>>INFOWORD1_PORTNUM_POS) & 0x7;
1506 
1507  if (boot_from_ifb)
1508  niietcm4_info->bflash_info_remap = false;
1509  else
1510  niietcm4_info->bflash_info_remap = true;
1511  if (extmem_sel == 0x2)
1512  niietcm4_info->extmem_boot_altfunc = 3;
1513  else
1514  niietcm4_info->extmem_boot_altfunc = 1;
1515  if (portnum == 0x0)
1516  niietcm4_info->extmem_boot_port = "GPIOA";
1517  else if (portnum == 0x1)
1518  niietcm4_info->extmem_boot_port = "GPIOB";
1519  else if (portnum == 0x2)
1520  niietcm4_info->extmem_boot_port = "GPIOC";
1521  else if (portnum == 0x3)
1522  niietcm4_info->extmem_boot_port = "GPIOD";
1523  else if (portnum == 0x4)
1524  niietcm4_info->extmem_boot_port = "GPIOE";
1525  else if (portnum == 0x5)
1526  niietcm4_info->extmem_boot_port = "GPIOF";
1527  else if (portnum == 0x6)
1528  niietcm4_info->extmem_boot_port = "GPIOG";
1529  else if (portnum == 0x7)
1530  niietcm4_info->extmem_boot_port = "GPIOH";
1531  else
1532  niietcm4_info->extmem_boot_port = "not defined";
1533  if (en_gpio)
1534  niietcm4_info->extmem_boot = false;
1535  else
1536  niietcm4_info->extmem_boot = true;
1537  niietcm4_info->extmem_boot_pin = pinnum;
1538 
1539  /* check state of extmem boot en pin, if "high", extmem remapped to 0x00000000 */
1540  uint32_t extmem_boot_port_data;
1541  retval = target_read_u32(target, 0x80010000 + 0x1000*portnum, &extmem_boot_port_data);
1542  if (retval != ERROR_OK)
1543  return retval;
1544  int extmem_boot_pin_data = (extmem_boot_port_data>>pinnum) & 0x1;
1545 
1546  uint32_t extmem_base;
1547  uint32_t bflash_base;
1548  if (extmem_boot_pin_data && niietcm4_info->extmem_boot) {
1549  extmem_base = 0x00000000;
1550  bflash_base = 0x40000000;
1551  } else {
1552  extmem_base = 0x40000000;
1553  bflash_base = 0x00000000;
1554  }
1555 
1556  uint32_t bflash_size = 0x100000;
1557  uint32_t bflash_pages = 128;
1558  uint32_t bflash_info_size = 0x2000;
1559  uint32_t bflash_info_pages = 1;
1560  if (niietcm4_info->bflash_info_remap) {
1561  bflash_base += 0x2000;
1562  bflash_size -= 0x2000;
1563  bflash_pages--;
1564  bank->size = bflash_info_size;
1565  bank->num_sectors = bflash_info_pages;
1566  } else {
1567  bank->size = bflash_size;
1568  bank->num_sectors = bflash_pages;
1569  }
1570 
1571  char info_bootflash_addr_str[64];
1572  if (niietcm4_info->bflash_info_remap)
1573  snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
1574  TARGET_ADDR_FMT " base address", bank->base);
1575  else
1576  snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
1577  "not mapped to global address space");
1578 
1579  snprintf(niietcm4_info->chip_brief,
1580  sizeof(niietcm4_info->chip_brief),
1581  "\n"
1582  "MEMORY CONFIGURATION\n"
1583  "Bootflash :\n"
1584  " %" PRIu32 " kB total\n"
1585  " %" PRIu32 " pages %" PRIu32 " kB each\n"
1586  " 0x%08" PRIx32 " base address\n"
1587  "%s"
1588  "Info bootflash :\n"
1589  " %" PRIu32 " kB total\n"
1590  " %" PRIu32 " pages %" PRIu32 " kB each\n"
1591  " %s\n"
1592  "%s"
1593  "Userflash :\n"
1594  " %" PRIu32 " kB total\n"
1595  " %" PRIu32 " pages %" PRIu32 " B each\n"
1596  " %" PRIu32 " bit cells\n"
1597  " not mapped to global address space\n"
1598  "Info userflash :\n"
1599  " %" PRIu32 " B total\n"
1600  " %" PRIu32 " pages of %" PRIu32 " B each\n"
1601  " %" PRIu32 " bit cells\n"
1602  " not mapped to global address space\n"
1603  "RAM :\n"
1604  " 192 kB total\n"
1605  " 0x20000000 base address\n"
1606  "External memory :\n"
1607  " 8/16 bit address space\n"
1608  " 0x%08" PRIx32 " base address\n"
1609  "\n"
1610  "INFOWORD STATUS\n"
1611  "Bootflash info region remap :\n"
1612  " %s\n"
1613  "External memory boot port :\n"
1614  " %s\n"
1615  "External memory boot pin :\n"
1616  " %" PRIu32 "\n"
1617  "External memory interface alternative function :\n"
1618  " %" PRIu32 "\n"
1619  "Option boot from external memory :\n"
1620  " %s\n",
1621  bflash_size/1024,
1622  bflash_pages,
1623  (bflash_size/bflash_pages)/1024,
1624  bflash_base,
1625  niietcm4_info->bflash_info_remap ? "" : " this flash will be used for debugging, writing and etc\n",
1626  bflash_info_size/1024,
1627  bflash_info_pages,
1628  (bflash_info_size/bflash_info_pages)/1024,
1629  info_bootflash_addr_str,
1630  niietcm4_info->bflash_info_remap ? " this flash will be used for debugging, writing and etc\n" : "",
1631  niietcm4_info->uflash_size/1024,
1632  niietcm4_info->uflash_pagetotal,
1633  niietcm4_info->uflash_size/niietcm4_info->uflash_pagetotal,
1634  niietcm4_info->uflash_width,
1635  niietcm4_info->uflash_info_size,
1636  niietcm4_info->uflash_info_pagetotal,
1637  niietcm4_info->uflash_info_size/niietcm4_info->uflash_info_pagetotal,
1638  niietcm4_info->uflash_width,
1639  extmem_base,
1640  niietcm4_info->bflash_info_remap ? "enable" : "disable",
1641  niietcm4_info->extmem_boot_port,
1642  niietcm4_info->extmem_boot_pin,
1643  niietcm4_info->extmem_boot_altfunc,
1644  niietcm4_info->extmem_boot ? "enable" : "disable");
1645  } else {
1646  bank->size = 0x100000;
1647  bank->num_sectors = 128;
1648 
1649  sprintf(niietcm4_info->chip_brief,
1650  "\n"
1651  "H[2] was HIGH while startup. Device entered service mode.\n"
1652  "All flashes were locked.\n"
1653  "If you want to perform emergency erase (erase all flashes),\n"
1654  "please use \"service_mode_erase\" command and reset device.\n"
1655  "Do not forget to pull H[2] down while reset for returning to normal operation mode.\n"
1656  );
1657  }
1658 
1659  return retval;
1660 }
1661 
1662 static int niietcm4_probe(struct flash_bank *bank)
1663 {
1664  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1665  struct target *target = bank->target;
1666 
1667  free(bank->sectors);
1668  bank->sectors = NULL;
1669 
1670  uint32_t retval;
1671  uint32_t chipid;
1672 
1673  retval = target_read_u32(target, CHIPID_ADDR, &chipid);
1674  if (retval != ERROR_OK) {
1675  chipid = K1921VK01T_ID;
1676  LOG_INFO("unknown chipid, assuming K1921VK01T");
1677  }
1678 
1679  if (chipid == K1921VK01T_ID)
1680  niietcm4_probe_k1921vk01t(bank);
1681 
1682  int page_total = bank->num_sectors;
1683  int page_size = bank->size / page_total;
1684 
1685  bank->sectors = malloc(sizeof(struct flash_sector) * page_total);
1686 
1687  for (int i = 0; i < page_total; i++) {
1688  bank->sectors[i].offset = i * page_size;
1689  bank->sectors[i].size = page_size;
1690  bank->sectors[i].is_erased = -1;
1691  bank->sectors[i].is_protected = -1;
1692  }
1693 
1694  niietcm4_info->probed = true;
1695 
1696  return ERROR_OK;
1697 }
1698 
1699 static int niietcm4_auto_probe(struct flash_bank *bank)
1700 {
1701  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1702  if (niietcm4_info->probed)
1703  return ERROR_OK;
1704  return niietcm4_probe(bank);
1705 }
1706 
1707 static int get_niietcm4_info(struct flash_bank *bank, struct command_invocation *cmd)
1708 {
1709  struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
1710  command_print_sameline(cmd, "\nNIIET Cortex-M4F %s\n%s",
1711  niietcm4_info->chip_name, niietcm4_info->chip_brief);
1712  return ERROR_OK;
1713 }
1714 
1715 
1716 const struct flash_driver niietcm4_flash = {
1717  .name = "niietcm4",
1718  .usage = "flash bank <name> niietcm4 <base> <size> 0 0 <target#>",
1719  .commands = niietcm4_command_handlers,
1720  .flash_bank_command = niietcm4_flash_bank_command,
1721  .erase = niietcm4_erase,
1722  .protect = niietcm4_protect,
1723  .write = niietcm4_write,
1724  .read = default_flash_read,
1725  .probe = niietcm4_probe,
1726  .auto_probe = niietcm4_auto_probe,
1727  .erase_check = default_flash_blank_check,
1728  .protect_check = niietcm4_protect_check,
1729  .info = get_niietcm4_info,
1730  .free_driver_priv = default_flash_free_driver_priv,
1731 };
init_reg_param
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
destroy_reg_param
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
PARAM_OUT
@ PARAM_OUT
Definition: algorithm.h:16
PARAM_IN_OUT
@ PARAM_IN_OUT
Definition: algorithm.h:17
ARM_MODE_THREAD
@ ARM_MODE_THREAD
Definition: arm.h:94
ARMV7M_COMMON_MAGIC
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:229
binarybuffer.h
Support functions to access arbitrary bits in a byte array.
buf_get_u32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:378
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CALL_COMMAND_HANDLER
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:123
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
page_size
uint32_t page_size
Page size.
Definition: dw-spi-helper.h:3
buffer_size
uint32_t buffer_size
Size of dw_spi_program::buffer.
Definition: dw-spi-helper.h:5
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
ERROR_FLASH_DST_BREAKS_ALIGNMENT
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
Definition: flash/common.h:32
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:377
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
default_flash_free_driver_priv
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
Definition: flash/nor/core.c:210
busy_sleep
void busy_sleep(uint64_t ms)
Definition: log.c:491
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:144
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
ERROR_OK
#define ERROR_OK
Definition: log.h:182
UFMC_MAGIC_KEY
#define UFMC_MAGIC_KEY
Definition: niietcm4.c:80
FMC_WRITE_IFB
#define FMC_WRITE_IFB
Definition: niietcm4.c:48
UFMC_PAGE_ERASE
#define UFMC_PAGE_ERASE
Definition: niietcm4.c:74
UF_LOCK_ADDR
#define UF_LOCK_ADDR
Definition: niietcm4.c:109
niietcm4_mass_erase
static int niietcm4_mass_erase(struct flash_bank *bank)
Definition: niietcm4.c:1135
INFOWORD2_LOCK_IFB_BF
#define INFOWORD2_LOCK_IFB_BF
Definition: niietcm4.c:103
niietcm4_command_handlers
static const struct command_registration niietcm4_command_handlers[]
Definition: niietcm4.c:1022
INFOWORD1_PINNUM_POS
#define INFOWORD1_PINNUM_POS
Definition: niietcm4.c:99
CHIPID_ADDR
#define CHIPID_ADDR
Definition: niietcm4.c:18
niietcm4_uflash_page_erase
static int niietcm4_uflash_page_erase(struct flash_bank *bank, int page_num, int mem_type)
Erase one page of userflash info or main region.
Definition: niietcm4.c:291
INFOWORD3_ADDR
#define INFOWORD3_ADDR
Definition: niietcm4.c:105
FCIC_CLR_OPERROR
#define FCIC_CLR_OPERROR
Definition: niietcm4.c:58
INFOWORD0_BOOTFROM_IFB_POS
#define INFOWORD0_BOOTFROM_IFB_POS
Definition: niietcm4.c:94
UFCIS
#define UFCIS
Definition: niietcm4.c:68
FMC_MAGIC_KEY
#define FMC_MAGIC_KEY
Definition: niietcm4.c:50
USERFLASH_PAGE_TOTALNUM
#define USERFLASH_PAGE_TOTALNUM
Definition: niietcm4.c:62
get_niietcm4_info
static int get_niietcm4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: niietcm4.c:1707
UFMC_PAGEERASE_IFB
#define UFMC_PAGEERASE_IFB
Definition: niietcm4.c:78
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(niietcm4_flash_bank_command)
Definition: niietcm4.c:1038
niietcm4_flash
const struct flash_driver niietcm4_flash
Definition: niietcm4.c:1716
INFOWORD1_PORTNUM_POS
#define INFOWORD1_PORTNUM_POS
Definition: niietcm4.c:100
niietcm4_write
static int niietcm4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: niietcm4.c:1357
INFOWORD2_ADDR
#define INFOWORD2_ADDR
Definition: niietcm4.c:102
niietcm4_probe
static int niietcm4_probe(struct flash_bank *bank)
Definition: niietcm4.c:1662
FMD1
#define FMD1
Definition: niietcm4.c:34
FMD2
#define FMD2
Definition: niietcm4.c:39
UFMC_FULL_ERASE
#define UFMC_FULL_ERASE
Definition: niietcm4.c:75
niietcm4_uflash_protect
static int niietcm4_uflash_protect(struct flash_bank *bank, int mem_type, int set, unsigned int first, unsigned int last)
Enable or disable protection of userflash pages.
Definition: niietcm4.c:322
niietcm4_dump_uflash_page
static int niietcm4_dump_uflash_page(struct flash_bank *bank, uint32_t *dump, int page_num, int mem_type)
Dump page of userflash region.
Definition: niietcm4.c:219
niietcm4_protect
static int niietcm4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: niietcm4.c:1201
SERVICE_MODE_ERASE_ADDR
#define SERVICE_MODE_ERASE_ADDR
Definition: niietcm4.c:28
UFCIC_CLR_OPCMLT
#define UFCIC_CLR_OPCMLT
Definition: niietcm4.c:87
BF_LOCK_ADDR
#define BF_LOCK_ADDR
Definition: niietcm4.c:108
COMMAND_HANDLER
COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command)
Definition: niietcm4.c:377
niietcm4_opstatus_check
static int niietcm4_opstatus_check(struct flash_bank *bank)
Wait while operation with bootflash being performed and check result status.
Definition: niietcm4.c:142
FCIC_CLR_OPCMLT
#define FCIC_CLR_OPCMLT
Definition: niietcm4.c:57
UFMC_WRITE
#define UFMC_WRITE
Definition: niietcm4.c:73
INFOWORD0_BOOTFROM_IFB
#define INFOWORD0_BOOTFROM_IFB
Definition: niietcm4.c:92
INFOWORD0_EN_GPIO_POS
#define INFOWORD0_EN_GPIO_POS
Definition: niietcm4.c:95
FMC_WRITE
#define FMC_WRITE
Definition: niietcm4.c:45
FMC
#define FMC
Definition: niietcm4.c:35
INFOWORD0_EXTMEM_SEL_POS
#define INFOWORD0_EXTMEM_SEL_POS
Definition: niietcm4.c:96
niietcm4_protect_check
static int niietcm4_protect_check(struct flash_bank *bank)
Definition: niietcm4.c:1067
niietcm4_write_block
static int niietcm4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: niietcm4.c:1263
FMC_PAGEERASE_IFB
#define FMC_PAGEERASE_IFB
Definition: niietcm4.c:49
UFMC_WRITE_IFB
#define UFMC_WRITE_IFB
Definition: niietcm4.c:77
FMD4
#define FMD4
Definition: niietcm4.c:41
UFCIS_OP_ERROR
#define UFCIS_OP_ERROR
Definition: niietcm4.c:84
UFMC_READ_IFB
#define UFMC_READ_IFB
Definition: niietcm4.c:79
FLASH_DRIVER_VER
#define FLASH_DRIVER_VER
Definition: niietcm4.c:17
FCIC
#define FCIC
Definition: niietcm4.c:38
niietcm4_auto_probe
static int niietcm4_auto_probe(struct flash_bank *bank)
Definition: niietcm4.c:1699
INFOWORD0_ADDR
#define INFOWORD0_ADDR
Definition: niietcm4.c:91
FMC_PAGE_ERASE
#define FMC_PAGE_ERASE
Definition: niietcm4.c:46
UFMD
#define UFMD
Definition: niietcm4.c:66
FCIS_OP_ERROR
#define FCIS_OP_ERROR
Definition: niietcm4.c:54
niietcm4_probe_k1921vk01t
static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
Definition: niietcm4.c:1461
UFMC_READ
#define UFMC_READ
Definition: niietcm4.c:76
FMA
#define FMA
Definition: niietcm4.c:33
USERFLASH_PAGE_SIZE
#define USERFLASH_PAGE_SIZE
Definition: niietcm4.c:61
FMC_FULL_ERASE
#define FMC_FULL_ERASE
Definition: niietcm4.c:47
niietcm4_erase
static int niietcm4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: niietcm4.c:1156
K1921VK01T_ID
#define K1921VK01T_ID
Definition: niietcm4.c:19
UFMC
#define UFMC
Definition: niietcm4.c:67
FMD3
#define FMD3
Definition: niietcm4.c:40
UFMA
#define UFMA
Definition: niietcm4.c:65
niietcm4_exec_command_handlers
static const struct command_registration niietcm4_exec_command_handlers[]
Definition: niietcm4.c:941
niietcm4_load_uflash_page
static int niietcm4_load_uflash_page(struct flash_bank *bank, uint32_t *dump, int page_num, int mem_type)
Load modified page dump to userflash region page.
Definition: niietcm4.c:255
INFOWORD0_EN_GPIO
#define INFOWORD0_EN_GPIO
Definition: niietcm4.c:93
FCIS
#define FCIS
Definition: niietcm4.c:36
INFOWORD1_ADDR
#define INFOWORD1_ADDR
Definition: niietcm4.c:98
UFCIC
#define UFCIC
Definition: niietcm4.c:70
INFOWORD3_LOCK_IFB_UF
#define INFOWORD3_LOCK_IFB_UF
Definition: niietcm4.c:106
UFCIC_CLR_OPERROR
#define UFCIC_CLR_OPERROR
Definition: niietcm4.c:88
INFO_MEM_TYPE
#define INFO_MEM_TYPE
Definition: niietcm4.c:27
niietcm4_uopstatus_check
static int niietcm4_uopstatus_check(struct flash_bank *bank)
Wait while operation with userflash being performed and check result status.
Definition: niietcm4.c:179
source
struct rtt_source source
Definition: rtt/rtt.c:23
mem_type
mem_type
Definition: stm8.c:137
armv7m_algorithm
Definition: armv7m.h:305
armv7m_algorithm::common_magic
unsigned int common_magic
Definition: armv7m.h:306
armv7m_algorithm::core_mode
enum arm_mode core_mode
Definition: armv7m.h:308
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
flash_sector
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
niietcm4_flash_bank
Private data for flash driver.
Definition: niietcm4.c:114
niietcm4_flash_bank::extmem_boot
bool extmem_boot
Definition: niietcm4.c:131
niietcm4_flash_bank::uflash_width
uint32_t uflash_width
Definition: niietcm4.c:121
niietcm4_flash_bank::extmem_boot_altfunc
uint32_t extmem_boot_altfunc
Definition: niietcm4.c:130
niietcm4_flash_bank::uflash_info_pagetotal
uint32_t uflash_info_pagetotal
Definition: niietcm4.c:125
niietcm4_flash_bank::chip_brief
char chip_brief[4096]
Definition: niietcm4.c:119
niietcm4_flash_bank::uflash_size
uint32_t uflash_size
Definition: niietcm4.c:122
niietcm4_flash_bank::extmem_boot_pin
uint32_t extmem_boot_pin
Definition: niietcm4.c:129
niietcm4_flash_bank::bflash_info_remap
bool bflash_info_remap
Definition: niietcm4.c:127
niietcm4_flash_bank::probed
bool probed
Definition: niietcm4.c:116
niietcm4_flash_bank::chipid
uint32_t chipid
Definition: niietcm4.c:117
niietcm4_flash_bank::uflash_info_size
uint32_t uflash_info_size
Definition: niietcm4.c:124
niietcm4_flash_bank::chip_name
char * chip_name
Definition: niietcm4.c:118
niietcm4_flash_bank::uflash_pagetotal
uint32_t uflash_pagetotal
Definition: niietcm4.c:123
niietcm4_flash_bank::extmem_boot_port
char * extmem_boot_port
Definition: niietcm4.c:128
reg_param
Definition: algorithm.h:27
target
Definition: target.h:119
target::state
enum target_state state
Definition: target.h:167
timeout
Definition: psoc6.c:83
working_area
Definition: target.h:88
working_area::address
target_addr_t address
Definition: target.h:89
target_write_buffer
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2369
target_alloc_working_area
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2090
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2635
target_free_working_area
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2148
target_alloc_working_area_try
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:1996
target_run_flash_async_algorithm
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:945
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2561
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:821
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:286
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22