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Data Structures
struct	l2c_init_data

struct	l2x0_regs

struct	outer_cache_fns

Macros
#define	L2X0_ADDR_FILTER_EN 1

#define	L2X0_ADDR_FILTER_END 0xC04

#define	L2X0_ADDR_FILTER_START 0xC00

#define	L2X0_AUX_CTRL 0x104

#define	L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16

#define	L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28

#define	L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7

#define	L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0

#define	L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)

#define	L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3

#define	L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)

#define	L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9

#define	L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30

#define	L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29

#define	L2X0_AUX_CTRL_MASK 0xc0000fff

#define	L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27

#define	L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26

#define	L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22

#define	L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)

#define	L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6

#define	L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)

#define	L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17

#define	L2X0_CACHE_ID 0x000

#define	L2X0_CACHE_ID_PART_L210 (1 << 6)

#define	L2X0_CACHE_ID_PART_L310 (3 << 6)

#define	L2X0_CACHE_ID_PART_MASK (0xf << 6)

#define	L2X0_CACHE_ID_RTL_MASK 0x3f

#define	L2X0_CACHE_ID_RTL_R0P0 0x0

#define	L2X0_CACHE_ID_RTL_R1P0 0x2

#define	L2X0_CACHE_ID_RTL_R2P0 0x4

#define	L2X0_CACHE_ID_RTL_R3P0 0x5

#define	L2X0_CACHE_ID_RTL_R3P1 0x6

#define	L2X0_CACHE_ID_RTL_R3P2 0x8

#define	L2X0_CACHE_LINE_SIZE 32

#define	L2X0_CACHE_SYNC 0x730

#define	L2X0_CACHE_TYPE 0x004

#define	L2X0_CLEAN_INV_LINE_IDX 0x7F8

#define	L2X0_CLEAN_INV_LINE_PA 0x7F0

#define	L2X0_CLEAN_INV_WAY 0x7FC

#define	L2X0_CLEAN_LINE_IDX 0x7B8

#define	L2X0_CLEAN_LINE_PA 0x7B0

#define	L2X0_CLEAN_WAY 0x7BC

#define	L2X0_CTRL 0x100

#define	L2X0_CTRL_EN 1

#define	L2X0_DATA_LATENCY_CTRL 0x10C

#define	L2X0_DEBUG_CTRL 0xF40

#define	L2X0_DUMMY_REG 0x740

#define	L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)

#define	L2X0_EVENT_CNT0_CFG 0x208

#define	L2X0_EVENT_CNT0_VAL 0x210

#define	L2X0_EVENT_CNT1_CFG 0x204

#define	L2X0_EVENT_CNT1_VAL 0x20C

#define	L2X0_EVENT_CNT_CTRL 0x200

#define	L2X0_INTR_CLEAR 0x220

#define	L2X0_INTR_MASK 0x214

#define	L2X0_INV_LINE_PA 0x770

#define	L2X0_INV_WAY 0x77C

#define	L2X0_LATENCY_CTRL_RD_SHIFT 4

#define	L2X0_LATENCY_CTRL_SETUP_SHIFT 0

#define	L2X0_LATENCY_CTRL_WR_SHIFT 8

#define	L2X0_LINE_DATA 0xF10

#define	L2X0_LINE_TAG 0xF30

#define	L2X0_LOCKDOWN_STRIDE 0x08

#define	L2X0_LOCKDOWN_WAY_D_BASE 0x900

#define	L2X0_LOCKDOWN_WAY_I_BASE 0x904

#define	L2X0_MASKED_INTR_STAT 0x218

#define	L2X0_POWER_CTRL 0xF80

#define	L2X0_PREFETCH_CTRL 0xF60

#define	L2X0_RAW_INTR_STAT 0x21C

#define	L2X0_STNDBY_MODE_EN (1 << 0)

#define	L2X0_TAG_LATENCY_CTRL 0x108

#define	L2X0_TEST_OPERATION 0xF00

#define	L2X0_WAY_SIZE_SHIFT 3

Functions
int	arm7a_l2x_flush_all_data (struct target *target)

int	armv7a_l2x_cache_flush_virt (struct target *target, target_addr_t virt, uint32_t size)

Variables
const struct command_registration	arm7a_l2x_cache_command_handler []

Macro Definition Documentation

◆ L2X0_ADDR_FILTER_EN

#define L2X0_ADDR_FILTER_EN 1

Definition at line 92 of file armv7a_cache_l2x.h.

◆ L2X0_ADDR_FILTER_END

#define L2X0_ADDR_FILTER_END 0xC04

Definition at line 47 of file armv7a_cache_l2x.h.

◆ L2X0_ADDR_FILTER_START

#define L2X0_ADDR_FILTER_START 0xC00

Definition at line 46 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL

#define L2X0_AUX_CTRL 0x104

Definition at line 17 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT

#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16

Definition at line 78 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT

#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28

Definition at line 84 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7

Definition at line 71 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0

Definition at line 70 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)

Definition at line 73 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3

Definition at line 72 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DIRTY_LATENCY_MASK

#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)

Definition at line 77 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT

#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9

Definition at line 76 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_EARLY_BRESP_SHIFT

#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30

Definition at line 86 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT

#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29

Definition at line 85 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_MASK

#define L2X0_AUX_CTRL_MASK 0xc0000fff

Definition at line 69 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT

#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27

Definition at line 83 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT

#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26

Definition at line 82 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT

#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22

Definition at line 81 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_TAG_LATENCY_MASK

#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)

Definition at line 75 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_TAG_LATENCY_SHIFT

#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6

Definition at line 74 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_WAY_SIZE_MASK

#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)

Definition at line 80 of file armv7a_cache_l2x.h.

◆ L2X0_AUX_CTRL_WAY_SIZE_SHIFT

#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17

Definition at line 79 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID

#define L2X0_CACHE_ID 0x000

Definition at line 14 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_PART_L210

#define L2X0_CACHE_ID_PART_L210 (1 << 6)

Definition at line 59 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_PART_L310

#define L2X0_CACHE_ID_PART_L310 (3 << 6)

Definition at line 60 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_PART_MASK

#define L2X0_CACHE_ID_PART_MASK (0xf << 6)

Definition at line 58 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_MASK

#define L2X0_CACHE_ID_RTL_MASK 0x3f

Definition at line 61 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R0P0

#define L2X0_CACHE_ID_RTL_R0P0 0x0

Definition at line 62 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R1P0

#define L2X0_CACHE_ID_RTL_R1P0 0x2

Definition at line 63 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R2P0

#define L2X0_CACHE_ID_RTL_R2P0 0x4

Definition at line 64 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R3P0

#define L2X0_CACHE_ID_RTL_R3P0 0x5

Definition at line 65 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R3P1

#define L2X0_CACHE_ID_RTL_R3P1 0x6

Definition at line 66 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_ID_RTL_R3P2

#define L2X0_CACHE_ID_RTL_R3P2 0x8

Definition at line 67 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_LINE_SIZE

#define L2X0_CACHE_LINE_SIZE 32

Definition at line 11 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_SYNC

#define L2X0_CACHE_SYNC 0x730

Definition at line 29 of file armv7a_cache_l2x.h.

◆ L2X0_CACHE_TYPE

#define L2X0_CACHE_TYPE 0x004

Definition at line 15 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_INV_LINE_IDX

#define L2X0_CLEAN_INV_LINE_IDX 0x7F8

Definition at line 37 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_INV_LINE_PA

#define L2X0_CLEAN_INV_LINE_PA 0x7F0

Definition at line 36 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_INV_WAY

#define L2X0_CLEAN_INV_WAY 0x7FC

Definition at line 38 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_LINE_IDX

#define L2X0_CLEAN_LINE_IDX 0x7B8

Definition at line 34 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_LINE_PA

#define L2X0_CLEAN_LINE_PA 0x7B0

Definition at line 33 of file armv7a_cache_l2x.h.

◆ L2X0_CLEAN_WAY

#define L2X0_CLEAN_WAY 0x7BC

Definition at line 35 of file armv7a_cache_l2x.h.

◆ L2X0_CTRL

#define L2X0_CTRL 0x100

Definition at line 16 of file armv7a_cache_l2x.h.

◆ L2X0_CTRL_EN

#define L2X0_CTRL_EN 1

Definition at line 94 of file armv7a_cache_l2x.h.

◆ L2X0_DATA_LATENCY_CTRL

#define L2X0_DATA_LATENCY_CTRL 0x10C

Definition at line 19 of file armv7a_cache_l2x.h.

◆ L2X0_DEBUG_CTRL

#define L2X0_DEBUG_CTRL 0xF40

Definition at line 51 of file armv7a_cache_l2x.h.

◆ L2X0_DUMMY_REG

#define L2X0_DUMMY_REG 0x740

Definition at line 30 of file armv7a_cache_l2x.h.

◆ L2X0_DYNAMIC_CLK_GATING_EN

#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)

Definition at line 54 of file armv7a_cache_l2x.h.

◆ L2X0_EVENT_CNT0_CFG

#define L2X0_EVENT_CNT0_CFG 0x208

Definition at line 22 of file armv7a_cache_l2x.h.

◆ L2X0_EVENT_CNT0_VAL

#define L2X0_EVENT_CNT0_VAL 0x210

Definition at line 24 of file armv7a_cache_l2x.h.

◆ L2X0_EVENT_CNT1_CFG

#define L2X0_EVENT_CNT1_CFG 0x204

Definition at line 21 of file armv7a_cache_l2x.h.

◆ L2X0_EVENT_CNT1_VAL

#define L2X0_EVENT_CNT1_VAL 0x20C

Definition at line 23 of file armv7a_cache_l2x.h.

◆ L2X0_EVENT_CNT_CTRL

#define L2X0_EVENT_CNT_CTRL 0x200

Definition at line 20 of file armv7a_cache_l2x.h.

◆ L2X0_INTR_CLEAR

#define L2X0_INTR_CLEAR 0x220

Definition at line 28 of file armv7a_cache_l2x.h.

◆ L2X0_INTR_MASK

#define L2X0_INTR_MASK 0x214

Definition at line 25 of file armv7a_cache_l2x.h.

◆ L2X0_INV_LINE_PA

#define L2X0_INV_LINE_PA 0x770

Definition at line 31 of file armv7a_cache_l2x.h.

◆ L2X0_INV_WAY

#define L2X0_INV_WAY 0x77C

Definition at line 32 of file armv7a_cache_l2x.h.

◆ L2X0_LATENCY_CTRL_RD_SHIFT

#define L2X0_LATENCY_CTRL_RD_SHIFT 4

Definition at line 89 of file armv7a_cache_l2x.h.

◆ L2X0_LATENCY_CTRL_SETUP_SHIFT

#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0

Definition at line 88 of file armv7a_cache_l2x.h.

◆ L2X0_LATENCY_CTRL_WR_SHIFT

#define L2X0_LATENCY_CTRL_WR_SHIFT 8

Definition at line 90 of file armv7a_cache_l2x.h.

◆ L2X0_LINE_DATA

#define L2X0_LINE_DATA 0xF10

Definition at line 49 of file armv7a_cache_l2x.h.

◆ L2X0_LINE_TAG

#define L2X0_LINE_TAG 0xF30

Definition at line 50 of file armv7a_cache_l2x.h.

◆ L2X0_LOCKDOWN_STRIDE

#define L2X0_LOCKDOWN_STRIDE 0x08

Definition at line 45 of file armv7a_cache_l2x.h.

◆ L2X0_LOCKDOWN_WAY_D_BASE

#define L2X0_LOCKDOWN_WAY_D_BASE 0x900

Definition at line 43 of file armv7a_cache_l2x.h.

◆ L2X0_LOCKDOWN_WAY_I_BASE

#define L2X0_LOCKDOWN_WAY_I_BASE 0x904

Definition at line 44 of file armv7a_cache_l2x.h.

◆ L2X0_MASKED_INTR_STAT

#define L2X0_MASKED_INTR_STAT 0x218

Definition at line 26 of file armv7a_cache_l2x.h.

◆ L2X0_POWER_CTRL

#define L2X0_POWER_CTRL 0xF80

Definition at line 53 of file armv7a_cache_l2x.h.

◆ L2X0_PREFETCH_CTRL

#define L2X0_PREFETCH_CTRL 0xF60

Definition at line 52 of file armv7a_cache_l2x.h.

◆ L2X0_RAW_INTR_STAT

#define L2X0_RAW_INTR_STAT 0x21C

Definition at line 27 of file armv7a_cache_l2x.h.

◆ L2X0_STNDBY_MODE_EN

#define L2X0_STNDBY_MODE_EN (1 << 0)

Definition at line 55 of file armv7a_cache_l2x.h.

◆ L2X0_TAG_LATENCY_CTRL

#define L2X0_TAG_LATENCY_CTRL 0x108

Definition at line 18 of file armv7a_cache_l2x.h.

◆ L2X0_TEST_OPERATION

#define L2X0_TEST_OPERATION 0xF00

Definition at line 48 of file armv7a_cache_l2x.h.

◆ L2X0_WAY_SIZE_SHIFT

#define L2X0_WAY_SIZE_SHIFT 3

Definition at line 96 of file armv7a_cache_l2x.h.

Function Documentation

◆ arm7a_l2x_flush_all_data()

int arm7a_l2x_flush_all_data ( struct target * target )

Definition at line 42 of file armv7a_cache_l2x.c.

References arm7a_l2x_sanity_check(), armv7a_mmu_common::armv7a_cache, armv7a_common::armv7a_mmu, armv7a_l2x_cache::base, L2X0_CLEAN_INV_WAY, armv7a_cache_common::outer_cache, target_to_armv7a(), target_write_phys_u32(), and armv7a_l2x_cache::way.

Referenced by armv7a_cache_flush_all_data(), and COMMAND_HANDLER().

◆ armv7a_l2x_cache_flush_virt()

int armv7a_l2x_cache_flush_virt	(	struct target *	target,
		target_addr_t	virt,
		uint32_t	size
	)

Definition at line 61 of file armv7a_cache_l2x.c.

References arm7a_l2x_sanity_check(), armv7a_mmu_common::armv7a_cache, armv7a_common::armv7a_mmu, armv7a_l2x_cache::base, ERROR_OK, L2X0_CLEAN_INV_LINE_PA, LOG_ERROR, armv7a_cache_common::outer_cache, size, target_to_armv7a(), target_write_phys_u32(), target::type, and target_type::virt2phys.

Referenced by armv7a_cache_flush_virt(), and COMMAND_HANDLER().

Variable Documentation

◆ arm7a_l2x_cache_command_handler

const struct command_registration arm7a_l2x_cache_command_handler[]

extern

Definition at line 295 of file armv7a_cache_l2x.c.

Data Structures

Macros

Functions

Variables