17 #define MAX_XMC_SECTORS 12
20 #define SCU_REG_BASE 0x50004000
22 #define SCU_ID_CHIP 0x04
25 #define PFLASH_BASE 0x0C000000
28 #define UCB0_BASE 0x00000000
29 #define UCB1_BASE 0x00000400
30 #define UCB2_BASE 0x00000800
33 #define FLASH_REG_BASE 0x58000000
36 #define FLASH_REG_PMU_ID (FLASH_REG_BASE | 0x0508)
39 #define PMU_MOD_REV_MASK 0xFF
40 #define PMU_MOD_TYPE_MASK 0xFF00
41 #define PMU_MOD_NO_MASK 0xFFFF0000
44 #define FLASH_REG_PREF_PCON (FLASH_REG_BASE | 0x4000)
47 #define PCON_IBYP (1 << 0)
48 #define PCON_IINV (1 << 1)
51 #define FLASH_REG_FLASH0_ID (FLASH_REG_BASE | 0x2008)
54 #define FLASH_REG_FLASH0_FSR (FLASH_REG_BASE | 0x2010)
57 #define FSR_FABUSY (1)
60 #define FSR_PFPAGE (6)
61 #define FSR_PFOPER (8)
63 #define FSR_PROER (11)
64 #define FSR_PFSBER (12)
65 #define FSR_PFDBER (14)
66 #define FSR_PROIN (16)
67 #define FSR_RPROIN (18)
68 #define FSR_RPRODIS (19)
69 #define FSR_WPROIN0 (21)
70 #define FSR_WPROIN1 (22)
71 #define FSR_WPROIN2 (23)
72 #define FSR_WPRODIS0 (25)
73 #define FSR_WPRODIS1 (26)
77 #define FSR_PBUSY_MASK (0x01 << FSR_PBUSY)
78 #define FSR_FABUSY_MASK (0x01 << FSR_FABUSY)
79 #define FSR_PROG_MASK (0x01 << FSR_PROG)
80 #define FSR_ERASE_MASK (0x01 << FSR_ERASE)
81 #define FSR_PFPAGE_MASK (0x01 << FSR_PFPAGE)
82 #define FSR_PFOPER_MASK (0x01 << FSR_PFOPER)
83 #define FSR_SQER_MASK (0x01 << FSR_SQER)
84 #define FSR_PROER_MASK (0x01 << FSR_PROER)
85 #define FSR_PFSBER_MASK (0x01 << FSR_PFSBER)
86 #define FSR_PFDBER_MASK (0x01 << FSR_PFDBER)
87 #define FSR_PROIN_MASK (0x01 << FSR_PROIN)
88 #define FSR_RPROIN_MASK (0x01 << FSR_RPROIN)
89 #define FSR_RPRODIS_MASK (0x01 << FSR_RPRODIS)
90 #define FSR_WPROIN0_MASK (0x01 << FSR_WPROIN0)
91 #define FSR_WPROIN1_MASK (0x01 << FSR_WPROIN1)
92 #define FSR_WPROIN2_MASK (0x01 << FSR_WPROIN2)
93 #define FSR_WPRODIS0_MASK (0x01 << FSR_WPRODIS0)
94 #define FSR_WPRODIS1_MASK (0x01 << FSR_WPRODIS1)
95 #define FSR_SLM_MASK (0x01 << FSR_SLM)
96 #define FSR_VER_MASK (0x01 << FSR_VER)
99 #define FLASH_REG_FLASH0_FCON (FLASH_REG_BASE | 0x2014)
101 #define FCON_WSPFLASH (0)
102 #define FCON_WSECPF (4)
103 #define FCON_IDLE (13)
104 #define FCON_ESLDIS (14)
105 #define FCON_SLEEP (15)
106 #define FCON_RPA (16)
107 #define FCON_DCF (17)
108 #define FCON_DDF (18)
109 #define FCON_VOPERM (24)
110 #define FCON_SQERM (25)
111 #define FCON_PROERM (26)
112 #define FCON_PFSBERM (27)
113 #define FCON_PFDBERM (29)
114 #define FCON_EOBM (31)
116 #define FCON_WSPFLASH_MASK (0x0f << FCON_WSPFLASH)
117 #define FCON_WSECPF_MASK (0x01 << FCON_WSECPF)
118 #define FCON_IDLE_MASK (0x01 << FCON_IDLE)
119 #define FCON_ESLDIS_MASK (0x01 << FCON_ESLDIS)
120 #define FCON_SLEEP_MASK (0x01 << FCON_SLEEP)
121 #define FCON_RPA_MASK (0x01 << FCON_RPA)
122 #define FCON_DCF_MASK (0x01 << FCON_DCF)
123 #define FCON_DDF_MASK (0x01 << FCON_DDF)
124 #define FCON_VOPERM_MASK (0x01 << FCON_VOPERM)
125 #define FCON_SQERM_MASK (0x01 << FCON_SQERM)
126 #define FCON_PROERM_MASK (0x01 << FCON_PROERM)
127 #define FCON_PFSBERM_MASK (0x01 << FCON_PFSBERM)
128 #define FCON_PFDBERM_MASK (0x01 << FCON_PFDBERM)
129 #define FCON_EOBM_MASK (0x01 << FCON_EOBM)
132 #define FLASH_REG_FLASH0_MARP (FLASH_REG_BASE | 0x2018)
134 #define MARP_MARGIN (0)
135 #define MARP_TRAPDIS (15)
137 #define MARP_MARGIN_MASK (0x0f << MARP_MARGIN)
138 #define MARP_TRAPDIS_MASK (0x01 << MARP_TRAPDIS)
141 #define FLASH_REG_FLASH0_PROCON0 (FLASH_REG_BASE | 0x2020)
142 #define FLASH_REG_FLASH0_PROCON1 (FLASH_REG_BASE | 0x2024)
143 #define FLASH_REG_FLASH0_PROCON2 (FLASH_REG_BASE | 0x2028)
145 #define PROCON_S0L (0)
146 #define PROCON_S1L (1)
147 #define PROCON_S2L (2)
148 #define PROCON_S3L (3)
149 #define PROCON_S4L (4)
150 #define PROCON_S5L (5)
151 #define PROCON_S6L (6)
152 #define PROCON_S7L (7)
153 #define PROCON_S8L (8)
154 #define PROCON_S9L (9)
155 #define PROCON_S10_S11L (10)
156 #define PROCON_RPRO (15)
158 #define PROCON_S0L_MASK (0x01 << PROCON_S0L)
159 #define PROCON_S1L_MASK (0x01 << PROCON_S1L)
160 #define PROCON_S2L_MASK (0x01 << PROCON_S2L)
161 #define PROCON_S3L_MASK (0x01 << PROCON_S3L)
162 #define PROCON_S4L_MASK (0x01 << PROCON_S4L)
163 #define PROCON_S5L_MASK (0x01 << PROCON_S5L)
164 #define PROCON_S6L_MASK (0x01 << PROCON_S6L)
165 #define PROCON_S7L_MASK (0x01 << PROCON_S7L)
166 #define PROCON_S8L_MASK (0x01 << PROCON_S8L)
167 #define PROCON_S9L_MASK (0x01 << PROCON_S9L)
168 #define PROCON_S10_S11L_MASK (0x01 << PROCON_S10_S11L)
169 #define PROCON_RPRO_MASK (0x01 << PROCON_RPRO)
171 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
174 #define FLASH_ID_XMC4500 0xA2
175 #define FLASH_ID_XMC4300_XMC4700_4800 0x92
176 #define FLASH_ID_XMC4100_4200 0x9C
177 #define FLASH_ID_XMC4400 0x9F
180 #define FLASH_OP_TIMEOUT 5000
185 #define FLASH_CMD_ERASE_1 0x0C005554
186 #define FLASH_CMD_ERASE_2 0x0C00AAA8
187 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
188 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
189 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
192 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
194 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
196 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
197 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
199 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
200 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
201 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
204 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
205 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
206 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
207 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
208 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
209 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
235 16, 16, 16, 16, 16, 16, 16, 128
239 16, 16, 16, 16, 16, 16, 16, 128, 256
243 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
247 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
256 for (
int i = 0; i < seq_len; i++) {
268 const unsigned int *capacity =
NULL;
274 switch (
bank->num_sectors) {
288 LOG_ERROR(
"Unexpected number of sectors, %u\n",
296 uint32_t total_offset = 0;
297 bank->sectors = calloc(
bank->num_sectors,
299 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
300 bank->sectors[i].size = capacity[i] * 1024;
301 bank->sectors[i].offset = total_offset;
302 bank->sectors[i].is_erased = -1;
303 bank->sectors[i].is_protected = -1;
305 bank->size +=
bank->sectors[i].size;
307 total_offset +=
bank->sectors[i].size;
312 bank->default_padded_value =
bank->erased_value = 0x00;
331 LOG_WARNING(
"Cannot communicate... target not halted.");
338 LOG_ERROR(
"Cannot read device identification register.");
343 if ((devid & 0xF0000) != 0x40000 && devid != 0) {
344 LOG_ERROR(
"Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
348 LOG_DEBUG(
"Found XMC4xxx with devid: 0x%08" PRIx32, devid);
354 LOG_ERROR(
"Cannot read Flash bank configuration.");
357 flash_id = (
config & 0xff0000) >> 16;
364 bank->num_sectors = 8;
365 LOG_DEBUG(
"XMC4xxx: XMC4100/4200 detected.");
368 bank->num_sectors = 9;
372 bank->num_sectors = 12;
376 bank->num_sectors = 16;
377 LOG_DEBUG(
"XMC4xxx: XMC4700/4800 detected.");
380 LOG_ERROR(
"XMC4xxx: Unexpected flash ID. got %02" PRIx8,
392 LOG_ERROR(
"Unable to load bank information.");
400 unsigned int sector, uint32_t *ret_addr)
403 if (sector >
bank->num_sectors)
406 *ret_addr =
bank->base +
bank->sectors[sector].offset;
420 LOG_ERROR(
"Unable to write erase command sequence");
434 LOG_ERROR(
"Cannot read flash status register.");
455 LOG_ERROR(
"Timed out waiting for flash");
495 erase_cmd_seq[5].
magic = 0xC0;
497 erase_cmd_seq[5].
magic = 0x30;
508 LOG_ERROR(
"Cannot read flash status register.");
514 LOG_ERROR(
"Error with flash erase sequence");
537 LOG_ERROR(
"Unable to erase, target is not halted");
549 for (
unsigned int i = first; i <= last; i++) {
556 LOG_DEBUG(
"Erasing sector %u @ 0x%08"PRIx32, i, tmp_addr);
560 LOG_ERROR(
"Unable to write erase command sequence");
561 goto clear_status_and_exit;
568 goto clear_status_and_exit;
571 clear_status_and_exit:
584 LOG_ERROR(
"Unable to write enter page mode command");
601 LOG_ERROR(
"Sequence error while entering page mode");
609 uint32_t
offset,
bool user_config)
626 write_cmd_seq[2].
magic = 0xC0;
628 write_cmd_seq[2].
magic = 0xA0;
633 write_cmd_seq[3].
magic = 0xAA;
652 for (
int i = 0; i < 256; i += 8) {
682 LOG_ERROR(
"Unable to enter write command sequence");
693 LOG_ERROR(
"Error with flash write sequence");
719 LOG_ERROR(
"Unable to erase, target is not halted");
731 LOG_ERROR(
"Attempting to write past the end of flash");
742 uint8_t tmp_buf[256] = {0};
748 remaining =
MIN(
count,
sizeof(tmp_buf));
749 end_pad =
sizeof(tmp_buf) - remaining;
752 int start_pad =
offset % 256;
754 LOG_INFO(
"Write does not start on a 256 byte boundary. "
755 "Padding by %d bytes", start_pad);
756 memset(tmp_buf, 0xff, start_pad);
759 remaining -= start_pad;
766 memcpy(&tmp_buf[start_pad],
buffer, remaining);
771 memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
779 goto abort_write_and_exit;
789 abort_write_and_exit:
801 LOG_WARNING(
"Cannot communicate... target not halted.");
808 LOG_ERROR(
"Cannot read device identification register.");
812 uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
813 uint16_t rev_id = scu_idcode & 0xf;
815 const char *rev_str =
NULL;
866 dev_str =
"XMC4500 EES";
909 char prot_str[512] = {0};
911 snprintf(prot_str,
sizeof(prot_str),
"\nFlash is read protected");
913 bool otp_enabled =
false;
914 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
922 strcat(prot_str,
"\nOTP Protection is enabled for sectors:\n");
923 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
925 snprintf(otp_str,
sizeof(otp_str),
"- %d\n", i);
926 strncat(prot_str, otp_str,
sizeof(prot_str) - strlen(prot_str) - 1);
954 if (user_level < 0 || user_level > 2) {
955 LOG_ERROR(
"Invalid user level, must be 0-2");
959 fb =
bank->driver_priv;
962 temp_unprot_seq[2].
magic = user_level;
969 LOG_ERROR(
"Unable to write temp unprotect sequence");
978 LOG_INFO(
"Flash is temporarily unprotected");
980 LOG_INFO(
"Unable to disable flash protection");
1001 LOG_ERROR(
"Invalid user level. Must be 0-1");
1008 LOG_ERROR(
"Error erasing user configuration block");
1015 unsigned int first,
unsigned int last)
1018 uint8_t ucp0_buf[8 *
sizeof(uint32_t)] = {0};
1019 uint32_t ucb_base = 0;
1020 uint32_t procon = 0;
1029 if (level != 0 && read_protect) {
1030 LOG_ERROR(
"Read protection is for user level 0 only!");
1059 LOG_ERROR(
"Flash protection is installed for user %d"
1060 " and must be removed before continuing", level);
1069 if ((
bank->num_sectors == 12) && (last == 12))
1074 for (
unsigned int i = first; i <= last; i++)
1082 LOG_DEBUG(
"Setting flash protection with procon:");
1124 LOG_ERROR(
"Error writing user configuration block 0");
1139 LOG_ERROR(
"Flash passwords not set, use xmc4xxx flash_password to set them");
1145 LOG_WARNING(
"Flash protection will be temporarily disabled"
1146 " for all pages (User 0 only)!");
1160 uint32_t protection[3] = {0};
1165 LOG_ERROR(
"Unable to read flash User0 protection register");
1171 LOG_ERROR(
"Unable to read flash User1 protection register");
1177 LOG_ERROR(
"Unable to read flash User2 protection register");
1181 unsigned int sectors =
bank->num_sectors;
1189 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
1190 bank->sectors[i].is_protected = 0;
1198 for (
unsigned int i = 0; i <
ARRAY_SIZE(protection); i++) {
1202 for (
unsigned int j = 0; j < sectors; j++) {
1203 int set = (protection[i] & (1 << j)) ? 1 : 0;
1204 bank->sectors[j].is_protected |= set;
1208 bank->sectors[j + 1].is_protected |= set;
1212 if (i == 2 && set) {
1235 if (!
bank->driver_priv)
1300 .
name =
"flash_password",
1301 .handler = xmc4xxx_handle_flash_password_command,
1303 .usage =
"bank_id password1 password2",
1304 .help =
"Set the flash passwords used for protect operations. "
1305 "Passwords should be in standard hex form (0x00000000). "
1306 "(You must call this before any other protect commands) "
1307 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1308 "Please use protection carefully!",
1311 .name =
"flash_unprotect",
1312 .handler = xmc4xxx_handle_flash_unprotect_command,
1314 .usage =
"bank_id user_level[0-1]",
1315 .help =
"Permanently Removes flash protection (read and write) "
1316 "for the specified user level",
1325 .help =
"xmc4xxx flash command group",
1335 .flash_bank_command = xmc4xxx_flash_bank_command,
Support functions to access arbitrary bits in a byte array.
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_FLASH_OPERATION_FAILED
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
static struct device_config config
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
bool write_prot_otp[MAX_XMC_SECTORS]
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
#define ERROR_TARGET_NOT_HALTED
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
#define FLASH_CMD_WRITE_PAGE_2
static const unsigned int sector_capacity_12[12]
static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
#define FLASH_CMD_ERASE_5
#define FLASH_ID_XMC4100_4200
#define FLASH_CMD_LOAD_PAGE_2
static const unsigned int sector_capacity_9[9]
#define FLASH_CMD_ENTER_PAGEMODE
static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf, uint32_t offset, bool user_config)
#define FLASH_CMD_ERASE_1
static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
#define FLASH_CMD_WRITE_PAGE_1
#define FLASH_CMD_TEMP_UNPROT_1
#define FLASH_REG_FLASH0_PROCON2
static const struct command_registration xmc4xxx_command_handlers[]
static int xmc4xxx_write_command_sequence(struct flash_bank *bank, struct xmc4xxx_command_seq *seq, int seq_len)
static int xmc4xxx_probe(struct flash_bank *bank)
#define FLASH_CMD_CLEAR_STATUS
#define FLASH_REG_FLASH0_PROCON1
#define FLASH_CMD_ERASE_4
static int xmc4xxx_protect_check(struct flash_bank *bank)
static int xmc4xxx_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
static const struct command_registration xmc4xxx_exec_command_handlers[]
static const unsigned int sector_capacity_8[8]
static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address, bool user_config)
static const unsigned int sector_capacity_16[16]
#define FLASH_CMD_TEMP_UNPROT_3
#define FLASH_CMD_TEMP_UNPROT_5
COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
static int xmc4xxx_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
const struct flash_driver xmc4xxx_flash
#define FLASH_CMD_ERASE_2
#define FLASH_ID_XMC4300_XMC4700_4800
static int xmc4xxx_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
#define FLASH_REG_FLASH0_ID
static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
#define FLASH_REG_FLASH0_FSR
#define FLASH_CMD_TEMP_UNPROT_2
#define FLASH_CMD_WRITE_PAGE_3
FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
#define FLASH_CMD_TEMP_UNPROT_6
#define FLASH_CMD_LOAD_PAGE_1
#define FLASH_CMD_TEMP_UNPROT_4
static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
#define FLASH_CMD_ERASE_3
static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank, unsigned int sector, uint32_t *ret_addr)
static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect, unsigned int first, unsigned int last)
#define FLASH_REG_FLASH0_PROCON0
static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
#define FLASH_PROTECT_CONFIRMATION_CODE