OpenOCD
mxc.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2009 by Alexei Babich *
5  * Rezonans plc., Chelyabinsk, Russia *
6  * impatt@mail.ru *
7  * *
8  * Copyright (C) 2010 by Gaetan CARLIER *
9  * Trump s.a., Belgium *
10  * *
11  * Copyright (C) 2011 by Erik Ahlen *
12  * Avalon Innovation, Sweden *
13  ***************************************************************************/
14 
15 /*
16  * Freescale iMX OpenOCD NAND Flash controller support.
17  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
18  */
19 
20 /*
21  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
22  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
23  * "nand write # file 0", "nand verify"
24  *
25  * get_next_halfword_from_sram_buffer() not tested
26  * !! all function only tested with 2k page nand device; mxc_write_page
27  * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
28  * !! oob must be be used due to NFS bug
29  * !! oob must be 64 bytes per 2KiB page
30 */
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34 
35 #include "imp.h"
36 #include "mxc.h"
37 #include <target/target.h>
38 
39 #define OOB_SIZE 64
40 
41 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
42  mxc_nf_info->mxc_version == MXC_VERSION_MX31)
43 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
44  mxc_nf_info->mxc_version == MXC_VERSION_MX35)
45 
46 /* This permits to print (in LOG_INFO) how much bytes
47  * has been written after a page read or write.
48  * This is useful when OpenOCD is used with a graphical
49  * front-end to estimate progression of the global read/write
50  */
51 #undef _MXC_PRINT_STAT
52 /* #define _MXC_PRINT_STAT */
53 
54 static const char target_not_halted_err_msg[] =
55  "target must be halted to use mxc NAND flash controller";
56 static const char data_block_size_err_msg[] =
57  "minimal granularity is one half-word, %" PRIu32 " is incorrect";
58 static const char sram_buffer_bounds_err_msg[] =
59  "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
60 static const char get_status_register_err_msg[] = "can't get NAND status";
61 static uint32_t in_sram_address;
62 static unsigned char sign_of_sequental_byte_read;
63 
64 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
65 static int initialize_nf_controller(struct nand_device *nand);
66 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
67 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
68 static int poll_for_complete_op(struct nand_device *nand, const char *text);
69 static int validate_target_state(struct nand_device *nand);
70 static int do_data_output(struct nand_device *nand);
71 
72 static int mxc_command(struct nand_device *nand, uint8_t command);
73 static int mxc_address(struct nand_device *nand, uint8_t address);
74 
75 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
76 {
77  struct mxc_nf_controller *mxc_nf_info;
78  int hwecc_needed;
79 
80  mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
81  if (!mxc_nf_info) {
82  LOG_ERROR("no memory for nand controller");
83  return ERROR_FAIL;
84  }
85  nand->controller_priv = mxc_nf_info;
86 
87  if (CMD_ARGC < 4) {
88  LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
89  return ERROR_FAIL;
90  }
91 
92  /*
93  * check board type
94  */
95  if (strcmp(CMD_ARGV[2], "mx25") == 0) {
96  mxc_nf_info->mxc_version = MXC_VERSION_MX25;
97  mxc_nf_info->mxc_base_addr = 0xBB000000;
98  mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
99  } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
100  mxc_nf_info->mxc_version = MXC_VERSION_MX27;
101  mxc_nf_info->mxc_base_addr = 0xD8000000;
102  mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
103  } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
104  mxc_nf_info->mxc_version = MXC_VERSION_MX31;
105  mxc_nf_info->mxc_base_addr = 0xB8000000;
106  mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
107  } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
108  mxc_nf_info->mxc_version = MXC_VERSION_MX35;
109  mxc_nf_info->mxc_base_addr = 0xBB000000;
110  mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
111  }
112 
113  /*
114  * check hwecc requirements
115  */
116  hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
117  if (hwecc_needed == 0)
118  mxc_nf_info->flags.hw_ecc_enabled = 1;
119  else
120  mxc_nf_info->flags.hw_ecc_enabled = 0;
121 
122  mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
123  mxc_nf_info->fin = MXC_NF_FIN_NONE;
124  mxc_nf_info->flags.target_little_endian =
125  (nand->target->endianness == TARGET_LITTLE_ENDIAN);
126 
127  /*
128  * should factory bad block indicator be swapped
129  * as a workaround for how the nfc handles pages.
130  */
131  if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
132  LOG_DEBUG("BI-swap enabled");
133  mxc_nf_info->flags.biswap_enabled = 1;
134  }
135 
136  return ERROR_OK;
137 }
138 
139 COMMAND_HANDLER(handle_mxc_biswap_command)
140 {
141  struct nand_device *nand = NULL;
142  struct mxc_nf_controller *mxc_nf_info = NULL;
143 
144  if (CMD_ARGC < 1 || CMD_ARGC > 2)
146 
147  int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
148  if (retval != ERROR_OK) {
149  command_print(CMD, "invalid nand device number or name: %s", CMD_ARGV[0]);
151  }
152 
153  mxc_nf_info = nand->controller_priv;
154  if (CMD_ARGC == 2) {
155  if (strcmp(CMD_ARGV[1], "enable") == 0)
156  mxc_nf_info->flags.biswap_enabled = true;
157  else
158  mxc_nf_info->flags.biswap_enabled = false;
159  }
160  if (mxc_nf_info->flags.biswap_enabled)
161  command_print(CMD, "BI-swapping enabled on %s", nand->name);
162  else
163  command_print(CMD, "BI-swapping disabled on %s", nand->name);
164 
165  return ERROR_OK;
166 }
167 
168 static const struct command_registration mxc_sub_command_handlers[] = {
169  {
170  .name = "biswap",
171  .mode = COMMAND_EXEC,
172  .handler = handle_mxc_biswap_command,
173  .help = "Turns on/off bad block information swapping from main area, "
174  "without parameter query status.",
175  .usage = "bank_id ['enable'|'disable']",
176  },
178 };
179 
180 static const struct command_registration mxc_nand_command_handler[] = {
181  {
182  .name = "mxc",
183  .mode = COMMAND_ANY,
184  .help = "MXC NAND flash controller commands",
185  .chain = mxc_sub_command_handlers,
186  .usage = "",
187  },
189 };
190 
191 static int mxc_init(struct nand_device *nand)
192 {
193  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
194  struct target *target = nand->target;
195 
196  int validate_target_result;
197  uint16_t buffsize_register_content;
198  uint32_t sreg_content;
199  uint32_t sreg = MX2_FMCR;
200  uint32_t sel_16bit = MX2_FMCR_NF_16BIT_SEL;
201  uint32_t sel_fms = MX2_FMCR_NF_FMS;
202  int retval;
203  uint16_t nand_status_content;
204  /*
205  * validate target state
206  */
207  validate_target_result = validate_target_state(nand);
208  if (validate_target_result != ERROR_OK)
209  return validate_target_result;
210 
211  if (nfc_is_v1()) {
212  target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
213  mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
214  } else
215  mxc_nf_info->flags.one_kb_sram = 0;
216 
217  if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
218  sreg = MX3_PCSR;
219  sel_16bit = MX3_PCSR_NF_16BIT_SEL;
220  sel_fms = MX3_PCSR_NF_FMS;
221  } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
222  sreg = MX25_RCSR;
223  sel_16bit = MX25_RCSR_NF_16BIT_SEL;
224  sel_fms = MX25_RCSR_NF_FMS;
225  } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
226  sreg = MX35_RCSR;
227  sel_16bit = MX35_RCSR_NF_16BIT_SEL;
228  sel_fms = MX35_RCSR_NF_FMS;
229  }
230 
231  target_read_u32(target, sreg, &sreg_content);
232  if (!nand->bus_width) {
233  /* bus_width not yet defined. Read it from MXC_FMCR */
234  nand->bus_width = (sreg_content & sel_16bit) ? 16 : 8;
235  } else {
236  /* bus_width forced in soft. Sync it to MXC_FMCR */
237  sreg_content |= ((nand->bus_width == 16) ? sel_16bit : 0x00000000);
238  target_write_u32(target, sreg, sreg_content);
239  }
240  if (nand->bus_width == 16)
241  LOG_DEBUG("MXC_NF : bus is 16-bit width");
242  else
243  LOG_DEBUG("MXC_NF : bus is 8-bit width");
244 
245  if (!nand->page_size)
246  nand->page_size = (sreg_content & sel_fms) ? 2048 : 512;
247  else {
248  sreg_content |= ((nand->page_size == 2048) ? sel_fms : 0x00000000);
249  target_write_u32(target, sreg, sreg_content);
250  }
251  if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
252  LOG_ERROR("NAND controller have only 1 kb SRAM, so "
253  "pagesize 2048 is incompatible with it");
254  } else
255  LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
256 
257  if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
258  LOG_ERROR("MXC driver does not have support for 4k pagesize.");
259 
261 
262  retval = ERROR_OK;
263  retval |= mxc_command(nand, NAND_CMD_STATUS);
264  retval |= mxc_address(nand, 0x00);
265  retval |= do_data_output(nand);
266  if (retval != ERROR_OK) {
268  return ERROR_FAIL;
269  }
270  target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
271  if (!(nand_status_content & 0x0080)) {
272  LOG_INFO("NAND read-only");
273  mxc_nf_info->flags.nand_readonly = 1;
274  } else
275  mxc_nf_info->flags.nand_readonly = 0;
276  return ERROR_OK;
277 }
278 
279 static int mxc_read_data(struct nand_device *nand, void *data)
280 {
281  int validate_target_result;
282  int try_data_output_from_nand_chip;
283  /*
284  * validate target state
285  */
286  validate_target_result = validate_target_state(nand);
287  if (validate_target_result != ERROR_OK)
288  return validate_target_result;
289 
290  /*
291  * get data from nand chip
292  */
293  try_data_output_from_nand_chip = do_data_output(nand);
294  if (try_data_output_from_nand_chip != ERROR_OK) {
295  LOG_ERROR("mxc_read_data : read data failed : '%x'",
296  try_data_output_from_nand_chip);
297  return try_data_output_from_nand_chip;
298  }
299 
300  if (nand->bus_width == 16)
302  else
303  get_next_byte_from_sram_buffer(nand, data);
304 
305  return ERROR_OK;
306 }
307 
308 static int mxc_write_data(struct nand_device *nand, uint16_t data)
309 {
310  LOG_ERROR("write_data() not implemented");
312 }
313 
314 static int mxc_reset(struct nand_device *nand)
315 {
316  /*
317  * validate target state
318  */
319  int validate_target_result;
320  validate_target_result = validate_target_state(nand);
321  if (validate_target_result != ERROR_OK)
322  return validate_target_result;
324  return ERROR_OK;
325 }
326 
327 static int mxc_command(struct nand_device *nand, uint8_t command)
328 {
329  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
330  struct target *target = nand->target;
331  int validate_target_result;
332  int poll_result;
333  /*
334  * validate target state
335  */
336  validate_target_result = validate_target_state(nand);
337  if (validate_target_result != ERROR_OK)
338  return validate_target_result;
339 
340  switch (command) {
341  case NAND_CMD_READOOB:
343  /* set read point for data_read() and read_block_data() to
344  * spare area in SRAM buffer
345  */
346  if (nfc_is_v1())
348  else
350  break;
351  case NAND_CMD_READ1:
353  /*
354  * offset == one half of page size
355  */
357  break;
358  default:
360  break;
361  }
362 
364  /*
365  * start command input operation (set MXC_NF_BIT_OP_DONE==0)
366  */
368  poll_result = poll_for_complete_op(nand, "command");
369  if (poll_result != ERROR_OK)
370  return poll_result;
371  /*
372  * reset cursor to begin of the buffer
373  */
375  /* Handle special read command and adjust NF_CFG2(FDO) */
376  switch (command) {
377  case NAND_CMD_READID:
378  mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
379  mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
380  break;
381  case NAND_CMD_STATUS:
382  mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
383  mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
385  in_sram_address = 0;
386  break;
387  case NAND_CMD_READ0:
388  mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
389  mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
390  break;
391  default:
392  /* Other command use the default 'One page data out' FDO */
393  mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
394  break;
395  }
396  return ERROR_OK;
397 }
398 
399 static int mxc_address(struct nand_device *nand, uint8_t address)
400 {
401  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
402  struct target *target = nand->target;
403  int validate_target_result;
404  int poll_result;
405  /*
406  * validate target state
407  */
408  validate_target_result = validate_target_state(nand);
409  if (validate_target_result != ERROR_OK)
410  return validate_target_result;
411 
413  /*
414  * start address input operation (set MXC_NF_BIT_OP_DONE==0)
415  */
417  poll_result = poll_for_complete_op(nand, "address");
418  if (poll_result != ERROR_OK)
419  return poll_result;
420 
421  return ERROR_OK;
422 }
423 
424 static int mxc_nand_ready(struct nand_device *nand, int tout)
425 {
426  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
427  struct target *target = nand->target;
428  uint16_t poll_complete_status;
429  int validate_target_result;
430 
431  /*
432  * validate target state
433  */
434  validate_target_result = validate_target_state(nand);
435  if (validate_target_result != ERROR_OK)
436  return validate_target_result;
437 
438  do {
439  target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
440  if (poll_complete_status & MXC_NF_BIT_OP_DONE)
441  return tout;
442 
443  alive_sleep(1);
444  } while (tout-- > 0);
445  return tout;
446 }
447 
448 static int mxc_write_page(struct nand_device *nand, uint32_t page,
449  uint8_t *data, uint32_t data_size,
450  uint8_t *oob, uint32_t oob_size)
451 {
452  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
453  struct target *target = nand->target;
454  int retval;
455  uint16_t nand_status_content;
456  uint16_t swap1, swap2, new_swap1;
457  uint8_t bufs;
458  int poll_result;
459 
460  if (data_size % 2) {
463  }
464  if (oob_size % 2) {
467  }
468  if (!data) {
469  LOG_ERROR("nothing to program");
471  }
472 
473  /*
474  * validate target state
475  */
476  retval = validate_target_state(nand);
477  if (retval != ERROR_OK)
478  return retval;
479 
482  retval = ERROR_OK;
483  retval |= mxc_command(nand, NAND_CMD_SEQIN);
484  retval |= mxc_address(nand, 0); /* col */
485  retval |= mxc_address(nand, 0); /* col */
486  retval |= mxc_address(nand, page & 0xff); /* page address */
487  retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
488  retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
489 
491  if (oob) {
492  if (mxc_nf_info->flags.hw_ecc_enabled) {
493  /*
494  * part of spare block will be overridden by hardware
495  * ECC generator
496  */
497  LOG_DEBUG("part of spare block will be overridden "
498  "by hardware ECC generator");
499  }
500  if (nfc_is_v1())
502  else {
503  uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
504  while (oob_size > 0) {
505  uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
506  target_write_buffer(target, addr, len, oob);
507  addr = align_address_v2(nand, addr + len);
508  oob += len;
509  oob_size -= len;
510  }
511  }
512  }
513 
514  if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
515  /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
517  if (oob) {
518  LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
520  }
521  swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
522  new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
523  swap2 = (swap1 << 8) | (swap2 & 0xFF);
524  target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
525  if (nfc_is_v1())
527  else
529  }
530 
531  /*
532  * start data input operation (set MXC_NF_BIT_OP_DONE==0)
533  */
534  if (nfc_is_v1() && nand->page_size > 512)
535  bufs = 4;
536  else
537  bufs = 1;
538 
539  for (uint8_t i = 0; i < bufs; ++i) {
542  poll_result = poll_for_complete_op(nand, "data input");
543  if (poll_result != ERROR_OK)
544  return poll_result;
545  }
546 
547  retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
548  if (retval != ERROR_OK)
549  return retval;
550 
551  /*
552  * check status register
553  */
554  retval = ERROR_OK;
555  retval |= mxc_command(nand, NAND_CMD_STATUS);
557  mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
558  mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
559  retval |= do_data_output(nand);
560  if (retval != ERROR_OK) {
562  return retval;
563  }
564  target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
565  if (nand_status_content & 0x0001) {
566  /*
567  * page not correctly written
568  */
570  }
571 #ifdef _MXC_PRINT_STAT
572  LOG_INFO("%d bytes newly written", data_size);
573 #endif
574  return ERROR_OK;
575 }
576 
577 static int mxc_read_page(struct nand_device *nand, uint32_t page,
578  uint8_t *data, uint32_t data_size,
579  uint8_t *oob, uint32_t oob_size)
580 {
581  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
582  struct target *target = nand->target;
583  int retval;
584  uint8_t bufs;
585  uint16_t swap1, swap2, new_swap1;
586 
587  if (data_size % 2) {
590  }
591  if (oob_size % 2) {
594  }
595 
596  /*
597  * validate target state
598  */
599  retval = validate_target_state(nand);
600  if (retval != ERROR_OK)
601  return retval;
602  /* Reset address_cycles before mxc_command ?? */
603  retval = mxc_command(nand, NAND_CMD_READ0);
604  if (retval != ERROR_OK)
605  return retval;
606  retval = mxc_address(nand, 0); /* col */
607  if (retval != ERROR_OK)
608  return retval;
609  retval = mxc_address(nand, 0); /* col */
610  if (retval != ERROR_OK)
611  return retval;
612  retval = mxc_address(nand, page & 0xff);/* page address */
613  if (retval != ERROR_OK)
614  return retval;
615  retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
616  if (retval != ERROR_OK)
617  return retval;
618  retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
619  if (retval != ERROR_OK)
620  return retval;
621  retval = mxc_command(nand, NAND_CMD_READSTART);
622  if (retval != ERROR_OK)
623  return retval;
624 
625  if (nfc_is_v1() && nand->page_size > 512)
626  bufs = 4;
627  else
628  bufs = 1;
629 
630  for (uint8_t i = 0; i < bufs; ++i) {
632  mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
633  retval = do_data_output(nand);
634  if (retval != ERROR_OK) {
635  LOG_ERROR("MXC_NF : Error reading page %d", i);
636  return retval;
637  }
638  }
639 
640  if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
641  uint32_t spare_buffer3;
642  /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
644  if (nfc_is_v1())
645  spare_buffer3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
646  else
647  spare_buffer3 = MXC_NF_V2_SPARE_BUFFER3;
648  target_read_u16(target, spare_buffer3, &swap2);
649  new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
650  swap2 = (swap1 << 8) | (swap2 & 0xFF);
651  target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
652  target_write_u16(target, spare_buffer3, swap2);
653  }
654 
655  if (data)
656  target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
657  if (oob) {
658  if (nfc_is_v1())
660  else {
661  uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
662  while (oob_size > 0) {
663  uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
664  target_read_buffer(target, addr, len, oob);
665  addr = align_address_v2(nand, addr + len);
666  oob += len;
667  oob_size -= len;
668  }
669  }
670  }
671 
672 #ifdef _MXC_PRINT_STAT
673  if (data_size > 0) {
674  /* When Operation Status is read (when page is erased),
675  * this function is used but data_size is null.
676  */
677  LOG_INFO("%d bytes newly read", data_size);
678  }
679 #endif
680  return ERROR_OK;
681 }
682 
683 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
684 {
685  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
686  uint32_t ret = addr;
688  (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
690  else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
692  return ret;
693 }
694 
695 static int initialize_nf_controller(struct nand_device *nand)
696 {
697  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
698  struct target *target = nand->target;
699  uint16_t work_mode = 0;
700  uint16_t temp;
701  /*
702  * resets NAND flash controller in zero time ? I don't know.
703  */
705  if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
706  work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
707 
709  LOG_DEBUG("MXC_NF : work in Big Endian mode");
710  work_mode |= MXC_NF_BIT_BE_EN;
711  } else
712  LOG_DEBUG("MXC_NF : work in Little Endian mode");
713  if (mxc_nf_info->flags.hw_ecc_enabled) {
714  LOG_DEBUG("MXC_NF : work with ECC mode");
715  work_mode |= MXC_NF_BIT_ECC_EN;
716  } else
717  LOG_DEBUG("MXC_NF : work without ECC mode");
718  if (nfc_is_v2()) {
720  if (nand->page_size) {
721  uint16_t pages_per_block = nand->erase_size / nand->page_size;
722  work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
723  }
724  work_mode |= MXC_NF_BIT_ECC_4BIT;
725  }
726  target_write_u16(target, MXC_NF_CFG1, work_mode);
727 
728  /*
729  * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
730  */
733  if ((temp & 0x0007) == 1) {
734  LOG_ERROR("NAND flash is tight-locked, reset needed");
735  return ERROR_FAIL;
736  }
737 
738  /*
739  * unlock NAND flash for write
740  */
741  if (nfc_is_v1()) {
744  } else {
753  }
755 
756  /*
757  * 0x0000 means that first SRAM buffer @base_addr will be used
758  */
760  /*
761  * address of SRAM buffer
762  */
765  return ERROR_OK;
766 }
767 
768 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
769 {
770  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
771  struct target *target = nand->target;
772  static uint8_t even_byte;
773  uint16_t temp;
774  /*
775  * host-big_endian ??
776  */
778  even_byte = 0;
779 
782  *value = 0;
784  even_byte = 0;
786  } else {
787  if (nfc_is_v2())
789 
791  if (even_byte) {
792  *value = temp >> 8;
793  even_byte = 0;
794  in_sram_address += 2;
795  } else {
796  *value = temp & 0xff;
797  even_byte = 1;
798  }
799  }
801  return ERROR_OK;
802 }
803 
804 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
805 {
806  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
807  struct target *target = nand->target;
808 
811  *value = 0;
813  } else {
814  if (nfc_is_v2())
816 
818  in_sram_address += 2;
819  }
820  return ERROR_OK;
821 }
822 
823 static int poll_for_complete_op(struct nand_device *nand, const char *text)
824 {
825  if (mxc_nand_ready(nand, 1000) == -1) {
826  LOG_ERROR("%s sending timeout", text);
828  }
829  return ERROR_OK;
830 }
831 
832 static int validate_target_state(struct nand_device *nand)
833 {
834  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
835  struct target *target = nand->target;
836 
837  if (target->state != TARGET_HALTED) {
840  }
841 
842  if (mxc_nf_info->flags.target_little_endian !=
844  /*
845  * endianness changed after NAND controller probed
846  */
848  }
849  return ERROR_OK;
850 }
851 
852 static int ecc_status_v1(struct nand_device *nand)
853 {
854  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
855  struct target *target = nand->target;
856  uint16_t ecc_status;
857 
858  target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
859  switch (ecc_status & 0x000c) {
860  case 1 << 2:
861  LOG_INFO("main area read with 1 (correctable) error");
862  break;
863  case 2 << 2:
864  LOG_INFO("main area read with more than 1 (incorrectable) error");
866  }
867  switch (ecc_status & 0x0003) {
868  case 1:
869  LOG_INFO("spare area read with 1 (correctable) error");
870  break;
871  case 2:
872  LOG_INFO("main area read with more than 1 (incorrectable) error");
874  }
875  return ERROR_OK;
876 }
877 
878 static int ecc_status_v2(struct nand_device *nand)
879 {
880  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
881  struct target *target = nand->target;
882  uint16_t ecc_status;
883  uint8_t no_subpages;
884  uint8_t err;
885 
886  no_subpages = nand->page_size >> 9;
887 
888  target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
889  do {
890  err = ecc_status & 0xF;
891  if (err > 4) {
892  LOG_INFO("UnCorrectable RS-ECC Error");
894  } else if (err > 0)
895  LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
896  ecc_status >>= 4;
897  } while (--no_subpages);
898  return ERROR_OK;
899 }
900 
901 static int do_data_output(struct nand_device *nand)
902 {
903  struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
904  struct target *target = nand->target;
905  int poll_result;
906  switch (mxc_nf_info->fin) {
907  case MXC_NF_FIN_DATAOUT:
908  /*
909  * start data output operation (set MXC_NF_BIT_OP_DONE==0)
910  */
912  poll_result = poll_for_complete_op(nand, "data output");
913  if (poll_result != ERROR_OK)
914  return poll_result;
915 
916  mxc_nf_info->fin = MXC_NF_FIN_NONE;
917  /*
918  * ECC stuff
919  */
920  if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
921  int ecc_status;
922  if (nfc_is_v1())
923  ecc_status = ecc_status_v1(nand);
924  else
925  ecc_status = ecc_status_v2(nand);
926  if (ecc_status != ERROR_OK)
927  return ecc_status;
928  }
929  break;
930  case MXC_NF_FIN_NONE:
931  break;
932  }
933  return ERROR_OK;
934 }
935 
937  .name = "mxc",
938  .nand_device_command = &mxc_nand_device_command,
939  .commands = mxc_nand_command_handler,
940  .init = &mxc_init,
941  .reset = &mxc_reset,
942  .command = &mxc_command,
943  .address = &mxc_address,
944  .write_data = &mxc_write_data,
945  .read_data = &mxc_read_data,
946  .write_page = &mxc_write_page,
947  .read_page = &mxc_read_page,
948  .nand_ready = &mxc_nand_ready,
949 };
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:117
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:387
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
void alive_sleep(uint64_t ms)
Definition: log.c:460
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_INFO(expr ...)
Definition: log.h:117
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
#define MX3_PCSR
Definition: mx3.h:76
#define nfc_is_v2()
Definition: mxc.c:43
static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
Definition: mxc.c:768
static int mxc_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: mxc.c:448
static int poll_for_complete_op(struct nand_device *nand, const char *text)
Definition: mxc.c:823
static int mxc_nand_ready(struct nand_device *nand, int tout)
Definition: mxc.c:424
static int ecc_status_v2(struct nand_device *nand)
Definition: mxc.c:878
static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
Definition: mxc.c:804
static uint32_t in_sram_address
Definition: mxc.c:61
static int mxc_read_data(struct nand_device *nand, void *data)
Definition: mxc.c:279
static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
Definition: mxc.c:683
static unsigned char sign_of_sequental_byte_read
Definition: mxc.c:62
NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
Definition: mxc.c:75
static const struct command_registration mxc_sub_command_handlers[]
Definition: mxc.c:168
struct nand_flash_controller mxc_nand_flash_controller
Definition: mxc.c:936
#define OOB_SIZE
Definition: mxc.c:39
static int ecc_status_v1(struct nand_device *nand)
Definition: mxc.c:852
static int validate_target_state(struct nand_device *nand)
Definition: mxc.c:832
static int mxc_reset(struct nand_device *nand)
Definition: mxc.c:314
#define nfc_is_v1()
Definition: mxc.c:41
static const char sram_buffer_bounds_err_msg[]
Definition: mxc.c:58
static const char data_block_size_err_msg[]
Definition: mxc.c:56
static int mxc_command(struct nand_device *nand, uint8_t command)
Definition: mxc.c:327
static int do_data_output(struct nand_device *nand)
Definition: mxc.c:901
static const char target_not_halted_err_msg[]
Definition: mxc.c:54
static int mxc_write_data(struct nand_device *nand, uint16_t data)
Definition: mxc.c:308
static const struct command_registration mxc_nand_command_handler[]
Definition: mxc.c:180
static int mxc_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: mxc.c:577
static int mxc_init(struct nand_device *nand)
Definition: mxc.c:191
COMMAND_HANDLER(handle_mxc_biswap_command)
Definition: mxc.c:139
static int mxc_address(struct nand_device *nand, uint8_t address)
Definition: mxc.c:399
static const char get_status_register_err_msg[]
Definition: mxc.c:60
static int initialize_nf_controller(struct nand_device *nand)
Definition: mxc.c:695
#define MX25_RCSR_NF_FMS
Definition: mxc.h:111
#define MXC_NF_BIT_ECC_4BIT
Definition: mxc.h:78
#define MXC_NF_V1_SPARE_BUFFER3
Definition: mxc.h:56
#define MXC_NF_BIT_OP_FCI
Definition: mxc.h:90
#define MXC_NF_SPARE_BUFFER_MAX
Definition: mxc.h:71
#define MXC_NF_BIT_OP_FDI
Definition: mxc.h:98
#define MX2_FMCR_NF_FMS
Definition: mxc.h:108
#define MXC_NF_ECCSTATUS
Definition: mxc.h:27
#define MXC_NF_CFG2
Definition: mxc.h:47
#define MXC_NF_V2_UNLOCKEND3
Definition: mxc.h:41
#define MX3_PCSR_NF_FMS
Definition: mxc.h:115
#define MX25_RCSR_NF_16BIT_SEL
Definition: mxc.h:110
#define MXC_NF_V2_UNLOCKEND1
Definition: mxc.h:39
#define MXC_NF_MAIN_BUFFER3
Definition: mxc.h:52
#define MXC_NF_V2_UNLOCKEND2
Definition: mxc.h:40
#define MXC_NF_SPARE_BUFFER_LEN
Definition: mxc.h:70
#define MXC_NF_BIT_INT_DIS
Definition: mxc.h:81
#define MXC_NF_BUFCFG
Definition: mxc.h:26
#define MX2_FMCR_NF_16BIT_SEL
Definition: mxc.h:107
@ MXC_VERSION_MX25
Definition: mxc.h:123
@ MXC_VERSION_MX27
Definition: mxc.h:124
@ MXC_VERSION_MX35
Definition: mxc.h:126
@ MXC_VERSION_MX31
Definition: mxc.h:125
#define MXC_NF_BIT_OP_DONE
Definition: mxc.h:102
#define MXC_NF_BIT_ECC_EN
Definition: mxc.h:80
#define MXC_NF_V1_UNLOCKSTART
Definition: mxc.h:32
#define MX35_RCSR_NF_16BIT_SEL
Definition: mxc.h:117
#define MXC_NF_V2_UNLOCKSTART3
Definition: mxc.h:37
#define MXC_NF_FCMD
Definition: mxc.h:25
#define MXC_NF_FADDR
Definition: mxc.h:24
#define MXC_NF_V1_SPARE_BUFFER0
Definition: mxc.h:53
#define MXC_NF_V2_SPAS
Definition: mxc.h:30
#define MX35_RCSR_NF_4K
Definition: mxc.h:119
#define MXC_NF_V2_UNLOCKSTART1
Definition: mxc.h:35
#define MXC_NF_BIT_RESET_EN
Definition: mxc.h:83
#define MXC_NF_V2_UNLOCKSTART2
Definition: mxc.h:36
#define MXC_NF_FWP
Definition: mxc.h:31
@ MXC_NF_FIN_DATAOUT
Definition: mxc.h:137
@ MXC_NF_FIN_NONE
Definition: mxc.h:136
@ MXC_NF_DATAOUT_NANDID
Definition: mxc.h:131
@ MXC_NF_DATAOUT_NANDSTATUS
Definition: mxc.h:132
@ MXC_NF_DATAOUT_PAGE
Definition: mxc.h:130
#define MX35_RCSR
Definition: mxc.h:116
#define MXC_NF_V2_SPARE_BUFFER0
Definition: mxc.h:61
#define MXC_NF_V1_UNLOCKEND
Definition: mxc.h:33
#define MX25_RCSR
Definition: mxc.h:109
#define MXC_NF_MAIN_BUFFER0
Definition: mxc.h:49
#define MXC_NF_V2_SPARE_BUFFER3
Definition: mxc.h:64
#define MX2_FMCR
Definition: mxc.h:106
#define MXC_NF_BUFSIZ
Definition: mxc.h:22
#define MX3_PCSR_NF_16BIT_SEL
Definition: mxc.h:114
#define MXC_NF_BIT_OP_FAI
Definition: mxc.h:94
#define MXC_NF_V2_UNLOCKEND0
Definition: mxc.h:38
#define MXC_NF_V2_UNLOCKSTART0
Definition: mxc.h:34
#define MXC_NF_BIT_BE_EN
Definition: mxc.h:82
#define MXC_NF_V2_LAST_BUFFADDR
Definition: mxc.h:74
#define MXC_NF_V2_CFG1_PPB(x)
Definition: mxc.h:85
#define MXC_NF_CFG1
Definition: mxc.h:46
#define MXC_NF_BIT_DATAOUT_TYPE(x)
Definition: mxc.h:101
#define MXC_NF_V1_LAST_BUFFADDR
Definition: mxc.h:72
#define MX35_RCSR_NF_FMS
Definition: mxc.h:118
#define MXC_NF_BUFADDR
Definition: mxc.h:23
#define ERROR_NAND_OPERATION_FAILED
Definition: nand/core.h:214
@ NAND_CMD_SEQIN
Definition: nand/core.h:148
@ NAND_CMD_READSTART
Definition: nand/core.h:155
@ NAND_CMD_READOOB
Definition: nand/core.h:144
@ NAND_CMD_READ0
Definition: nand/core.h:140
@ NAND_CMD_READID
Definition: nand/core.h:150
@ NAND_CMD_STATUS
Definition: nand/core.h:146
@ NAND_CMD_READ1
Definition: nand/core.h:141
@ NAND_CMD_PAGEPROG
Definition: nand/core.h:143
uint32_t addr
Definition: nuttx.c:65
#define MIN(a, b)
Definition: replacements.h:22
const char * name
Definition: command.h:229
const char * usage
a string listing the options and arguments, required or optional
Definition: command.h:235
enum mxc_version mxc_version
Definition: mxc.h:149
struct mxc_nf_flags flags
Definition: mxc.h:154
uint32_t mxc_regs_addr
Definition: mxc.h:151
enum mxc_nf_finalize_action fin
Definition: mxc.h:153
uint32_t mxc_base_addr
Definition: mxc.h:150
enum mxc_dataout_type optype
Definition: mxc.h:152
unsigned hw_ecc_enabled
Definition: mxc.h:144
unsigned biswap_enabled
Definition: mxc.h:145
unsigned target_little_endian
Definition: mxc.h:141
unsigned one_kb_sram
Definition: mxc.h:143
unsigned nand_readonly
Definition: mxc.h:142
void * controller_priv
Definition: nand/core.h:51
int page_size
Definition: nand/core.h:56
int bus_width
Definition: nand/core.h:54
int erase_size
Definition: nand/core.h:57
const char * name
Definition: nand/core.h:48
struct target * target
Definition: nand/core.h:49
Interface for NAND flash controllers.
Definition: nand/driver.h:23
const char * name
Driver name that is used to select it from configuration files.
Definition: nand/driver.h:25
Definition: target.h:120
enum target_state state
Definition: target.h:162
enum target_endianness endianness
Definition: target.h:160
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2408
int target_write_u16(struct target *target, target_addr_t address, uint16_t value)
Definition: target.c:2728
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2473
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2640
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2616
@ TARGET_HALTED
Definition: target.h:55
@ TARGET_BIG_ENDIAN
Definition: target.h:86
@ TARGET_LITTLE_ENDIAN
Definition: target.h:86
#define NULL
Definition: usb.h:16