30 "target must be halted to use mx3 NAND flash controller";
32 "minimal granularity is one half-word, %" PRIu32
" is incorrect";
34 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
40 uint32_t
mask,
const char *text);
57 LOG_ERROR(
"no memory for nand controller");
61 nand->controller_priv = mx3_nf_info;
70 hwecc_needed = strcmp(
CMD_ARGV[2],
"hwecc");
71 if (hwecc_needed == 0)
94 int validate_target_result;
96 if (validate_target_result !=
ERROR_OK)
97 return validate_target_result;
101 uint16_t buffsize_register_content;
107 uint32_t pcsr_register_content;
110 nand->
bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
112 pcsr_register_content |= ((nand->
bus_width == 16) ? 0x80000000 : 0x00000000);
117 nand->
page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
119 pcsr_register_content |= ((nand->
page_size == 2048) ? 0x40000000 : 0x00000000);
123 LOG_ERROR(
"NAND controller have only 1 kb SRAM, "
124 "so pagesize 2048 is incompatible with it");
129 uint32_t cgr_register_content;
131 if (!(cgr_register_content & 0x00000300)) {
132 LOG_ERROR(
"clock gating to EMI disabled");
138 uint32_t gpr_register_content;
140 if (gpr_register_content & 0x00000060) {
141 LOG_ERROR(
"pins mode overridden by GPR");
163 "nfwe,nfre,nfale,nfcle");
172 uint16_t nand_status_content;
182 if (!(nand_status_content & 0x0080)) {
201 int validate_target_result;
203 if (validate_target_result !=
ERROR_OK)
204 return validate_target_result;
211 int try_data_output_from_nand_chip;
213 if (try_data_output_from_nand_chip !=
ERROR_OK)
214 return try_data_output_from_nand_chip;
227 LOG_ERROR(
"write_data() not implemented");
236 int validate_target_result;
238 if (validate_target_result !=
ERROR_OK)
239 return validate_target_result;
252 int validate_target_result;
254 if (validate_target_result !=
ERROR_OK)
255 return validate_target_result;
319 int validate_target_result;
321 if (validate_target_result !=
ERROR_OK)
322 return validate_target_result;
341 uint16_t poll_complete_status;
348 int validate_target_result;
350 if (validate_target_result !=
ERROR_OK)
351 return validate_target_result;
359 }
while (tout-- > 0);
364 uint8_t *data, uint32_t data_size, uint8_t *oob,
409 LOG_DEBUG(
"part of spare block will be overridden by hardware ECC generator");
431 uint16_t nand_status_content;
441 if (nand_status_content & 0x0001) {
453 uint8_t *data, uint32_t data_size, uint8_t *oob,
506 uint32_t
mask,
const char *text)
508 uint32_t register_content;
510 if ((register_content &
mask) != (0x12121212 &
mask)) {
511 LOG_ERROR(
"IOMUX for {%s} is bad", text);
541 if ((temp & 0x0007) == 1) {
542 LOG_ERROR(
"NAND flash is tight-locked, reset needed");
567 static uint8_t even_byte;
587 *value = temp & 0xff;
611 uint16_t poll_complete_status;
612 for (
int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
649 switch (mx3_nf_info->
fin) {
670 switch (ecc_status & 0x000c) {
672 LOG_DEBUG(
"main area read with 1 (correctable) error");
675 LOG_DEBUG(
"main area read with more than 1 (incorrectable) error");
678 switch (ecc_status & 0x0003) {
680 LOG_DEBUG(
"spare area read with 1 (correctable) error");
683 LOG_DEBUG(
"main area read with more than 1 (incorrectable) error");
696 .usage =
"nand device imx31 target noecc|hwecc",
697 .nand_device_command = &imx31_nand_device_command,
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
void alive_sleep(uint64_t ms)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
static int imx31_command(struct nand_device *nand, uint8_t command)
NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
static uint32_t in_sram_address
static int imx31_init(struct nand_device *nand)
static int imx31_address(struct nand_device *nand, uint8_t address)
static unsigned char sign_of_sequental_byte_read
static int imx31_reset(struct nand_device *nand)
static int imx31_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value)
struct nand_flash_controller imx31_nand_flash_controller
static int imx31_write_data(struct nand_device *nand, uint16_t data)
static int imx31_nand_ready(struct nand_device *nand, int tout)
static int imx31_read_data(struct nand_device *nand, void *data)
static int validate_target_state(struct nand_device *nand)
static int test_iomux_settings(struct target *target, uint32_t value, uint32_t mask, const char *text)
static int imx31_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static const char sram_buffer_bounds_err_msg[]
static const char data_block_size_err_msg[]
static int do_data_output(struct nand_device *nand)
static const char target_not_halted_err_msg[]
static int poll_for_complete_op(struct target *target, const char *text)
static const char get_status_register_err_msg[]
static int initialize_nf_controller(struct nand_device *nand)
static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
#define MX3_NF_BIT_OP_FDI
#define MX3_NF_BIT_INT_DIS
#define MX3_NF_BIT_RESET_EN
#define MX3_NF_BIT_OP_FCI
@ MX3_NF_DATAOUT_NANDSTATUS
#define MX3_NF_BIT_DATAOUT_TYPE(x)
#define MX3_NF_BIT_ECC_EN
#define MX3_NF_MAIN_BUFFER0
#define MX3_NF_BIT_OP_FAI
#define MX3_NF_SPARE_BUFFER0
#define MX3_NF_LAST_BUFFER_ADDR
#define MX3_NF_BIT_OP_DONE
#define ERROR_NAND_OPERATION_FAILED
struct mx3_nf_flags flags
enum mx_nf_finalize_action fin
enum mx_dataout_type optype
unsigned target_little_endian
Interface for NAND flash controllers.
const char * name
Driver name that is used to select it from configuration files.
enum target_endianness endianness
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_u16(struct target *target, target_addr_t address, uint16_t value)
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)