28 u_char *read_ecc, u_char *calc_ecc);
38 #define ECC_OFFS 0x120
39 #define SPARE_OFFS 0x140
40 #define DATA_OFFS 0x200
43 10, 11, 12, 13, 14, 15
46 40, 41, 42, 43, 44, 45,
47 46, 47, 48, 49, 50, 51,
48 52, 53, 54, 55, 56, 57,
49 58, 59, 60, 61, 62, 63
73 nand->controller_priv = lpc32xx_info;
78 LOG_WARNING(
"LPC32xx oscillator frequency should be between "
79 "1000 and 20000 kHz, was %i",
92 int bypass = (pll_ctrl & 0x8000) >> 15;
93 int direct = (pll_ctrl & 0x4000) >> 14;
94 int feedback = (pll_ctrl & 0x2000) >> 13;
95 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
96 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
97 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
98 int lock = (pll_ctrl & 0x1);
103 if (!bypass && direct)
104 return (m * fclkin) / n;
106 if (bypass && !direct)
107 return fclkin / (2 * p);
113 return m * (fclkin / n);
115 return (m / (2 * p)) * (fclkin / n);
122 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
138 if ((sysclk_ctrl & 1) == 0)
150 if ((pwr_ctrl & (1 << 2)) == 0)
155 LOG_ERROR(
"could not read HCLKPLL_CTRL");
166 if (pwr_ctrl & (1 << 10))
167 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
169 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
172 LOG_DEBUG(
"LPC32xx HCLK currently clocked at %i kHz", hclk);
174 cycle = (1.0 / hclk) * 1000000.0;
189 LOG_ERROR(
"target must be halted to use LPC32xx "
190 "NAND flash controller");
195 if (bus_width != 8) {
196 LOG_ERROR(
"LPC32xx doesn't support %i", bus_width);
203 if ((address_cycles < 3) || (address_cycles > 5)) {
204 LOG_ERROR(
"LPC32xx driver doesn't support %i address cycles", address_cycles);
208 if ((page_size != 512) && (page_size != 2048)) {
209 LOG_ERROR(
"LPC32xx doesn't support page size %i", page_size);
215 LOG_DEBUG(
"no LPC32xx NAND flash controller selected, "
216 "using default 'slc'");
221 uint32_t mlc_icr_value = 0x0;
223 int twp, twh, trp, treh, trhz, trbwb, tcea;
228 LOG_ERROR(
"could not set FLASHCLK_CTRL");
248 mlc_icr_value |= 0x8;
249 if (page_size == 2048)
250 mlc_icr_value |= 0x4;
251 if (address_cycles == 4)
252 mlc_icr_value |= 0x2;
254 mlc_icr_value |= 0x1;
264 twp = ((40 / cycle) + 1);
265 twh = ((20 / cycle) + 1);
266 trp = ((30 / cycle) + 1);
267 treh = ((15 / cycle) + 1);
268 trhz = ((30 / cycle) + 1);
269 trbwb = ((100 / cycle) + 1);
270 tcea = ((45 / cycle) + 1);
284 | ((treh & 0xf) << 12)
285 | ((trhz & 0x7) << 16)
286 | ((trbwb & 0x1f) << 19)
287 | ((tcea & 0x3) << 24));
298 int r_setup, r_hold, r_width, r_rdy;
299 int w_setup, w_hold, w_width, w_rdy;
304 LOG_ERROR(
"could not set FLASHCLK_CTRL");
324 0x3e | ((bus_width == 16) ? 1 : 0));
356 r_setup = w_setup = 0;
357 r_hold = w_hold = 10 / cycle;
358 r_width = 30 / cycle;
359 w_width = 40 / cycle;
360 r_rdy = w_rdy = 100 / cycle;
365 | ((r_hold & 0xf) << 4)
366 | ((r_width & 0xf) << 8)
367 | ((r_rdy & 0xf) << 12)
368 | ((w_setup & 0xf) << 16)
369 | ((w_hold & 0xf) << 20)
370 | ((w_width & 0xf) << 24)
371 | ((w_rdy & 0xf) << 28));
388 LOG_ERROR(
"target must be halted to use "
389 "LPC32xx NAND flash controller");
394 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
405 LOG_ERROR(
"LPC32xx MLC NAND controller timed out "
418 LOG_ERROR(
"LPC32xx SLC NAND controller timed out "
434 LOG_ERROR(
"target must be halted to use "
435 "LPC32xx NAND flash controller");
440 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
468 LOG_ERROR(
"target must be halted to use "
469 "LPC32xx NAND flash controller");
474 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
502 LOG_ERROR(
"target must be halted to use "
503 "LPC32xx NAND flash controller");
508 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
536 LOG_ERROR(
"target must be halted to use LPC32xx "
537 "NAND flash controller");
542 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
547 uint8_t *data8 = data;
550 LOG_ERROR(
"BUG: bus_width neither 8 nor 16 bit");
568 uint8_t *data8 = data;
569 *data8 = data32 & 0xff;
571 LOG_ERROR(
"BUG: bus_width neither 8 nor 16 bit");
580 uint8_t *data, uint32_t data_size,
581 uint8_t *oob, uint32_t oob_size)
586 static uint8_t page_buffer[512];
587 static uint8_t oob_buffer[6];
588 int quarter, num_quarters;
620 (page >> 16) & 0xff);
657 num_quarters = (nand->
page_size == 2048) ? 4 : 1;
659 for (quarter = 0; quarter < num_quarters; quarter++) {
660 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
661 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
663 memset(page_buffer, 0xff, 512);
665 memcpy(page_buffer, data, thisrun_data_size);
666 data_size -= thisrun_data_size;
667 data += thisrun_data_size;
670 memset(oob_buffer, 0xff, 6);
672 memcpy(oob_buffer, oob, thisrun_oob_size);
673 oob_size -= thisrun_oob_size;
674 oob += thisrun_oob_size;
680 LOG_ERROR(
"could not set MLC_ECC_ENC_REG");
685 4, 128, page_buffer);
687 LOG_ERROR(
"could not set MLC_BUF (data)");
693 LOG_ERROR(
"could not set MLC_BUF (oob)");
700 LOG_ERROR(
"could not set MLC_ECC_AUTO_ENC_REG");
706 "completion of auto encode cycle");
725 LOG_ERROR(
"write operation didn't pass, status: 0x%2.2x",
741 uint32_t i, dmasrc,
ctrl, ecc_ctrl, oob_ctrl, dmadst;
783 ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
784 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
798 ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
799 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
813 oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
814 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
815 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
855 for (i = 0; i < page_size/0x100; i++) {
859 target_mem_base + (i*2 + 1) *
sizeof(
struct dmac_ll);
862 dmalist[(i*2) + 1].dma_src = 0x20020034;
866 target_mem_base + (i*2 + 2) *
sizeof(
struct dmac_ll);
894 LOG_ERROR(
"Could not set DMACIntTCClear");
901 LOG_ERROR(
"Could not set DMACIntErrClear");
916 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
917 | 0<<15 | 0<<16 | 0<<18);
940 LOG_ERROR(
"lpc32xx_start_slc_dma: Could not set SLC_TC");
946 LOG_ERROR(
"timeout while waiting for completion of DMA");
967 LOG_ERROR(
"Could not read DMACRawIntTCStat");
973 LOG_ERROR(
"Could not read DMACRawIntErrStat");
976 if ((tc_stat | err_stat) & 1) {
981 "DMA error, aborted");
997 for (i = 0; i < (
count * 3); i += 3) {
998 uint32_t ce =
ecc[i/3];
999 ce = ~(ce << 2) & 0xFFFFFF;
1000 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1001 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1002 spare[i] = (uint8_t)(ce & 0xFF);
1010 while (oob_size > 0) {
1011 LOG_DEBUG(
"%02x: %02x %02x %02x %02x %02x %02x %02x %02x",
addr,
1012 oob[0], oob[1], oob[2], oob[3],
1013 oob[4], oob[5], oob[6], oob[7]);
1022 uint32_t page, uint8_t *data,
1023 uint32_t data_size, uint8_t *oob,
1028 uint32_t target_mem_base;
1030 LOG_DEBUG(
"SLC write page %" PRIx32
" data=%d, oob=%d, "
1031 "data_size=%" PRIu32
", oob_size=%" PRIu32,
1032 page, data != 0, oob != 0, data_size, oob_size);
1034 target_mem_base = pworking_area->
address;
1040 uint32_t i, all_ff = 1;
1041 for (i = 0; i < data_size; i++)
1042 if (data[i] != 0xFF) {
1055 nll *
sizeof(
struct dmac_ll) / 4,
1058 LOG_ERROR(
"Could not write DMA descriptors to IRAM");
1083 static uint8_t fdata[2048];
1085 memcpy(fdata, data, data_size);
1090 LOG_ERROR(
"Could not write data to IRAM");
1099 LOG_ERROR(
"Could not write DMA descriptor to DMAC");
1105 tot_size += tot_size == 2048 ? 64 : 16;
1114 LOG_ERROR(
"Data DMA failed during write");
1120 static uint8_t foob[64];
1121 int foob_size = nand->
page_size == 2048 ? 64 : 16;
1122 memset(foob, 0xFF, foob_size);
1124 memcpy(foob, oob, oob_size);
1127 int ecc_count = nand->
page_size == 2048 ? 8 : 2;
1128 static uint32_t hw_ecc[8];
1130 4, ecc_count, (uint8_t *)hw_ecc);
1132 LOG_ERROR(
"Reading hw generated ECC from IRAM failed");
1136 static uint8_t
ecc[24];
1140 for (i = 0; i < ecc_count * 3; i++)
1141 foob[layout[i]] =
ecc[i];
1145 foob_size / 4, foob);
1147 LOG_ERROR(
"Writing OOB to IRAM failed");
1154 (uint8_t *)(&
dmalist[nll-1]));
1156 LOG_ERROR(
"Could not write OOB DMA descriptor to DMAC");
1166 LOG_ERROR(
"Could not set DMACIntTCClear");
1180 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1181 | 0<<15 | 0<<16 | 0<<18);
1183 LOG_ERROR(
"Could not set DMACC0Config");
1189 "completion of DMA");
1212 uint8_t *data, uint32_t data_size,
1213 uint8_t *oob, uint32_t oob_size)
1220 LOG_ERROR(
"target must be halted to use LPC32xx "
1221 "NAND flash controller");
1226 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
1230 LOG_ERROR(
"LPC32xx MLC controller can't write "
1235 if (oob && (oob_size > 24)) {
1236 LOG_ERROR(
"LPC32xx MLC controller can't write more "
1237 "than 6 bytes for each quarter's OOB data");
1241 if (data_size > (uint32_t)nand->
page_size) {
1242 LOG_ERROR(
"data size exceeds page size");
1257 data_size, oob, oob_size);
1263 LOG_ERROR(
"Can't allocate working area in "
1264 "LPC internal RAM");
1268 data, data_size, oob, oob_size);
1276 uint8_t *data, uint32_t data_size,
1277 uint8_t *oob, uint32_t oob_size)
1280 static uint8_t page_buffer[2048];
1281 static uint8_t oob_buffer[64];
1282 uint32_t page_bytes_done = 0;
1283 uint32_t oob_bytes_done = 0;
1319 (page >> 8) & 0xff);
1327 (page >> 16) & 0xff);
1354 (page >> 8) & 0xff);
1369 while (page_bytes_done < (uint32_t)nand->
page_size) {
1373 LOG_ERROR(
"could not set MLC_ECC_AUTO_DEC_REG");
1379 "completion of auto decode cycle");
1389 if (mlc_isr & 0x8) {
1390 if (mlc_isr & 0x40) {
1391 LOG_ERROR(
"uncorrectable error detected: "
1392 "0x%2.2x", (
unsigned)mlc_isr);
1396 LOG_WARNING(
"%i symbol error detected and corrected",
1397 ((
int)(((mlc_isr & 0x30) >> 4) + 1)));
1402 page_buffer + page_bytes_done);
1404 LOG_ERROR(
"could not read MLC_BUF (data)");
1411 oob_buffer + oob_bytes_done);
1413 LOG_ERROR(
"could not read MLC_BUF (oob)");
1418 page_bytes_done += 512;
1419 oob_bytes_done += 16;
1423 memcpy(data, page_buffer, data_size);
1426 memcpy(oob, oob_buffer, oob_size);
1433 uint32_t page, uint8_t *data,
1434 uint32_t data_size, uint8_t *oob,
1439 uint32_t target_mem_base;
1441 LOG_DEBUG(
"SLC read page %" PRIx32
" data=%" PRIu32
", oob=%" PRIu32,
1442 page, data_size, oob_size);
1444 target_mem_base = pworking_area->
address;
1452 nll *
sizeof(
struct dmac_ll) / 4,
1455 LOG_ERROR(
"Could not write DMA descriptors to IRAM");
1461 LOG_ERROR(
"lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1475 LOG_ERROR(
"lpc32xx_read_page_slc: Could not set SLC_CFG");
1483 LOG_ERROR(
"Could not write DMA descriptor to DMAC");
1489 tot_size += nand->
page_size == 2048 ? 64 : 16;
1492 LOG_ERROR(
"lpc32xx_read_page_slc: DMA read failed");
1499 4, data_size/4, data);
1501 LOG_ERROR(
"Could not read data from IRAM");
1511 LOG_ERROR(
"Could not read OOB from IRAM");
1518 static uint8_t foob[64];
1520 4, nand->
page_size == 2048 ? 16 : 4, foob);
1523 LOG_ERROR(
"Could not read OOB from IRAM");
1527 int ecc_count = nand->
page_size == 2048 ? 8 : 2;
1528 static uint32_t hw_ecc[8];
1530 ecc_count, (uint8_t *)hw_ecc);
1532 LOG_ERROR(
"Could not read hw generated ECC from IRAM");
1535 static uint8_t
ecc[24];
1538 static uint8_t fecc[24];
1541 for (i = 0; i < ecc_count * 3; i++)
1542 fecc[i] = foob[layout[i]];
1544 for (i = 0; i < ecc_count; i++) {
1548 LOG_WARNING(
"error detected and corrected: %" PRIu32
"/%d",
1556 LOG_ERROR(
"uncorrectable error detected: %" PRIu32
"/%d", page, i);
1563 uint8_t *data, uint32_t data_size,
1564 uint8_t *oob, uint32_t oob_size)
1571 LOG_ERROR(
"target must be halted to use LPC32xx "
1572 "NAND flash controller");
1577 LOG_ERROR(
"BUG: no LPC32xx NAND flash controller selected");
1580 if (data_size > (uint32_t)nand->
page_size) {
1581 LOG_ERROR(
"data size exceeds page size");
1593 LOG_ERROR(
"Can't allocate working area in "
1594 "LPC internal RAM");
1598 data, data_size, oob, oob_size);
1612 LOG_ERROR(
"target must be halted to use LPC32xx "
1613 "NAND flash controller");
1631 LOG_DEBUG(
"lpc32xx_controller_ready count=%d",
1646 LOG_DEBUG(
"lpc32xx_controller_ready count=%d",
1665 LOG_ERROR(
"target must be halted to use LPC32xx "
1666 "NAND flash controller");
1685 LOG_DEBUG(
"lpc32xx_nand_ready count end=%d",
1700 LOG_DEBUG(
"lpc32xx_nand_ready count end=%d",
1724 LOG_ERROR(
"Could not read SLC_INT_STAT");
1741 char *selected[] = {
1760 if (strcmp(
CMD_ARGV[1],
"mlc") == 0) {
1763 }
else if (strcmp(
CMD_ARGV[1],
"slc") == 0) {
1779 .handler = handle_lpc32xx_select_command,
1781 .help =
"select MLC or SLC controller (default is MLC)",
1782 .usage =
"bank_id ['mlc'|'slc' ]",
1790 .help =
"LPC32xx NAND flash controller commands",
1800 .nand_device_command = lpc32xx_nand_device_command,
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_FLASH_OPERATION_FAILED
int nand_read_status(struct nand_device *nand, uint8_t *status)
int nand_write_finish(struct nand_device *nand)
int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
struct nand_device * get_nand_device_by_num(int num)
int nand_page_command(struct nand_device *nand, uint32_t page, uint8_t cmd, bool oob_only)
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, int do_read)
static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
static int lpc32xx_write_page_slc(struct nand_device *nand, struct working_area *pworking_area, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static const struct command_registration lpc32xx_command_handler[]
static int lpc32xx_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static int lpc32xx_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static const int sp_ooblayout[]
static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
static int lpc32xx_address(struct nand_device *nand, uint8_t address)
static const int lp_ooblayout[]
static int lpc32xx_read_data(struct nand_device *nand, void *data)
static float lpc32xx_cycle_time(struct nand_device *nand)
static int lpc32xx_init(struct nand_device *nand)
static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, int do_wait)
static const struct command_registration lpc32xx_exec_command_handlers[]
static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
static int lpc32xx_reset(struct nand_device *nand)
static struct dmac_ll dmalist[(2048/256) *2+1]
COMMAND_HANDLER(handle_lpc32xx_select_command)
int nand_correct_data(struct nand_device *nand, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
nand_correct_data - Detect and correct a 1 bit error for 256 byte block
static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare, const uint32_t *ecc, int count)
NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
static int lpc32xx_read_page_slc(struct nand_device *nand, struct working_area *pworking_area, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
static int lpc32xx_command(struct nand_device *nand, uint8_t command)
#define ERROR_NAND_OPERATION_TIMEOUT
#define ERROR_NAND_OPERATION_FAILED
#define ERROR_NAND_OPERATION_NOT_SUPPORTED
struct rtt_control ctrl
Control block.
volatile uint32_t next_lli
volatile uint32_t dma_dest
volatile uint32_t dma_src
volatile uint32_t next_ctrl
uint32_t sw_wp_upper_bound
uint32_t sw_wp_lower_bound
enum lpc32xx_selected_controller selected_controller
Interface for NAND flash controllers.
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.