OpenOCD
armv7a_cache_l2x.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2015 Oleksij Rempel *
5  * linux@rempel-privat.de *
6  ***************************************************************************/
7 
8 #ifndef OPENOCD_TARGET_ARM7A_CACHE_L2X_H
9 #define OPENOCD_TARGET_ARM7A_CACHE_L2X_H
10 
11 #define L2X0_CACHE_LINE_SIZE 32
12 
13 /* source: linux/arch/arm/include/asm/hardware/cache-l2x0.h */
14 #define L2X0_CACHE_ID 0x000
15 #define L2X0_CACHE_TYPE 0x004
16 #define L2X0_CTRL 0x100
17 #define L2X0_AUX_CTRL 0x104
18 #define L2X0_TAG_LATENCY_CTRL 0x108
19 #define L2X0_DATA_LATENCY_CTRL 0x10C
20 #define L2X0_EVENT_CNT_CTRL 0x200
21 #define L2X0_EVENT_CNT1_CFG 0x204
22 #define L2X0_EVENT_CNT0_CFG 0x208
23 #define L2X0_EVENT_CNT1_VAL 0x20C
24 #define L2X0_EVENT_CNT0_VAL 0x210
25 #define L2X0_INTR_MASK 0x214
26 #define L2X0_MASKED_INTR_STAT 0x218
27 #define L2X0_RAW_INTR_STAT 0x21C
28 #define L2X0_INTR_CLEAR 0x220
29 #define L2X0_CACHE_SYNC 0x730
30 #define L2X0_DUMMY_REG 0x740
31 #define L2X0_INV_LINE_PA 0x770
32 #define L2X0_INV_WAY 0x77C
33 #define L2X0_CLEAN_LINE_PA 0x7B0
34 #define L2X0_CLEAN_LINE_IDX 0x7B8
35 #define L2X0_CLEAN_WAY 0x7BC
36 #define L2X0_CLEAN_INV_LINE_PA 0x7F0
37 #define L2X0_CLEAN_INV_LINE_IDX 0x7F8
38 #define L2X0_CLEAN_INV_WAY 0x7FC
39 /*
40  * The lockdown registers repeat 8 times for L310, the L210 has only one
41  * D and one I lockdown register at 0x0900 and 0x0904.
42  */
43 #define L2X0_LOCKDOWN_WAY_D_BASE 0x900
44 #define L2X0_LOCKDOWN_WAY_I_BASE 0x904
45 #define L2X0_LOCKDOWN_STRIDE 0x08
46 #define L2X0_ADDR_FILTER_START 0xC00
47 #define L2X0_ADDR_FILTER_END 0xC04
48 #define L2X0_TEST_OPERATION 0xF00
49 #define L2X0_LINE_DATA 0xF10
50 #define L2X0_LINE_TAG 0xF30
51 #define L2X0_DEBUG_CTRL 0xF40
52 #define L2X0_PREFETCH_CTRL 0xF60
53 #define L2X0_POWER_CTRL 0xF80
54 #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
55 #define L2X0_STNDBY_MODE_EN (1 << 0)
56 
57 /* Registers shifts and masks */
58 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
59 #define L2X0_CACHE_ID_PART_L210 (1 << 6)
60 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
61 #define L2X0_CACHE_ID_RTL_MASK 0x3f
62 #define L2X0_CACHE_ID_RTL_R0P0 0x0
63 #define L2X0_CACHE_ID_RTL_R1P0 0x2
64 #define L2X0_CACHE_ID_RTL_R2P0 0x4
65 #define L2X0_CACHE_ID_RTL_R3P0 0x5
66 #define L2X0_CACHE_ID_RTL_R3P1 0x6
67 #define L2X0_CACHE_ID_RTL_R3P2 0x8
68 
69 #define L2X0_AUX_CTRL_MASK 0xc0000fff
70 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
71 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
72 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
73 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
74 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
75 #define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
76 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
77 #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
78 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
79 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
80 #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
81 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
82 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
83 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
84 #define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
85 #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
86 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
87 
88 #define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
89 #define L2X0_LATENCY_CTRL_RD_SHIFT 4
90 #define L2X0_LATENCY_CTRL_WR_SHIFT 8
91 
92 #define L2X0_ADDR_FILTER_EN 1
93 
94 #define L2X0_CTRL_EN 1
95 
96 #define L2X0_WAY_SIZE_SHIFT 3
97 
98 struct l2x0_regs {
99  unsigned long phy_base;
100  unsigned long aux_ctrl;
101  /*
102  * Whether the following registers need to be saved/restored
103  * depends on platform
104  */
105  unsigned long tag_latency;
106  unsigned long data_latency;
107  unsigned long filter_start;
108  unsigned long filter_end;
109  unsigned long prefetch_ctrl;
110  unsigned long pwr_ctrl;
111  unsigned long ctrl;
112  unsigned long aux2_ctrl;
113 };
114 
116  void (*inv_range)(unsigned long, unsigned long);
117  void (*clean_range)(unsigned long, unsigned long);
118  void (*flush_range)(unsigned long, unsigned long);
119  void (*flush_all)(void);
120  void (*disable)(void);
121 
122  void (*resume)(void);
123 
124  /* This is an ARM L2C thing */
125  void (*write_sec)(unsigned long, unsigned);
126  void (*configure)(const struct l2x0_regs *);
127 };
128 
130  const char *type;
131  unsigned way_size_0;
132  unsigned num_lock;
133 
134  void (*enable)(uint32_t, uint32_t, unsigned);
135  void (*fixup)(uint32_t, uint32_t, struct outer_cache_fns *);
136  void (*save)(uint32_t);
137  void (*configure)(uint32_t);
139 };
140 
142 
144  uint32_t size);
146 
147 #endif /* OPENOCD_TARGET_ARM7A_CACHE_L2X_H */
int arm7a_l2x_flush_all_data(struct target *target)
int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt, uint32_t size)
const struct command_registration arm7a_l2x_cache_command_handler[]
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
void(* enable)(uint32_t, uint32_t, unsigned)
struct outer_cache_fns outer_cache
void(* fixup)(uint32_t, uint32_t, struct outer_cache_fns *)
const char * type
void(* configure)(uint32_t)
void(* save)(uint32_t)
unsigned long ctrl
unsigned long filter_start
unsigned long aux_ctrl
unsigned long prefetch_ctrl
unsigned long data_latency
unsigned long phy_base
unsigned long pwr_ctrl
unsigned long tag_latency
unsigned long aux2_ctrl
unsigned long filter_end
void(* flush_range)(unsigned long, unsigned long)
void(* flush_all)(void)
void(* inv_range)(unsigned long, unsigned long)
void(* disable)(void)
void(* clean_range)(unsigned long, unsigned long)
void(* write_sec)(unsigned long, unsigned)
void(* resume)(void)
void(* configure)(const struct l2x0_regs *)
Definition: target.h:120
uint64_t target_addr_t
Definition: types.h:335