14 #ifndef OPENOCD_TARGET_CORTEX_M_H
15 #define OPENOCD_TARGET_CORTEX_M_H
20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
22 #define SYSTEM_CONTROL_BASE 0x400FE000
24 #define ITM_TER0 0xE0000E00
25 #define ITM_TPR 0xE0000E40
26 #define ITM_TCR 0xE0000E80
27 #define ITM_TCR_ITMENA_BIT BIT(0)
28 #define ITM_TCR_BUSY_BIT BIT(23)
29 #define ITM_LAR 0xE0000FB0
30 #define ITM_LAR_KEY 0xC5ACCE55
32 #define CPUID 0xE000ED00
34 #define ARM_CPUID_IMPLEMENTOR_POS 24
35 #define ARM_CPUID_IMPLEMENTOR_MASK (0xFF << ARM_CPUID_IMPLEMENTOR_POS)
36 #define ARM_CPUID_PARTNO_POS 4
37 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
39 #define ARM_MAKE_CPUID(impl, partno) ((((impl) << ARM_CPUID_IMPLEMENTOR_POS) & ARM_CPUID_IMPLEMENTOR_MASK) | \
40 (((partno) << ARM_CPUID_PARTNO_POS) & ARM_CPUID_PARTNO_MASK))
66 #define CORTEX_M_F_HAS_FPV4 BIT(0)
67 #define CORTEX_M_F_HAS_FPV5 BIT(1)
68 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
78 #define DCB_DHCSR 0xE000EDF0
79 #define DCB_DCRSR 0xE000EDF4
80 #define DCB_DCRDR 0xE000EDF8
81 #define DCB_DEMCR 0xE000EDFC
82 #define DCB_DSCSR 0xE000EE08
84 #define DAUTHSTATUS 0xE000EFB8
85 #define DAUTHSTATUS_SID_MASK 0x00000030
87 #define DCRSR_WNR BIT(16)
89 #define DWT_CTRL 0xE0001000
90 #define DWT_CYCCNT 0xE0001004
91 #define DWT_PCSR 0xE000101C
92 #define DWT_COMP0 0xE0001020
93 #define DWT_MASK0 0xE0001024
94 #define DWT_FUNCTION0 0xE0001028
95 #define DWT_DEVARCH 0xE0001FBC
97 #define DWT_DEVARCH_ARMV8M_V2_0 0x101A02
98 #define DWT_DEVARCH_ARMV8M_V2_1 0x111A02
100 #define FP_CTRL 0xE0002000
101 #define FP_REMAP 0xE0002004
102 #define FP_COMP0 0xE0002008
103 #define FP_COMP1 0xE000200C
104 #define FP_COMP2 0xE0002010
105 #define FP_COMP3 0xE0002014
106 #define FP_COMP4 0xE0002018
107 #define FP_COMP5 0xE000201C
108 #define FP_COMP6 0xE0002020
109 #define FP_COMP7 0xE0002024
111 #define FPU_CPACR 0xE000ED88
112 #define FPU_FPCCR 0xE000EF34
113 #define FPU_FPCAR 0xE000EF38
114 #define FPU_FPDSCR 0xE000EF3C
116 #define TPIU_SSPSR 0xE0040000
117 #define TPIU_CSPSR 0xE0040004
118 #define TPIU_ACPR 0xE0040010
119 #define TPIU_SPPR 0xE00400F0
120 #define TPIU_FFSR 0xE0040300
121 #define TPIU_FFCR 0xE0040304
122 #define TPIU_FSCR 0xE0040308
125 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
128 #define DBGKEY (0xA05Ful << 16)
129 #define C_DEBUGEN BIT(0)
130 #define C_HALT BIT(1)
131 #define C_STEP BIT(2)
132 #define C_MASKINTS BIT(3)
133 #define S_REGRDY BIT(16)
134 #define S_HALT BIT(17)
135 #define S_SLEEP BIT(18)
136 #define S_LOCKUP BIT(19)
137 #define S_RETIRE_ST BIT(24)
138 #define S_RESET_ST BIT(25)
141 #define TRCENA BIT(24)
142 #define VC_HARDERR BIT(10)
143 #define VC_INTERR BIT(9)
144 #define VC_BUSERR BIT(8)
145 #define VC_STATERR BIT(7)
146 #define VC_CHKERR BIT(6)
147 #define VC_NOCPERR BIT(5)
148 #define VC_MMERR BIT(4)
149 #define VC_CORERESET BIT(0)
152 #define DSCSR_CDS BIT(16)
155 #define NVIC_ICTR 0xE000E004
156 #define NVIC_ISE0 0xE000E100
157 #define NVIC_ICSR 0xE000ED04
158 #define NVIC_AIRCR 0xE000ED0C
159 #define NVIC_SHCSR 0xE000ED24
160 #define NVIC_CFSR 0xE000ED28
161 #define NVIC_MMFSRB 0xE000ED28
162 #define NVIC_BFSRB 0xE000ED29
163 #define NVIC_USFSRH 0xE000ED2A
164 #define NVIC_HFSR 0xE000ED2C
165 #define NVIC_DFSR 0xE000ED30
166 #define NVIC_MMFAR 0xE000ED34
167 #define NVIC_BFAR 0xE000ED38
168 #define NVIC_SFSR 0xE000EDE4
169 #define NVIC_SFAR 0xE000EDE8
172 #define AIRCR_VECTKEY (0x5FAul << 16)
173 #define AIRCR_SYSRESETREQ BIT(2)
174 #define AIRCR_VECTCLRACTIVE BIT(1)
175 #define AIRCR_VECTRESET BIT(0)
177 #define SHCSR_BUSFAULTENA BIT(17)
179 #define DFSR_HALTED 1
181 #define DFSR_DWTTRAP 4
182 #define DFSR_VCATCH 8
183 #define DFSR_EXTERNAL 16
186 #define FPCR_LITERAL 1
187 #define FPCR_REPLACE_REMAP (0ul << 30)
188 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
189 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
190 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
336 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
arm_arch
ARM Architecture specifying the version and the profile.
@ ARM_IMPLEMENTOR_INFINEON
@ ARM_IMPLEMENTOR_REALTEK
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
static bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
void cortex_m_enable_watchpoints(struct target *target)
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
static struct cortex_m_common * target_to_cortex_m_safe(struct target *target)
#define CORTEX_M_COMMON_MAGIC
int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
static bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
void cortex_m_enable_breakpoints(struct target *target)
int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
int cortex_m_examine(struct target *target)
int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
#define ARM_MAKE_CPUID(impl, partno)
static struct cortex_m_common * target_to_cm(struct target *target)
@ CORTEX_M_ISRMASK_STEPONLY
int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
void cortex_m_deinit_target(struct target *target)
int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
cortex_m_impl_part
Known Arm Cortex masked CPU Ids This includes the implementor and part number, but not the revision o...
@ CORTEX_M_PARTNO_INVALID
int cortex_m_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
cortex_m_soft_reset_config
@ CORTEX_M_RESET_VECTRESET
@ CORTEX_M_RESET_SYSRESETREQ
const struct cortex_m_part_info * core_info
enum cortex_m_soft_reset_config soft_reset_config
struct armv7m_common armv7m
unsigned int dwt_comp_available
unsigned int dwt_num_comp
struct cortex_m_dwt_comparator * dwt_comparator_list
bool dcb_dhcsr_sticky_is_recent
struct cortex_m_fp_comparator * fp_comparator_list
struct reg_cache * dwt_cache
enum cortex_m_isrmasking_mode isrmasking_mode
unsigned int common_magic
uint32_t dcb_dhcsr_cumulated_sticky
uint32_t dwt_comparator_address
enum cortex_m_impl_part impl_part
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.