OpenOCD
cortex_m.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2006 by Magnus Lundin *
8  * lundin@mlu.mine.nu *
9  * *
10  * Copyright (C) 2008 by Spencer Oliver *
11  * spen@spen-soft.co.uk *
12  ***************************************************************************/
13 
14 #ifndef OPENOCD_TARGET_CORTEX_M_H
15 #define OPENOCD_TARGET_CORTEX_M_H
16 
17 #include "armv7m.h"
18 #include "helper/bits.h"
19 
20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
21 
22 #define SYSTEM_CONTROL_BASE 0x400FE000
23 
24 #define ITM_TER0 0xE0000E00
25 #define ITM_TPR 0xE0000E40
26 #define ITM_TCR 0xE0000E80
27 #define ITM_TCR_ITMENA_BIT BIT(0)
28 #define ITM_TCR_BUSY_BIT BIT(23)
29 #define ITM_LAR 0xE0000FB0
30 #define ITM_LAR_KEY 0xC5ACCE55
31 
32 #define CPUID 0xE000ED00
33 
34 #define ARM_CPUID_IMPLEMENTOR_POS 24
35 #define ARM_CPUID_IMPLEMENTOR_MASK (0xFF << ARM_CPUID_IMPLEMENTOR_POS)
36 #define ARM_CPUID_PARTNO_POS 4
37 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
38 
39 #define ARM_MAKE_CPUID(impl, partno) ((((impl) << ARM_CPUID_IMPLEMENTOR_POS) & ARM_CPUID_IMPLEMENTOR_MASK) | \
40  (((partno) << ARM_CPUID_PARTNO_POS) & ARM_CPUID_PARTNO_MASK))
41 
48  STAR_MC1_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
63 };
64 
65 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
66 #define CORTEX_M_F_HAS_FPV4 BIT(0)
67 #define CORTEX_M_F_HAS_FPV5 BIT(1)
68 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
69 
72  const char *name;
73  enum arm_arch arch;
74  uint32_t flags;
75 };
76 
77 /* Debug Control Block */
78 #define DCB_DHCSR 0xE000EDF0
79 #define DCB_DCRSR 0xE000EDF4
80 #define DCB_DCRDR 0xE000EDF8
81 #define DCB_DEMCR 0xE000EDFC
82 #define DCB_DSCSR 0xE000EE08
83 
84 #define DAUTHSTATUS 0xE000EFB8
85 #define DAUTHSTATUS_SID_MASK 0x00000030
86 
87 #define DCRSR_WNR BIT(16)
88 
89 #define DWT_CTRL 0xE0001000
90 #define DWT_CYCCNT 0xE0001004
91 #define DWT_PCSR 0xE000101C
92 #define DWT_COMP0 0xE0001020
93 #define DWT_MASK0 0xE0001024
94 #define DWT_FUNCTION0 0xE0001028
95 #define DWT_DEVARCH 0xE0001FBC
96 
97 #define DWT_DEVARCH_ARMV8M_V2_0 0x101A02
98 #define DWT_DEVARCH_ARMV8M_V2_1 0x111A02
99 
100 #define FP_CTRL 0xE0002000
101 #define FP_REMAP 0xE0002004
102 #define FP_COMP0 0xE0002008
103 #define FP_COMP1 0xE000200C
104 #define FP_COMP2 0xE0002010
105 #define FP_COMP3 0xE0002014
106 #define FP_COMP4 0xE0002018
107 #define FP_COMP5 0xE000201C
108 #define FP_COMP6 0xE0002020
109 #define FP_COMP7 0xE0002024
110 
111 #define FPU_CPACR 0xE000ED88
112 #define FPU_FPCCR 0xE000EF34
113 #define FPU_FPCAR 0xE000EF38
114 #define FPU_FPDSCR 0xE000EF3C
115 
116 #define TPIU_SSPSR 0xE0040000
117 #define TPIU_CSPSR 0xE0040004
118 #define TPIU_ACPR 0xE0040010
119 #define TPIU_SPPR 0xE00400F0
120 #define TPIU_FFSR 0xE0040300
121 #define TPIU_FFCR 0xE0040304
122 #define TPIU_FSCR 0xE0040308
123 
124 /* Maximum SWO prescaler value. */
125 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
126 
127 /* DCB_DHCSR bit and field definitions */
128 #define DBGKEY (0xA05Ful << 16)
129 #define C_DEBUGEN BIT(0)
130 #define C_HALT BIT(1)
131 #define C_STEP BIT(2)
132 #define C_MASKINTS BIT(3)
133 #define S_REGRDY BIT(16)
134 #define S_HALT BIT(17)
135 #define S_SLEEP BIT(18)
136 #define S_LOCKUP BIT(19)
137 #define S_RETIRE_ST BIT(24)
138 #define S_RESET_ST BIT(25)
139 
140 /* DCB_DEMCR bit and field definitions */
141 #define TRCENA BIT(24)
142 #define VC_HARDERR BIT(10)
143 #define VC_INTERR BIT(9)
144 #define VC_BUSERR BIT(8)
145 #define VC_STATERR BIT(7)
146 #define VC_CHKERR BIT(6)
147 #define VC_NOCPERR BIT(5)
148 #define VC_MMERR BIT(4)
149 #define VC_CORERESET BIT(0)
150 
151 /* DCB_DSCSR bit and field definitions */
152 #define DSCSR_CDS BIT(16)
153 
154 /* NVIC registers */
155 #define NVIC_ICTR 0xE000E004
156 #define NVIC_ISE0 0xE000E100
157 #define NVIC_ICSR 0xE000ED04
158 #define NVIC_AIRCR 0xE000ED0C
159 #define NVIC_SHCSR 0xE000ED24
160 #define NVIC_CFSR 0xE000ED28
161 #define NVIC_MMFSRB 0xE000ED28
162 #define NVIC_BFSRB 0xE000ED29
163 #define NVIC_USFSRH 0xE000ED2A
164 #define NVIC_HFSR 0xE000ED2C
165 #define NVIC_DFSR 0xE000ED30
166 #define NVIC_MMFAR 0xE000ED34
167 #define NVIC_BFAR 0xE000ED38
168 #define NVIC_SFSR 0xE000EDE4
169 #define NVIC_SFAR 0xE000EDE8
170 
171 /* NVIC_AIRCR bits */
172 #define AIRCR_VECTKEY (0x5FAul << 16)
173 #define AIRCR_SYSRESETREQ BIT(2)
174 #define AIRCR_VECTCLRACTIVE BIT(1)
175 #define AIRCR_VECTRESET BIT(0)
176 /* NVIC_SHCSR bits */
177 #define SHCSR_BUSFAULTENA BIT(17)
178 /* NVIC_DFSR bits */
179 #define DFSR_HALTED 1
180 #define DFSR_BKPT 2
181 #define DFSR_DWTTRAP 4
182 #define DFSR_VCATCH 8
183 #define DFSR_EXTERNAL 16
184 
185 #define FPCR_CODE 0
186 #define FPCR_LITERAL 1
187 #define FPCR_REPLACE_REMAP (0ul << 30)
188 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
189 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
190 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
191 
193  bool used;
194  int type;
195  uint32_t fpcr_value;
196  uint32_t fpcr_address;
197 };
198 
200  bool used;
201  uint32_t comp;
202  uint32_t mask;
203  uint32_t function;
205 };
206 
210 };
211 
217 };
218 
220  unsigned int common_magic;
221 
222  struct armv7m_common armv7m;
223 
224  /* Context information */
225  uint32_t dcb_dhcsr;
227  /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
229  uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
230  uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
231 
232  /* Flash Patch and Breakpoint (FPB) */
233  unsigned int fp_num_lit;
234  unsigned int fp_num_code;
235  int fp_rev;
238 
239  /* Data Watchpoint and Trace (DWT) */
240  unsigned int dwt_num_comp;
241  unsigned int dwt_comp_available;
242  uint32_t dwt_devarch;
245 
249 
251 
252  bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
253 
254  uint64_t apsel;
255 
256  /* Whether this target has the erratum that makes C_MASKINTS not apply to
257  * already pending interrupts */
259 };
260 
261 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
262 {
263  return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
264 }
265 
266 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
267 {
268  if (!is_cortex_m_or_hla(cortex_m))
269  return false;
270 
271  return !cortex_m->armv7m.is_hla_target;
272 }
273 
280 static inline struct cortex_m_common *
282 {
283  return container_of(target->arch_info,
284  struct cortex_m_common, armv7m.arm);
285 }
286 
293 static inline struct cortex_m_common *
295 {
296  /* Check the parent types first to prevent peeking memory too far
297  * from arch_info pointer */
299  return NULL;
300 
301  struct cortex_m_common *cortex_m = target_to_cm(target);
302  if (!is_cortex_m_or_hla(cortex_m))
303  return NULL;
304 
305  return cortex_m;
306 }
307 
313 static inline enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
314 {
315  struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
316  if (!cortex_m)
318 
319  if (!cortex_m->core_info)
321 
322  return cortex_m->core_info->impl_part;
323 }
324 
325 int cortex_m_examine(struct target *target);
334 void cortex_m_deinit_target(struct target *target);
335 int cortex_m_profiling(struct target *target, uint32_t *samples,
336  uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
337 
338 #endif /* OPENOCD_TARGET_CORTEX_M_H */
arm_arch
ARM Architecture specifying the version and the profile.
Definition: arm.h:53
@ ARM_IMPLEMENTOR_INFINEON
Definition: arm.h:64
@ ARM_IMPLEMENTOR_REALTEK
Definition: arm.h:65
@ ARM_IMPLEMENTOR_ARM
Definition: arm.h:63
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
Definition: armv7m.h:274
static bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
Definition: cortex_m.h:261
void cortex_m_enable_watchpoints(struct target *target)
Definition: cortex_m.c:2131
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
Definition: cortex_m.h:313
static struct cortex_m_common * target_to_cortex_m_safe(struct target *target)
Definition: cortex_m.h:294
#define CORTEX_M_COMMON_MAGIC
Definition: cortex_m.h:20
int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: cortex_m.c:2040
static bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
Definition: cortex_m.h:266
void cortex_m_enable_breakpoints(struct target *target)
Definition: cortex_m.c:1205
int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1915
int cortex_m_examine(struct target *target)
Definition: cortex_m.c:2487
int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: cortex_m.c:2083
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1900
#define ARM_MAKE_CPUID(impl, partno)
Definition: cortex_m.h:39
static struct cortex_m_common * target_to_cm(struct target *target)
Definition: cortex_m.h:281
cortex_m_isrmasking_mode
Definition: cortex_m.h:212
@ CORTEX_M_ISRMASK_OFF
Definition: cortex_m.h:214
@ CORTEX_M_ISRMASK_ON
Definition: cortex_m.h:215
@ CORTEX_M_ISRMASK_STEPONLY
Definition: cortex_m.h:216
@ CORTEX_M_ISRMASK_AUTO
Definition: cortex_m.h:213
int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1774
void cortex_m_deinit_target(struct target *target)
Definition: cortex_m.c:2179
int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1859
cortex_m_impl_part
Known Arm Cortex masked CPU Ids This includes the implementor and part number, but not the revision o...
Definition: cortex_m.h:46
@ CORTEX_M85_PARTNO
Definition: cortex_m.h:59
@ CORTEX_M7_PARTNO
Definition: cortex_m.h:53
@ INFINEON_SLX2_PARTNO
Definition: cortex_m.h:60
@ CORTEX_M35P_PARTNO
Definition: cortex_m.h:57
@ CORTEX_M4_PARTNO
Definition: cortex_m.h:52
@ STAR_MC1_PARTNO
Definition: cortex_m.h:48
@ CORTEX_M33_PARTNO
Definition: cortex_m.h:56
@ CORTEX_M1_PARTNO
Definition: cortex_m.h:50
@ CORTEX_M0_PARTNO
Definition: cortex_m.h:49
@ CORTEX_M0P_PARTNO
Definition: cortex_m.h:54
@ REALTEK_M200_PARTNO
Definition: cortex_m.h:61
@ CORTEX_M55_PARTNO
Definition: cortex_m.h:58
@ REALTEK_M300_PARTNO
Definition: cortex_m.h:62
@ CORTEX_M23_PARTNO
Definition: cortex_m.h:55
@ CORTEX_M_PARTNO_INVALID
Definition: cortex_m.h:47
@ CORTEX_M3_PARTNO
Definition: cortex_m.h:51
int cortex_m_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
Definition: cortex_m.c:2196
cortex_m_soft_reset_config
Definition: cortex_m.h:207
@ CORTEX_M_RESET_VECTRESET
Definition: cortex_m.h:209
@ CORTEX_M_RESET_SYSRESETREQ
Definition: cortex_m.h:208
bool is_hla_target
Definition: armv7m.h:236
struct arm arm
Definition: armv7m.h:225
const struct cortex_m_part_info * core_info
Definition: cortex_m.h:250
enum cortex_m_soft_reset_config soft_reset_config
Definition: cortex_m.h:246
struct armv7m_common armv7m
Definition: cortex_m.h:222
uint64_t apsel
Definition: cortex_m.h:254
unsigned int dwt_comp_available
Definition: cortex_m.h:241
unsigned int dwt_num_comp
Definition: cortex_m.h:240
uint32_t dcb_dhcsr
Definition: cortex_m.h:225
bool fpb_enabled
Definition: cortex_m.h:236
struct cortex_m_dwt_comparator * dwt_comparator_list
Definition: cortex_m.h:243
bool slow_register_read
Definition: cortex_m.h:252
bool dcb_dhcsr_sticky_is_recent
Definition: cortex_m.h:228
struct cortex_m_fp_comparator * fp_comparator_list
Definition: cortex_m.h:237
struct reg_cache * dwt_cache
Definition: cortex_m.h:244
unsigned int fp_num_lit
Definition: cortex_m.h:233
bool vectreset_supported
Definition: cortex_m.h:247
uint32_t dwt_devarch
Definition: cortex_m.h:242
uint32_t nvic_dfsr
Definition: cortex_m.h:229
unsigned int fp_num_code
Definition: cortex_m.h:234
bool maskints_erratum
Definition: cortex_m.h:258
enum cortex_m_isrmasking_mode isrmasking_mode
Definition: cortex_m.h:248
uint32_t nvic_icsr
Definition: cortex_m.h:230
unsigned int common_magic
Definition: cortex_m.h:220
uint32_t dcb_dhcsr_cumulated_sticky
Definition: cortex_m.h:226
uint32_t dwt_comparator_address
Definition: cortex_m.h:204
enum arm_arch arch
Definition: cortex_m.h:73
const char * name
Definition: cortex_m.h:72
enum cortex_m_impl_part impl_part
Definition: cortex_m.h:71
uint32_t flags
Definition: cortex_m.h:74
Definition: target.h:116
void * arch_info
Definition: target.h:164
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
#define NULL
Definition: usb.h:16