OpenOCD
esirisc_flash.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2018 by Square, Inc. *
5  * Steven Stallion <stallion@squareup.com> *
6  * James Zhao <hjz@squareup.com> *
7  ***************************************************************************/
8 
9 #ifdef HAVE_CONFIG_H
10 #include "config.h"
11 #endif
12 
13 #include <flash/common.h>
14 #include <flash/nor/imp.h>
15 #include <helper/command.h>
16 #include <helper/log.h>
17 #include <helper/time_support.h>
18 #include <helper/types.h>
19 #include <target/esirisc.h>
20 #include <target/target.h>
21 
22 /* eSi-TSMC Flash Registers */
23 #define CONTROL 0x00 /* Control Register */
24 #define TIMING0 0x04 /* Timing Register 0 */
25 #define TIMING1 0x08 /* Timing Register 1 */
26 #define TIMING2 0x0c /* Timing Register 2 */
27 #define UNLOCK1 0x18 /* Unlock 1 */
28 #define UNLOCK2 0x1c /* Unlock 2 */
29 #define ADDRESS 0x20 /* Erase/Program Address */
30 #define PB_DATA 0x24 /* Program Buffer Data */
31 #define PB_INDEX 0x28 /* Program Buffer Index */
32 #define STATUS 0x2c /* Status Register */
33 #define REDUN_0 0x30 /* Redundant Address 0 */
34 #define REDUN_1 0x34 /* Redundant Address 1 */
35 
36 /* Control Fields */
37 #define CONTROL_SLM (1<<0) /* Sleep Mode */
38 #define CONTROL_WP (1<<1) /* Register Write Protect */
39 #define CONTROL_E (1<<3) /* Erase */
40 #define CONTROL_EP (1<<4) /* Erase Page */
41 #define CONTROL_P (1<<5) /* Program Flash */
42 #define CONTROL_ERC (1<<6) /* Erase Reference Cell */
43 #define CONTROL_R (1<<7) /* Recall Trim Code */
44 #define CONTROL_AP (1<<8) /* Auto-Program */
45 
46 /* Timing Fields */
47 #define TIMING0_R(x) (((x) << 0) & 0x3f) /* Read Wait States */
48 #define TIMING0_F(x) (((x) << 16) & 0xffff0000) /* Tnvh Clock Cycles */
49 #define TIMING1_E(x) (((x) << 0) & 0xffffff) /* Tme/Terase/Tre Clock Cycles */
50 #define TIMING2_P(x) (((x) << 0) & 0xffff) /* Tprog Clock Cycles */
51 #define TIMING2_H(x) (((x) << 16) & 0xff0000) /* Clock Cycles in 100ns */
52 #define TIMING2_T(x) (((x) << 24) & 0xf000000) /* Clock Cycles in 10ns */
53 
54 /* Status Fields */
55 #define STATUS_BUSY (1<<0) /* Busy (Erase/Program) */
56 #define STATUS_WER (1<<1) /* Write Protect Error */
57 #define STATUS_DR (1<<2) /* Disable Redundancy */
58 #define STATUS_DIS (1<<3) /* Discharged */
59 #define STATUS_BO (1<<4) /* Brown Out */
60 
61 /* Redundant Address Fields */
62 #define REDUN_R (1<<0) /* Used */
63 #define REDUN_P(x) (((x) << 12) & 0x7f000) /* Redundant Page Address */
64 
65 /*
66  * The eSi-TSMC Flash manual provides two sets of timings based on the
67  * underlying flash process. By default, 90nm is assumed.
68  */
69 #if 0 /* 55nm */
70 #define TNVH 5000 /* 5us */
71 #define TME 80000000 /* 80ms */
72 #define TERASE 160000000 /* 160ms */
73 #define TRE 100000000 /* 100ms */
74 #define TPROG 8000 /* 8us */
75 #else /* 90nm */
76 #define TNVH 5000 /* 5us */
77 #define TME 20000000 /* 20ms */
78 #define TERASE 40000000 /* 40ms */
79 #define TRE 40000000 /* 40ms */
80 #define TPROG 40000 /* 40us */
81 #endif
82 
83 #define CONTROL_TIMEOUT 5000 /* 5s */
84 #define FLASH_PAGE_SIZE 4096
85 #define PB_MAX 32
86 
87 #define NUM_NS_PER_S 1000000000ULL
88 
90  bool probed;
91  uint32_t cfg;
92  uint32_t clock;
93  uint32_t wait_states;
94 };
95 
97 
98 FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command)
99 {
100  struct esirisc_flash_bank *esirisc_info;
101 
102  if (CMD_ARGC < 9)
104 
105  esirisc_info = calloc(1, sizeof(struct esirisc_flash_bank));
106 
107  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], esirisc_info->cfg);
108  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], esirisc_info->clock);
109  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], esirisc_info->wait_states);
110 
111  bank->driver_priv = esirisc_info;
112 
113  /* register commands using existing esirisc context */
115 
116  return ERROR_OK;
117 }
118 
119 /*
120  * Register writes are ignored if the control.WP flag is set; the
121  * following sequence is required to modify this flag even when
122  * protection is disabled.
123  */
125 {
126  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
127  struct target *target = bank->target;
128 
129  target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0x7123);
130  target_write_u32(target, esirisc_info->cfg + UNLOCK2, 0x812a);
131  target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0xbee1);
132 
133  return ERROR_OK;
134 }
135 
137 {
138  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
139  struct target *target = bank->target;
140  uint32_t control;
141 
142  target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
143  if (!(control & CONTROL_WP))
144  return ERROR_OK;
145 
146  (void)esirisc_flash_unlock(bank);
147 
148  control &= ~CONTROL_WP;
149 
150  target_write_u32(target, esirisc_info->cfg + CONTROL, control);
151 
152  return ERROR_OK;
153 }
154 
156 {
157  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
158  struct target *target = bank->target;
159  uint32_t control;
160 
161  target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
162  if (control & CONTROL_WP)
163  return ERROR_OK;
164 
165  (void)esirisc_flash_unlock(bank);
166 
167  control |= CONTROL_WP;
168 
169  target_write_u32(target, esirisc_info->cfg + CONTROL, control);
170 
171  return ERROR_OK;
172 }
173 
175 {
176  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
177  struct target *target = bank->target;
178  uint32_t status;
179 
180  target_read_u32(target, esirisc_info->cfg + STATUS, &status);
181  if (status & STATUS_WER) {
182  LOG_ERROR("%s: bad status: 0x%" PRIx32, bank->name, status);
184  }
185 
186  return ERROR_OK;
187 }
188 
190 {
191  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
192  struct target *target = bank->target;
193 
194  target_write_u32(target, esirisc_info->cfg + STATUS, STATUS_WER);
195 
196  return ERROR_OK;
197 }
198 
199 static int esirisc_flash_wait(struct flash_bank *bank, int ms)
200 {
201  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
202  struct target *target = bank->target;
203  uint32_t status;
204  int64_t t;
205 
206  t = timeval_ms();
207  for (;;) {
208  target_read_u32(target, esirisc_info->cfg + STATUS, &status);
209  if (!(status & STATUS_BUSY))
210  return ERROR_OK;
211 
212  if ((timeval_ms() - t) > ms)
213  return ERROR_TARGET_TIMEOUT;
214 
215  keep_alive();
216  }
217 }
218 
219 static int esirisc_flash_control(struct flash_bank *bank, uint32_t control)
220 {
221  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
222  struct target *target = bank->target;
223 
225 
226  target_write_u32(target, esirisc_info->cfg + CONTROL, control);
227 
228  int retval = esirisc_flash_wait(bank, CONTROL_TIMEOUT);
229  if (retval != ERROR_OK) {
230  LOG_ERROR("%s: control timed out: 0x%" PRIx32, bank->name, control);
231  return retval;
232  }
233 
235 }
236 
238 {
240 }
241 
242 static int esirisc_flash_erase(struct flash_bank *bank, unsigned int first,
243  unsigned int last)
244 {
245  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
246  struct target *target = bank->target;
247  int retval = ERROR_OK;
248 
249  if (target->state != TARGET_HALTED)
251 
253 
254  for (unsigned int page = first; page < last; ++page) {
255  uint32_t address = page * FLASH_PAGE_SIZE;
256 
257  target_write_u32(target, esirisc_info->cfg + ADDRESS, address);
258 
260  if (retval != ERROR_OK) {
261  LOG_ERROR("%s: failed to erase address: 0x%" PRIx32, bank->name, address);
262  break;
263  }
264  }
265 
267 
268  return retval;
269 }
270 
272 {
273  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
274  struct target *target = bank->target;
275  int retval;
276 
277  if (target->state != TARGET_HALTED)
279 
281 
282  target_write_u32(target, esirisc_info->cfg + ADDRESS, 0);
283 
285  if (retval != ERROR_OK)
286  LOG_ERROR("%s: failed to mass erase", bank->name);
287 
289 
290  return retval;
291 }
292 
293 /*
294  * Per TSMC, the reference cell should be erased once per sample. This
295  * is typically done during wafer sort, however we include support for
296  * those that may need to calibrate flash at a later time.
297  */
299 {
300  struct target *target = bank->target;
301  int retval;
302 
303  if (target->state != TARGET_HALTED)
305 
307 
309  if (retval != ERROR_OK)
310  LOG_ERROR("%s: failed to erase reference cell", bank->name);
311 
313 
314  return retval;
315 }
316 
318  const uint8_t *buffer, uint32_t count)
319 {
320  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
321  struct target *target = bank->target;
322  struct esirisc_common *esirisc = target_to_esirisc(target);
323 
324  /*
325  * The pb_index register is auto-incremented when pb_data is written
326  * and should be cleared before each operation.
327  */
328  target_write_u32(target, esirisc_info->cfg + PB_INDEX, 0);
329 
330  /*
331  * The width of the pb_data register depends on the underlying
332  * target; writing one byte at a time incurs a significant
333  * performance penalty and should be avoided.
334  */
335  while (count > 0) {
336  uint32_t max_bytes = DIV_ROUND_UP(esirisc->num_bits, 8);
337  uint32_t num_bytes = MIN(count, max_bytes);
338 
339  target_write_buffer(target, esirisc_info->cfg + PB_DATA, num_bytes, buffer);
340 
341  buffer += num_bytes;
342  count -= num_bytes;
343  }
344 
345  return ERROR_OK;
346 }
347 
349  const uint8_t *buffer, uint32_t offset, uint32_t count)
350 {
351  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
352  struct target *target = bank->target;
353  int retval = ERROR_OK;
354 
355  if (target->state != TARGET_HALTED)
357 
359 
360  /*
361  * The address register is auto-incremented based on the contents of
362  * the pb_index register after each operation completes. It can be
363  * set once provided pb_index is cleared before each operation.
364  */
365  target_write_u32(target, esirisc_info->cfg + ADDRESS, offset);
366 
367  /*
368  * Care must be taken when filling the program buffer; a maximum of
369  * 32 bytes may be written at a time and may not cross a 32-byte
370  * boundary based on the current offset.
371  */
372  while (count > 0) {
373  uint32_t max_bytes = PB_MAX - (offset & 0x1f);
374  uint32_t num_bytes = MIN(count, max_bytes);
375 
376  esirisc_flash_fill_pb(bank, buffer, num_bytes);
377 
379  if (retval != ERROR_OK) {
380  LOG_ERROR("%s: failed to program address: 0x%" PRIx32, bank->name, offset);
381  break;
382  }
383 
384  buffer += num_bytes;
385  offset += num_bytes;
386  count -= num_bytes;
387  }
388 
390 
391  return retval;
392 }
393 
394 static uint32_t esirisc_flash_num_cycles(struct flash_bank *bank, uint64_t ns)
395 {
396  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
397 
398  /* apply scaling factor to avoid truncation */
399  uint64_t hz = (uint64_t)esirisc_info->clock * 1000;
400  uint64_t num_cycles = ((hz / NUM_NS_PER_S) * ns) / 1000;
401 
402  if (hz % NUM_NS_PER_S > 0)
403  num_cycles++;
404 
405  return num_cycles;
406 }
407 
408 static int esirisc_flash_init(struct flash_bank *bank)
409 {
410  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
411  struct target *target = bank->target;
412  uint32_t value;
413  int retval;
414 
416 
417  /* initialize timing registers */
419  | TIMING0_R(esirisc_info->wait_states);
420 
421  LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
422  target_write_u32(target, esirisc_info->cfg + TIMING0, value);
423 
425 
426  LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
427  target_write_u32(target, esirisc_info->cfg + TIMING1, value);
428 
432 
433  LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
434  target_write_u32(target, esirisc_info->cfg + TIMING2, value);
435 
436  /* recall trim code */
437  retval = esirisc_flash_recall(bank);
438  if (retval != ERROR_OK)
439  LOG_ERROR("%s: failed to recall trim code", bank->name);
440 
442 
443  return retval;
444 }
445 
447 {
448  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
449  struct target *target = bank->target;
450  int retval;
451 
452  if (target->state != TARGET_HALTED)
454 
455  bank->num_sectors = bank->size / FLASH_PAGE_SIZE;
456  bank->sectors = alloc_block_array(0, FLASH_PAGE_SIZE, bank->num_sectors);
457 
458  retval = esirisc_flash_init(bank);
459  if (retval != ERROR_OK) {
460  LOG_ERROR("%s: failed to initialize bank", bank->name);
461  return retval;
462  }
463 
464  esirisc_info->probed = true;
465 
466  return ERROR_OK;
467 }
468 
470 {
471  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
472 
473  if (esirisc_info->probed)
474  return ERROR_OK;
475 
476  return esirisc_flash_probe(bank);
477 }
478 
480 {
481  struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
482 
484  "%4s cfg at 0x%" PRIx32 ", clock %" PRIu32 ", wait_states %" PRIu32,
485  "", /* align with first line */
486  esirisc_info->cfg,
487  esirisc_info->clock,
488  esirisc_info->wait_states);
489 
490  return ERROR_OK;
491 }
492 
493 COMMAND_HANDLER(handle_esirisc_flash_mass_erase_command)
494 {
495  struct flash_bank *bank;
496  int retval;
497 
498  if (CMD_ARGC < 1)
500 
501  retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
502  if (retval != ERROR_OK)
503  return retval;
504 
505  retval = esirisc_flash_mass_erase(bank);
506 
507  command_print(CMD, "mass erase %s",
508  (retval == ERROR_OK) ? "successful" : "failed");
509 
510  return retval;
511 }
512 
513 COMMAND_HANDLER(handle_esirisc_flash_ref_erase_command)
514 {
515  struct flash_bank *bank;
516  int retval;
517 
518  if (CMD_ARGC < 1)
520 
521  retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
522  if (retval != ERROR_OK)
523  return retval;
524 
525  retval = esirisc_flash_ref_erase(bank);
526 
527  command_print(CMD, "erase reference cell %s",
528  (retval == ERROR_OK) ? "successful" : "failed");
529 
530  return retval;
531 }
532 
534  {
535  .name = "mass_erase",
536  .handler = handle_esirisc_flash_mass_erase_command,
537  .mode = COMMAND_EXEC,
538  .help = "erase all pages in data memory",
539  .usage = "bank_id",
540  },
541  {
542  .name = "ref_erase",
543  .handler = handle_esirisc_flash_ref_erase_command,
544  .mode = COMMAND_EXEC,
545  .help = "erase reference cell (uncommon)",
546  .usage = "bank_id",
547  },
549 };
550 
552  {
553  .name = "flash",
554  .mode = COMMAND_EXEC,
555  .help = "eSi-TSMC Flash command group",
556  .usage = "",
558  },
560 };
561 
562 const struct flash_driver esirisc_flash = {
563  .name = "esirisc",
564  .usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
565  "cfg_address clock_hz wait_states",
566  .flash_bank_command = esirisc_flash_bank_command,
567  .erase = esirisc_flash_erase,
568  .write = esirisc_flash_write,
569  .read = default_flash_read,
570  .probe = esirisc_flash_probe,
571  .auto_probe = esirisc_flash_auto_probe,
572  .erase_check = default_flash_blank_check,
573  .info = esirisc_flash_info,
574  .free_driver_priv = default_flash_free_driver_priv,
575 };
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:450
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:117
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:145
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
static int register_commands(struct command_context *cmd_ctx, const char *cmd_prefix, const struct command_registration *cmds)
Register one or more commands in the specified context, as children of parent (or top-level commends,...
Definition: command.h:268
@ COMMAND_EXEC
Definition: command.h:40
uint8_t bank
Definition: esirisc.c:135
static struct esirisc_common * target_to_esirisc(struct target *target)
Definition: esirisc.h:109
#define TIMING2_H(x)
Definition: esirisc_flash.c:51
#define TERASE
Definition: esirisc_flash.c:78
static const struct command_registration esirisc_flash_exec_command_handlers[]
static int esirisc_flash_unlock(struct flash_bank *bank)
static int esirisc_flash_enable_protect(struct flash_bank *bank)
#define UNLOCK2
Definition: esirisc_flash.c:28
#define ADDRESS
Definition: esirisc_flash.c:29
#define STATUS_WER
Definition: esirisc_flash.c:56
static int esirisc_flash_clear_status(struct flash_bank *bank)
static const struct command_registration esirisc_flash_command_handlers[]
Definition: esirisc_flash.c:96
#define TIMING2
Definition: esirisc_flash.c:26
static int esirisc_flash_check_status(struct flash_bank *bank)
FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command)
Definition: esirisc_flash.c:98
#define FLASH_PAGE_SIZE
Definition: esirisc_flash.c:84
#define TIMING1
Definition: esirisc_flash.c:25
#define CONTROL
Definition: esirisc_flash.c:23
#define STATUS
Definition: esirisc_flash.c:32
static int esirisc_flash_wait(struct flash_bank *bank, int ms)
#define CONTROL_P
Definition: esirisc_flash.c:41
#define TIMING1_E(x)
Definition: esirisc_flash.c:49
#define TPROG
Definition: esirisc_flash.c:80
#define CONTROL_WP
Definition: esirisc_flash.c:38
#define TIMING0
Definition: esirisc_flash.c:24
static int esirisc_flash_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int esirisc_flash_info(struct flash_bank *bank, struct command_invocation *cmd)
static int esirisc_flash_fill_pb(struct flash_bank *bank, const uint8_t *buffer, uint32_t count)
#define CONTROL_TIMEOUT
Definition: esirisc_flash.c:83
COMMAND_HANDLER(handle_esirisc_flash_mass_erase_command)
#define TIMING0_F(x)
Definition: esirisc_flash.c:48
#define PB_MAX
Definition: esirisc_flash.c:85
static int esirisc_flash_ref_erase(struct flash_bank *bank)
#define TNVH
Definition: esirisc_flash.c:76
#define CONTROL_ERC
Definition: esirisc_flash.c:42
#define UNLOCK1
Definition: esirisc_flash.c:27
static int esirisc_flash_disable_protect(struct flash_bank *bank)
#define TIMING2_P(x)
Definition: esirisc_flash.c:50
#define CONTROL_EP
Definition: esirisc_flash.c:40
#define CONTROL_E
Definition: esirisc_flash.c:39
#define STATUS_BUSY
Definition: esirisc_flash.c:55
#define TIMING0_R(x)
Definition: esirisc_flash.c:47
static int esirisc_flash_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
#define PB_INDEX
Definition: esirisc_flash.c:31
static int esirisc_flash_probe(struct flash_bank *bank)
static int esirisc_flash_recall(struct flash_bank *bank)
static int esirisc_flash_init(struct flash_bank *bank)
#define PB_DATA
Definition: esirisc_flash.c:30
#define CONTROL_R
Definition: esirisc_flash.c:43
const struct flash_driver esirisc_flash
static uint32_t esirisc_flash_num_cycles(struct flash_bank *bank, uint64_t ns)
static int esirisc_flash_mass_erase(struct flash_bank *bank)
#define TIMING2_T(x)
Definition: esirisc_flash.c:52
static int esirisc_flash_control(struct flash_bank *bank, uint32_t control)
static int esirisc_flash_auto_probe(struct flash_bank *bank)
#define NUM_NS_PER_S
Definition: esirisc_flash.c:87
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void keep_alive(void)
Definition: log.c:419
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
#define MIN(a, b)
Definition: replacements.h:22
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:229
int num_bits
Definition: esirisc.h:78
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Definition: target.h:120
enum target_state state
Definition: target.h:162
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2408
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2616
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:792
@ TARGET_HALTED
Definition: target.h:55
#define ERROR_TARGET_TIMEOUT
Definition: target.h:791
int64_t timeval_ms(void)
#define DIV_ROUND_UP(m, n)
Rounds m up to the nearest multiple of n using division.
Definition: types.h:79
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22