OpenOCD
at91sam4.c
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2 
3 /*
4  * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5  *
6  * at91sam3s* support
7  * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8  *
9  * at91sam3x* & at91sam4 support
10  * Copyright (C) 2011 by Olivier Schonken, Jim Norris
11  *
12  * Some of the lower level code was based on code supplied by
13  * ATMEL under BSD-Source-Code License and this copyright.
14  * ATMEL Microcontroller Software Support
15  * Copyright (c) 2009, Atmel Corporation. All rights reserved.
16  */
17 
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21 
22 #include "imp.h"
23 #include <helper/time_support.h>
24 
25 #define REG_NAME_WIDTH (12)
26 
27 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
28 #define FLASH_BANK_BASE_S 0x00400000
29 #define FLASH_BANK_BASE_C 0x01000000
30 
31 /* at91sam4sd series (two one flash banks), first bank address */
32 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
33 /* at91sam4sd16x, second bank address */
34 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
35 /* at91sam4sd32x, second bank address */
36 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
37 
38 /* at91sam4c32x, first and second bank address */
39 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
40 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
41 
42 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
43 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
44 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
45 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
46 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
47 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
48 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
49 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
50 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
51 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
52 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
53 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
54 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
55 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
56 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
57 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
58 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
59 
60 #define OFFSET_EFC_FMR 0
61 #define OFFSET_EFC_FCR 4
62 #define OFFSET_EFC_FSR 8
63 #define OFFSET_EFC_FRR 12
64 
65 extern const struct flash_driver at91sam4_flash;
66 
67 static float _tomhz(uint32_t freq_hz)
68 {
69  float f;
70 
71  f = ((float)(freq_hz)) / 1000000.0;
72  return f;
73 }
74 
75 /* How the chip is configured. */
76 struct sam4_cfg {
77  uint32_t unique_id[4];
78 
79  uint32_t slow_freq;
80  uint32_t rc_freq;
81  uint32_t mainosc_freq;
82  uint32_t plla_freq;
83  uint32_t mclk_freq;
84  uint32_t cpu_freq;
85  uint32_t fclk_freq;
86  uint32_t pclk0_freq;
87  uint32_t pclk1_freq;
88  uint32_t pclk2_freq;
89 
90 
91 #define SAM4_CHIPID_CIDR (0x400E0740)
92  uint32_t CHIPID_CIDR;
93 #define SAM4_CHIPID_EXID (0x400E0744)
94  uint32_t CHIPID_EXID;
95 
96 #define SAM4_PMC_BASE (0x400E0400)
97 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
98  uint32_t PMC_SCSR;
99 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
100  uint32_t PMC_PCSR;
101 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
102  uint32_t CKGR_UCKR;
103 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
104  uint32_t CKGR_MOR;
105 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
106  uint32_t CKGR_MCFR;
107 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
108  uint32_t CKGR_PLLAR;
109 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
110  uint32_t PMC_MCKR;
111 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
112  uint32_t PMC_PCK0;
113 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
114  uint32_t PMC_PCK1;
115 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
116  uint32_t PMC_PCK2;
117 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
118  uint32_t PMC_SR;
119 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
120  uint32_t PMC_IMR;
121 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
122  uint32_t PMC_FSMR;
123 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
124  uint32_t PMC_FSPR;
125 };
126 
127 struct sam4_bank_private {
128  bool probed;
129  /* DANGER: THERE ARE DRAGONS HERE.. */
130  /* NOTE: If you add more 'ghost' pointers */
131  /* be aware that you must *manually* update */
132  /* these pointers in the function sam4_get_details() */
133  /* See the comment "Here there be dragons" */
134 
135  /* so we can find the chip we belong to */
136  struct sam4_chip *chip;
137  /* so we can find the original bank pointer */
138  struct flash_bank *bank;
139  unsigned bank_number;
140  uint32_t controller_address;
141  uint32_t base_address;
142  uint32_t flash_wait_states;
143  bool present;
144  unsigned size_bytes;
145  unsigned nsectors;
146  unsigned sector_size;
147  unsigned page_size;
148 };
149 
150 struct sam4_chip_details {
151  /* THERE ARE DRAGONS HERE.. */
152  /* note: If you add pointers here */
153  /* be careful about them as they */
154  /* may need to be updated inside */
155  /* the function: "sam4_get_details() */
156  /* which copy/overwrites the */
157  /* 'runtime' copy of this structure */
158  uint32_t chipid_cidr;
159  const char *name;
160 
161  unsigned n_gpnvms;
162 #define SAM4_N_NVM_BITS 3
163  unsigned gpnvm[SAM4_N_NVM_BITS];
164  unsigned total_flash_size;
165  unsigned total_sram_size;
166  unsigned n_banks;
167 #define SAM4_MAX_FLASH_BANKS 2
168  /* these are "initialized" from the global const data */
169  struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
170 };
171 
172 struct sam4_chip {
173  struct sam4_chip *next;
174  bool probed;
175 
176  /* this is "initialized" from the global const structure */
177  struct sam4_chip_details details;
178  struct target *target;
179  struct sam4_cfg cfg;
180 };
181 
182 
183 struct sam4_reg_list {
184  uint32_t address; size_t struct_offset; const char *name;
185  void (*explain_func)(struct sam4_chip *chip);
186 };
187 
188 static struct sam4_chip *all_sam4_chips;
189 
190 static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
191 {
192  struct target *t;
193  static struct sam4_chip *p;
194 
195  t = get_current_target(cmd->ctx);
196  if (!t) {
197  command_print_sameline(cmd, "No current target?\n");
198  return NULL;
199  }
200 
201  p = all_sam4_chips;
202  if (!p) {
203  /* this should not happen */
204  /* the command is not registered until the chip is created? */
205  command_print_sameline(cmd, "No SAM4 chips exist?\n");
206  return NULL;
207  }
208 
209  while (p) {
210  if (p->target == t)
211  return p;
212  p = p->next;
213  }
214  command_print_sameline(cmd, "Cannot find SAM4 chip?\n");
215  return NULL;
216 }
217 
218 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
219 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
220 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
221 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
222 
223 /* these are used to *initialize* the "chip->details" structure. */
224 static const struct sam4_chip_details all_sam4_details[] = {
225  /* Start at91sam4c* series */
226  /* at91sam4c32e - LQFP144 */
227  {
228  .chipid_cidr = 0xA66D0EE0,
229  .name = "at91sam4c32e",
230  .total_flash_size = 2024 * 1024,
231  .total_sram_size = 256 * 1024,
232  .n_gpnvms = 3,
233  .n_banks = 2,
234 /* .bank[0] = { */
235  {
236  {
237  .probed = false,
238  .chip = NULL,
239  .bank = NULL,
240  .bank_number = 0,
241  .base_address = FLASH_BANK0_BASE_C32,
242  .controller_address = 0x400e0a00,
243  .flash_wait_states = 5,
244  .present = true,
245  .size_bytes = 1024 * 1024,
246  .nsectors = 128,
247  .sector_size = 8192,
248  .page_size = 512,
249  },
250 /* .bank[1] = { */
251  {
252  .probed = false,
253  .chip = NULL,
254  .bank = NULL,
255  .bank_number = 1,
256  .base_address = FLASH_BANK1_BASE_C32,
257  .controller_address = 0x400e0c00,
258  .flash_wait_states = 5,
259  .present = true,
260  .size_bytes = 1024 * 1024,
261  .nsectors = 128,
262  .sector_size = 8192,
263  .page_size = 512,
264  },
265  },
266  },
267  /* at91sam4c32c - LQFP100 */
268  {
269  .chipid_cidr = 0xA64D0EE0,
270  .name = "at91sam4c32c",
271  .total_flash_size = 2024 * 1024,
272  .total_sram_size = 256 * 1024,
273  .n_gpnvms = 3,
274  .n_banks = 2,
275 /* .bank[0] = { */
276  {
277  {
278  .probed = false,
279  .chip = NULL,
280  .bank = NULL,
281  .bank_number = 0,
282  .base_address = FLASH_BANK0_BASE_C32,
283  .controller_address = 0x400e0a00,
284  .flash_wait_states = 5,
285  .present = true,
286  .size_bytes = 1024 * 1024,
287  .nsectors = 128,
288  .sector_size = 8192,
289  .page_size = 512,
290  },
291 /* .bank[1] = { */
292  {
293  .probed = false,
294  .chip = NULL,
295  .bank = NULL,
296  .bank_number = 1,
297  .base_address = FLASH_BANK1_BASE_C32,
298  .controller_address = 0x400e0c00,
299  .flash_wait_states = 5,
300  .present = true,
301  .size_bytes = 1024 * 1024,
302  .nsectors = 128,
303  .sector_size = 8192,
304  .page_size = 512,
305  },
306  },
307  },
308  /* at91sam4c16c - LQFP100 */
309  {
310  .chipid_cidr = 0xA64C0CE0,
311  .name = "at91sam4c16c",
312  .total_flash_size = 1024 * 1024,
313  .total_sram_size = 128 * 1024,
314  .n_gpnvms = 2,
315  .n_banks = 1,
316  {
317 /* .bank[0] = {*/
318  {
319  .probed = false,
320  .chip = NULL,
321  .bank = NULL,
322  .bank_number = 0,
323  .base_address = FLASH_BANK_BASE_C,
324  .controller_address = 0x400e0a00,
325  .flash_wait_states = 5,
326  .present = true,
327  .size_bytes = 1024 * 1024,
328  .nsectors = 128,
329  .sector_size = 8192,
330  .page_size = 512,
331  },
332 /* .bank[1] = {*/
333  {
334  .present = false,
335  .probed = false,
336  .bank_number = 1,
337 
338  },
339  },
340  },
341  /* at91sam4c8c - LQFP100 */
342  {
343  .chipid_cidr = 0xA64C0AE0,
344  .name = "at91sam4c8c",
345  .total_flash_size = 512 * 1024,
346  .total_sram_size = 128 * 1024,
347  .n_gpnvms = 2,
348  .n_banks = 1,
349  {
350 /* .bank[0] = {*/
351  {
352  .probed = false,
353  .chip = NULL,
354  .bank = NULL,
355  .bank_number = 0,
356  .base_address = FLASH_BANK_BASE_C,
357  .controller_address = 0x400e0a00,
358  .flash_wait_states = 5,
359  .present = true,
360  .size_bytes = 512 * 1024,
361  .nsectors = 64,
362  .sector_size = 8192,
363  .page_size = 512,
364  },
365 /* .bank[1] = {*/
366  {
367  .present = false,
368  .probed = false,
369  .bank_number = 1,
370 
371  },
372  },
373  },
374  /* at91sam4c4c (rev B) - LQFP100 */
375  {
376  .chipid_cidr = 0xA64C0CE5,
377  .name = "at91sam4c4c",
378  .total_flash_size = 256 * 1024,
379  .total_sram_size = 128 * 1024,
380  .n_gpnvms = 2,
381  .n_banks = 1,
382  {
383 /* .bank[0] = {*/
384  {
385  .probed = false,
386  .chip = NULL,
387  .bank = NULL,
388  .bank_number = 0,
389  .base_address = FLASH_BANK_BASE_C,
390  .controller_address = 0x400e0a00,
391  .flash_wait_states = 5,
392  .present = true,
393  .size_bytes = 256 * 1024,
394  .nsectors = 32,
395  .sector_size = 8192,
396  .page_size = 512,
397  },
398 /* .bank[1] = {*/
399  {
400  .present = false,
401  .probed = false,
402  .bank_number = 1,
403 
404  },
405  },
406  },
407 
408  /* Start at91sam4e* series */
409  /*atsam4e16e - LQFP144/LFBGA144*/
410  {
411  .chipid_cidr = 0xA3CC0CE0,
412  .name = "at91sam4e16e",
413  .total_flash_size = 1024 * 1024,
414  .total_sram_size = 128 * 1024,
415  .n_gpnvms = 2,
416  .n_banks = 1,
417  {
418 /* .bank[0] = {*/
419  {
420  .probed = false,
421  .chip = NULL,
422  .bank = NULL,
423  .bank_number = 0,
424  .base_address = FLASH_BANK_BASE_S,
425  .controller_address = 0x400e0a00,
426  .flash_wait_states = 5,
427  .present = true,
428  .size_bytes = 1024 * 1024,
429  .nsectors = 128,
430  .sector_size = 8192,
431  .page_size = 512,
432  },
433 /* .bank[1] = {*/
434  {
435  .present = false,
436  .probed = false,
437  .bank_number = 1,
438 
439  },
440  },
441  },
442 
443  /* Start at91sam4n* series */
444  /*atsam4n8a - LQFP48/QFN48*/
445  {
446  .chipid_cidr = 0x293B0AE0,
447  .name = "at91sam4n8a",
448  .total_flash_size = 512 * 1024,
449  .total_sram_size = 64 * 1024,
450  .n_gpnvms = 2,
451  .n_banks = 1,
452  {
453 /* .bank[0] = {*/
454  {
455  .probed = false,
456  .chip = NULL,
457  .bank = NULL,
458  .bank_number = 0,
459  .base_address = FLASH_BANK_BASE_S,
460  .controller_address = 0x400e0a00,
461  .flash_wait_states = 5,
462  .present = true,
463  .size_bytes = 512 * 1024,
464  .nsectors = 64,
465  .sector_size = 8192,
466  .page_size = 512,
467  },
468 /* .bank[1] = {*/
469  {
470  .present = false,
471  .probed = false,
472  .bank_number = 1,
473 
474  },
475  },
476  },
477  /*atsam4n8b - LQFP64/QFN64*/
478  {
479  .chipid_cidr = 0x294B0AE0,
480  .name = "at91sam4n8b",
481  .total_flash_size = 512 * 1024,
482  .total_sram_size = 64 * 1024,
483  .n_gpnvms = 2,
484  .n_banks = 1,
485  {
486 /* .bank[0] = {*/
487  {
488  .probed = false,
489  .chip = NULL,
490  .bank = NULL,
491  .bank_number = 0,
492  .base_address = FLASH_BANK_BASE_S,
493  .controller_address = 0x400e0a00,
494  .flash_wait_states = 5,
495  .present = true,
496  .size_bytes = 512 * 1024,
497  .nsectors = 64,
498  .sector_size = 8192,
499  .page_size = 512,
500  },
501 /* .bank[1] = {*/
502  {
503  .present = false,
504  .probed = false,
505  .bank_number = 1,
506 
507  },
508  },
509  },
510  /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
511  {
512  .chipid_cidr = 0x295B0AE0,
513  .name = "at91sam4n8c",
514  .total_flash_size = 512 * 1024,
515  .total_sram_size = 64 * 1024,
516  .n_gpnvms = 2,
517  .n_banks = 1,
518  {
519 /* .bank[0] = {*/
520  {
521  .probed = false,
522  .chip = NULL,
523  .bank = NULL,
524  .bank_number = 0,
525  .base_address = FLASH_BANK_BASE_S,
526  .controller_address = 0x400e0a00,
527  .flash_wait_states = 5,
528  .present = true,
529  .size_bytes = 512 * 1024,
530  .nsectors = 64,
531  .sector_size = 8192,
532  .page_size = 512,
533  },
534 /* .bank[1] = {*/
535  {
536  .present = false,
537  .probed = false,
538  .bank_number = 1,
539 
540  },
541  },
542  },
543  /*atsam4n16b - LQFP64/QFN64*/
544  {
545  .chipid_cidr = 0x29460CE0,
546  .name = "at91sam4n16b",
547  .total_flash_size = 1024 * 1024,
548  .total_sram_size = 80 * 1024,
549  .n_gpnvms = 2,
550  .n_banks = 1,
551  {
552 /* .bank[0] = {*/
553  {
554  .probed = false,
555  .chip = NULL,
556  .bank = NULL,
557  .bank_number = 0,
558  .base_address = FLASH_BANK_BASE_S,
559  .controller_address = 0x400e0a00,
560  .flash_wait_states = 5,
561  .present = true,
562  .size_bytes = 1024 * 1024,
563  .nsectors = 128,
564  .sector_size = 8192,
565  .page_size = 512,
566  },
567 /* .bank[1] = {*/
568  {
569  .present = false,
570  .probed = false,
571  .bank_number = 1,
572 
573  },
574  },
575  },
576  /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
577  {
578  .chipid_cidr = 0x29560CE0,
579  .name = "at91sam4n16c",
580  .total_flash_size = 1024 * 1024,
581  .total_sram_size = 80 * 1024,
582  .n_gpnvms = 2,
583  .n_banks = 1,
584  {
585 /* .bank[0] = {*/
586  {
587  .probed = false,
588  .chip = NULL,
589  .bank = NULL,
590  .bank_number = 0,
591  .base_address = FLASH_BANK_BASE_S,
592  .controller_address = 0x400e0a00,
593  .flash_wait_states = 5,
594  .present = true,
595  .size_bytes = 1024 * 1024,
596  .nsectors = 128,
597  .sector_size = 8192,
598  .page_size = 512,
599  },
600 /* .bank[1] = {*/
601  {
602  .present = false,
603  .probed = false,
604  .bank_number = 1,
605 
606  },
607  },
608  },
609 
610  /* Start at91sam4s* series */
611  /*atsam4s16c - LQFP100/BGA100*/
612  {
613  .chipid_cidr = 0x28AC0CE0,
614  .name = "at91sam4s16c",
615  .total_flash_size = 1024 * 1024,
616  .total_sram_size = 128 * 1024,
617  .n_gpnvms = 2,
618  .n_banks = 1,
619  {
620 /* .bank[0] = {*/
621  {
622  .probed = false,
623  .chip = NULL,
624  .bank = NULL,
625  .bank_number = 0,
626  .base_address = FLASH_BANK_BASE_S,
627  .controller_address = 0x400e0a00,
628  .flash_wait_states = 5,
629  .present = true,
630  .size_bytes = 1024 * 1024,
631  .nsectors = 128,
632  .sector_size = 8192,
633  .page_size = 512,
634  },
635 /* .bank[1] = {*/
636  {
637  .present = false,
638  .probed = false,
639  .bank_number = 1,
640 
641  },
642  },
643  },
644  /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
645  {
646  .chipid_cidr = 0x28a70ce0,
647  .name = "at91sam4sa16c",
648  .total_flash_size = 1024 * 1024,
649  .total_sram_size = 160 * 1024,
650  .n_gpnvms = 2,
651  .n_banks = 1,
652 
653 /* .bank[0] = { */
654  {
655  {
656  .probed = false,
657  .chip = NULL,
658  .bank = NULL,
659  .bank_number = 0,
660  .base_address = FLASH_BANK_BASE_S,
661  .controller_address = 0x400e0a00,
662  .flash_wait_states = 5,
663  .present = true,
664  .size_bytes = 1024 * 1024,
665  .nsectors = 128,
666  .sector_size = 8192,
667  .page_size = 512,
668  },
669 /* .bank[1] = {*/
670  {
671  .present = false,
672  .probed = false,
673  .bank_number = 1,
674 
675  },
676  },
677  },
678  /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
679  {
680  .chipid_cidr = 0x289C0CE0,
681  .name = "at91sam4s16b",
682  .total_flash_size = 1024 * 1024,
683  .total_sram_size = 128 * 1024,
684  .n_gpnvms = 2,
685  .n_banks = 1,
686  {
687 /* .bank[0] = {*/
688  {
689  .probed = false,
690  .chip = NULL,
691  .bank = NULL,
692  .bank_number = 0,
693  .base_address = FLASH_BANK_BASE_S,
694  .controller_address = 0x400e0a00,
695  .flash_wait_states = 5,
696  .present = true,
697  .size_bytes = 1024 * 1024,
698  .nsectors = 128,
699  .sector_size = 8192,
700  .page_size = 512,
701  },
702 /* .bank[1] = {*/
703  {
704  .present = false,
705  .probed = false,
706  .bank_number = 1,
707 
708  },
709  },
710  },
711  /*atsam4sa16b - LQFP64/QFN64*/
712  {
713  .chipid_cidr = 0x28970CE0,
714  .name = "at91sam4sa16b",
715  .total_flash_size = 1024 * 1024,
716  .total_sram_size = 160 * 1024,
717  .n_gpnvms = 2,
718  .n_banks = 1,
719  {
720 /* .bank[0] = {*/
721  {
722  .probed = false,
723  .chip = NULL,
724  .bank = NULL,
725  .bank_number = 0,
726  .base_address = FLASH_BANK_BASE_S,
727  .controller_address = 0x400e0a00,
728  .flash_wait_states = 5,
729  .present = true,
730  .size_bytes = 1024 * 1024,
731  .nsectors = 128,
732  .sector_size = 8192,
733  .page_size = 512,
734  },
735 /* .bank[1] = {*/
736  {
737  .present = false,
738  .probed = false,
739  .bank_number = 1,
740 
741  },
742  },
743  },
744  /*atsam4s16a - LQFP48/QFN48*/
745  {
746  .chipid_cidr = 0x288C0CE0,
747  .name = "at91sam4s16a",
748  .total_flash_size = 1024 * 1024,
749  .total_sram_size = 128 * 1024,
750  .n_gpnvms = 2,
751  .n_banks = 1,
752  {
753 /* .bank[0] = {*/
754  {
755  .probed = false,
756  .chip = NULL,
757  .bank = NULL,
758  .bank_number = 0,
759  .base_address = FLASH_BANK_BASE_S,
760  .controller_address = 0x400e0a00,
761  .flash_wait_states = 5,
762  .present = true,
763  .size_bytes = 1024 * 1024,
764  .nsectors = 128,
765  .sector_size = 8192,
766  .page_size = 512,
767  },
768 /* .bank[1] = {*/
769  {
770  .present = false,
771  .probed = false,
772  .bank_number = 1,
773 
774  },
775  },
776  },
777  /*atsam4s8c - LQFP100/BGA100*/
778  {
779  .chipid_cidr = 0x28AC0AE0,
780  .name = "at91sam4s8c",
781  .total_flash_size = 512 * 1024,
782  .total_sram_size = 128 * 1024,
783  .n_gpnvms = 2,
784  .n_banks = 1,
785  {
786 /* .bank[0] = {*/
787  {
788  .probed = false,
789  .chip = NULL,
790  .bank = NULL,
791  .bank_number = 0,
792  .base_address = FLASH_BANK_BASE_S,
793  .controller_address = 0x400e0a00,
794  .flash_wait_states = 5,
795  .present = true,
796  .size_bytes = 512 * 1024,
797  .nsectors = 64,
798  .sector_size = 8192,
799  .page_size = 512,
800  },
801 /* .bank[1] = {*/
802  {
803  .present = false,
804  .probed = false,
805  .bank_number = 1,
806 
807  },
808  },
809  },
810  /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
811  {
812  .chipid_cidr = 0x289C0AE0,
813  .name = "at91sam4s8b",
814  .total_flash_size = 512 * 1024,
815  .total_sram_size = 128 * 1024,
816  .n_gpnvms = 2,
817  .n_banks = 1,
818  {
819 /* .bank[0] = {*/
820  {
821  .probed = false,
822  .chip = NULL,
823  .bank = NULL,
824  .bank_number = 0,
825  .base_address = FLASH_BANK_BASE_S,
826  .controller_address = 0x400e0a00,
827  .flash_wait_states = 5,
828  .present = true,
829  .size_bytes = 512 * 1024,
830  .nsectors = 64,
831  .sector_size = 8192,
832  .page_size = 512,
833  },
834 /* .bank[1] = {*/
835  {
836  .present = false,
837  .probed = false,
838  .bank_number = 1,
839 
840  },
841  },
842  },
843  /*atsam4s8a - LQFP48/BGA48*/
844  {
845  .chipid_cidr = 0x288C0AE0,
846  .name = "at91sam4s8a",
847  .total_flash_size = 512 * 1024,
848  .total_sram_size = 128 * 1024,
849  .n_gpnvms = 2,
850  .n_banks = 1,
851  {
852 /* .bank[0] = {*/
853  {
854  .probed = false,
855  .chip = NULL,
856  .bank = NULL,
857  .bank_number = 0,
858  .base_address = FLASH_BANK_BASE_S,
859  .controller_address = 0x400e0a00,
860  .flash_wait_states = 5,
861  .present = true,
862  .size_bytes = 512 * 1024,
863  .nsectors = 64,
864  .sector_size = 8192,
865  .page_size = 512,
866  },
867 /* .bank[1] = {*/
868  {
869  .present = false,
870  .probed = false,
871  .bank_number = 1,
872 
873  },
874  },
875  },
876 
877  /*atsam4s4c - LQFP100/BGA100*/
878  {
879  .chipid_cidr = 0x28ab09e0,
880  .name = "at91sam4s4c",
881  .total_flash_size = 256 * 1024,
882  .total_sram_size = 64 * 1024,
883  .n_gpnvms = 2,
884  .n_banks = 1,
885  {
886 /* .bank[0] = {*/
887  {
888  .probed = false,
889  .chip = NULL,
890  .bank = NULL,
891  .bank_number = 0,
892  .base_address = FLASH_BANK_BASE_S,
893  .controller_address = 0x400e0a00,
894  .flash_wait_states = 5,
895  .present = true,
896  .size_bytes = 256 * 1024,
897  .nsectors = 32,
898  .sector_size = 8192,
899  .page_size = 512,
900  },
901 /* .bank[1] = {*/
902  {
903  .present = false,
904  .probed = false,
905  .bank_number = 1,
906 
907  },
908  },
909  },
910 
911  /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
912  {
913  .chipid_cidr = 0x289b09e0,
914  .name = "at91sam4s4b",
915  .total_flash_size = 256 * 1024,
916  .total_sram_size = 64 * 1024,
917  .n_gpnvms = 2,
918  .n_banks = 1,
919  {
920 /* .bank[0] = {*/
921  {
922  .probed = false,
923  .chip = NULL,
924  .bank = NULL,
925  .bank_number = 0,
926  .base_address = FLASH_BANK_BASE_S,
927  .controller_address = 0x400e0a00,
928  .flash_wait_states = 5,
929  .present = true,
930  .size_bytes = 256 * 1024,
931  .nsectors = 32,
932  .sector_size = 8192,
933  .page_size = 512,
934  },
935 /* .bank[1] = {*/
936  {
937  .present = false,
938  .probed = false,
939  .bank_number = 1,
940 
941  },
942  },
943  },
944 
945  /*atsam4s4a - LQFP48/QFN48*/
946  {
947  .chipid_cidr = 0x288b09e0,
948  .name = "at91sam4s4a",
949  .total_flash_size = 256 * 1024,
950  .total_sram_size = 64 * 1024,
951  .n_gpnvms = 2,
952  .n_banks = 1,
953  {
954 /* .bank[0] = {*/
955  {
956  .probed = false,
957  .chip = NULL,
958  .bank = NULL,
959  .bank_number = 0,
960  .base_address = FLASH_BANK_BASE_S,
961  .controller_address = 0x400e0a00,
962  .flash_wait_states = 5,
963  .present = true,
964  .size_bytes = 256 * 1024,
965  .nsectors = 32,
966  .sector_size = 8192,
967  .page_size = 512,
968  },
969 /* .bank[1] = {*/
970  {
971  .present = false,
972  .probed = false,
973  .bank_number = 1,
974 
975  },
976  },
977  },
978 
979  /*atsam4s2c - LQFP100/BGA100*/
980  {
981  .chipid_cidr = 0x28ab07e0,
982  .name = "at91sam4s2c",
983  .total_flash_size = 128 * 1024,
984  .total_sram_size = 64 * 1024,
985  .n_gpnvms = 2,
986  .n_banks = 1,
987  {
988 /* .bank[0] = {*/
989  {
990  .probed = false,
991  .chip = NULL,
992  .bank = NULL,
993  .bank_number = 0,
994  .base_address = FLASH_BANK_BASE_S,
995  .controller_address = 0x400e0a00,
996  .flash_wait_states = 5,
997  .present = true,
998  .size_bytes = 128 * 1024,
999  .nsectors = 16,
1000  .sector_size = 8192,
1001  .page_size = 512,
1002  },
1003 /* .bank[1] = {*/
1004  {
1005  .present = false,
1006  .probed = false,
1007  .bank_number = 1,
1008 
1009  },
1010  },
1011  },
1012 
1013  /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1014  {
1015  .chipid_cidr = 0x289b07e0,
1016  .name = "at91sam4s2b",
1017  .total_flash_size = 128 * 1024,
1018  .total_sram_size = 64 * 1024,
1019  .n_gpnvms = 2,
1020  .n_banks = 1,
1021  {
1022 /* .bank[0] = {*/
1023  {
1024  .probed = false,
1025  .chip = NULL,
1026  .bank = NULL,
1027  .bank_number = 0,
1028  .base_address = FLASH_BANK_BASE_S,
1029  .controller_address = 0x400e0a00,
1030  .flash_wait_states = 5,
1031  .present = true,
1032  .size_bytes = 128 * 1024,
1033  .nsectors = 16,
1034  .sector_size = 8192,
1035  .page_size = 512,
1036  },
1037 /* .bank[1] = {*/
1038  {
1039  .present = false,
1040  .probed = false,
1041  .bank_number = 1,
1042 
1043  },
1044  },
1045  },
1046 
1047  /*atsam4s2a - LQFP48/QFN48*/
1048  {
1049  .chipid_cidr = 0x288b07e0,
1050  .name = "at91sam4s2a",
1051  .total_flash_size = 128 * 1024,
1052  .total_sram_size = 64 * 1024,
1053  .n_gpnvms = 2,
1054  .n_banks = 1,
1055  {
1056 /* .bank[0] = {*/
1057  {
1058  .probed = false,
1059  .chip = NULL,
1060  .bank = NULL,
1061  .bank_number = 0,
1062  .base_address = FLASH_BANK_BASE_S,
1063  .controller_address = 0x400e0a00,
1064  .flash_wait_states = 5,
1065  .present = true,
1066  .size_bytes = 128 * 1024,
1067  .nsectors = 16,
1068  .sector_size = 8192,
1069  .page_size = 512,
1070  },
1071 /* .bank[1] = {*/
1072  {
1073  .present = false,
1074  .probed = false,
1075  .bank_number = 1,
1076 
1077  },
1078  },
1079  },
1080 
1081  /*at91sam4sd32c - LQFP100/BGA100*/
1082  {
1083  .chipid_cidr = 0x29a70ee0,
1084  .name = "at91sam4sd32c",
1085  .total_flash_size = 2048 * 1024,
1086  .total_sram_size = 160 * 1024,
1087  .n_gpnvms = 3,
1088  .n_banks = 2,
1089 
1090 /* .bank[0] = { */
1091  {
1092  {
1093  .probed = false,
1094  .chip = NULL,
1095  .bank = NULL,
1096  .bank_number = 0,
1097  .base_address = FLASH_BANK0_BASE_SD,
1098  .controller_address = 0x400e0a00,
1099  .flash_wait_states = 5,
1100  .present = true,
1101  .size_bytes = 1024 * 1024,
1102  .nsectors = 128,
1103  .sector_size = 8192,
1104  .page_size = 512,
1105  },
1106 
1107 /* .bank[1] = { */
1108  {
1109  .probed = false,
1110  .chip = NULL,
1111  .bank = NULL,
1112  .bank_number = 1,
1113  .base_address = FLASH_BANK1_BASE_2048K_SD,
1114  .controller_address = 0x400e0c00,
1115  .flash_wait_states = 5,
1116  .present = true,
1117  .size_bytes = 1024 * 1024,
1118  .nsectors = 128,
1119  .sector_size = 8192,
1120  .page_size = 512,
1121  },
1122  },
1123  },
1124 
1125  /*at91sam4sd32b - LQFP64/BGA64*/
1126  {
1127  .chipid_cidr = 0x29970ee0,
1128  .name = "at91sam4sd32b",
1129  .total_flash_size = 2048 * 1024,
1130  .total_sram_size = 160 * 1024,
1131  .n_gpnvms = 3,
1132  .n_banks = 2,
1133 
1134 /* .bank[0] = { */
1135  {
1136  {
1137  .probed = false,
1138  .chip = NULL,
1139  .bank = NULL,
1140  .bank_number = 0,
1141  .base_address = FLASH_BANK0_BASE_SD,
1142  .controller_address = 0x400e0a00,
1143  .flash_wait_states = 5,
1144  .present = true,
1145  .size_bytes = 1024 * 1024,
1146  .nsectors = 128,
1147  .sector_size = 8192,
1148  .page_size = 512,
1149  },
1150 
1151 /* .bank[1] = { */
1152  {
1153  .probed = false,
1154  .chip = NULL,
1155  .bank = NULL,
1156  .bank_number = 1,
1157  .base_address = FLASH_BANK1_BASE_2048K_SD,
1158  .controller_address = 0x400e0c00,
1159  .flash_wait_states = 5,
1160  .present = true,
1161  .size_bytes = 1024 * 1024,
1162  .nsectors = 128,
1163  .sector_size = 8192,
1164  .page_size = 512,
1165  },
1166  },
1167  },
1168 
1169  /*at91sam4sd16c - LQFP100/BGA100*/
1170  {
1171  .chipid_cidr = 0x29a70ce0,
1172  .name = "at91sam4sd16c",
1173  .total_flash_size = 1024 * 1024,
1174  .total_sram_size = 160 * 1024,
1175  .n_gpnvms = 3,
1176  .n_banks = 2,
1177 
1178 /* .bank[0] = { */
1179  {
1180  {
1181  .probed = false,
1182  .chip = NULL,
1183  .bank = NULL,
1184  .bank_number = 0,
1185  .base_address = FLASH_BANK0_BASE_SD,
1186  .controller_address = 0x400e0a00,
1187  .flash_wait_states = 5,
1188  .present = true,
1189  .size_bytes = 512 * 1024,
1190  .nsectors = 64,
1191  .sector_size = 8192,
1192  .page_size = 512,
1193  },
1194 
1195 /* .bank[1] = { */
1196  {
1197  .probed = false,
1198  .chip = NULL,
1199  .bank = NULL,
1200  .bank_number = 1,
1201  .base_address = FLASH_BANK1_BASE_1024K_SD,
1202  .controller_address = 0x400e0c00,
1203  .flash_wait_states = 5,
1204  .present = true,
1205  .size_bytes = 512 * 1024,
1206  .nsectors = 64,
1207  .sector_size = 8192,
1208  .page_size = 512,
1209  },
1210  },
1211  },
1212 
1213  /*at91sam4sd16b - LQFP64/BGA64*/
1214  {
1215  .chipid_cidr = 0x29970ce0,
1216  .name = "at91sam4sd16b",
1217  .total_flash_size = 1024 * 1024,
1218  .total_sram_size = 160 * 1024,
1219  .n_gpnvms = 3,
1220  .n_banks = 2,
1221 
1222 /* .bank[0] = { */
1223  {
1224  {
1225  .probed = false,
1226  .chip = NULL,
1227  .bank = NULL,
1228  .bank_number = 0,
1229  .base_address = FLASH_BANK0_BASE_SD,
1230  .controller_address = 0x400e0a00,
1231  .flash_wait_states = 5,
1232  .present = true,
1233  .size_bytes = 512 * 1024,
1234  .nsectors = 64,
1235  .sector_size = 8192,
1236  .page_size = 512,
1237  },
1238 
1239 /* .bank[1] = { */
1240  {
1241  .probed = false,
1242  .chip = NULL,
1243  .bank = NULL,
1244  .bank_number = 1,
1245  .base_address = FLASH_BANK1_BASE_1024K_SD,
1246  .controller_address = 0x400e0c00,
1247  .flash_wait_states = 5,
1248  .present = true,
1249  .size_bytes = 512 * 1024,
1250  .nsectors = 64,
1251  .sector_size = 8192,
1252  .page_size = 512,
1253  },
1254  },
1255  },
1256 
1257  /* atsamg53n19 */
1258  {
1259  .chipid_cidr = 0x247e0ae0,
1260  .name = "atsamg53n19",
1261  .total_flash_size = 512 * 1024,
1262  .total_sram_size = 96 * 1024,
1263  .n_gpnvms = 2,
1264  .n_banks = 1,
1265 
1266 /* .bank[0] = {*/
1267  {
1268  {
1269  .probed = false,
1270  .chip = NULL,
1271  .bank = NULL,
1272  .bank_number = 0,
1273  .base_address = FLASH_BANK_BASE_S,
1274  .controller_address = 0x400e0a00,
1275  .flash_wait_states = 5,
1276  .present = true,
1277  .size_bytes = 512 * 1024,
1278  .nsectors = 64,
1279  .sector_size = 8192,
1280  .page_size = 512,
1281  },
1282 /* .bank[1] = {*/
1283  {
1284  .present = false,
1285  .probed = false,
1286  .bank_number = 1,
1287 
1288  },
1289  }
1290  },
1291 
1292  /* atsamg55g19 Rev.A */
1293  {
1294  .chipid_cidr = 0x24470ae0,
1295  .name = "atsamg55g19",
1296  .total_flash_size = 512 * 1024,
1297  .total_sram_size = 160 * 1024,
1298  .n_gpnvms = 2,
1299  .n_banks = 1,
1300 
1301  {
1302 /* .bank[0] = */
1303  {
1304  .probed = false,
1305  .chip = NULL,
1306  .bank = NULL,
1307  .bank_number = 0,
1308  .base_address = FLASH_BANK_BASE_S,
1309  .controller_address = 0x400e0a00,
1310  .flash_wait_states = 5,
1311  .present = true,
1312  .size_bytes = 512 * 1024,
1313  .nsectors = 64,
1314  .sector_size = 8192,
1315  .page_size = 512,
1316  },
1317 /* .bank[1] = */
1318  {
1319  .present = false,
1320  .probed = false,
1321  .bank_number = 1,
1322  },
1323  }
1324  },
1325 
1326  /* atsamg55g19 Rev.B */
1327  {
1328  .chipid_cidr = 0x24470ae1,
1329  .name = "atsamg55g19b",
1330  .total_flash_size = 512 * 1024,
1331  .total_sram_size = 160 * 1024,
1332  .n_gpnvms = 2,
1333  .n_banks = 1,
1334 
1335  {
1336 /* .bank[0] = */
1337  {
1338  .probed = false,
1339  .chip = NULL,
1340  .bank = NULL,
1341  .bank_number = 0,
1342  .base_address = FLASH_BANK_BASE_S,
1343  .controller_address = 0x400e0a00,
1344  .flash_wait_states = 5,
1345  .present = true,
1346  .size_bytes = 512 * 1024,
1347  .nsectors = 64,
1348  .sector_size = 8192,
1349  .page_size = 512,
1350  },
1351 /* .bank[1] = */
1352  {
1353  .present = false,
1354  .probed = false,
1355  .bank_number = 1,
1356  },
1357  }
1358  },
1359 
1360  /* atsamg55j19 Rev.A */
1361  {
1362  .chipid_cidr = 0x24570ae0,
1363  .name = "atsamg55j19",
1364  .total_flash_size = 512 * 1024,
1365  .total_sram_size = 160 * 1024,
1366  .n_gpnvms = 2,
1367  .n_banks = 1,
1368 
1369  {
1370 /* .bank[0] = */
1371  {
1372  .probed = false,
1373  .chip = NULL,
1374  .bank = NULL,
1375  .bank_number = 0,
1376  .base_address = FLASH_BANK_BASE_S,
1377  .controller_address = 0x400e0a00,
1378  .flash_wait_states = 5,
1379  .present = true,
1380  .size_bytes = 512 * 1024,
1381  .nsectors = 64,
1382  .sector_size = 8192,
1383  .page_size = 512,
1384  },
1385 /* .bank[1] = */
1386  {
1387  .present = false,
1388  .probed = false,
1389  .bank_number = 1,
1390  },
1391  }
1392  },
1393 
1394  /* atsamg55j19 Rev.B */
1395  {
1396  .chipid_cidr = 0x24570ae1,
1397  .name = "atsamg55j19b",
1398  .total_flash_size = 512 * 1024,
1399  .total_sram_size = 160 * 1024,
1400  .n_gpnvms = 2,
1401  .n_banks = 1,
1402 
1403  {
1404 /* .bank[0] = */
1405  {
1406  .probed = false,
1407  .chip = NULL,
1408  .bank = NULL,
1409  .bank_number = 0,
1410  .base_address = FLASH_BANK_BASE_S,
1411  .controller_address = 0x400e0a00,
1412  .flash_wait_states = 5,
1413  .present = true,
1414  .size_bytes = 512 * 1024,
1415  .nsectors = 64,
1416  .sector_size = 8192,
1417  .page_size = 512,
1418  },
1419 /* .bank[1] = */
1420  {
1421  .present = false,
1422  .probed = false,
1423  .bank_number = 1,
1424  },
1425  }
1426  },
1427 
1428  /* terminate */
1429  {
1430  .chipid_cidr = 0,
1431  .name = NULL,
1432  }
1433 };
1434 
1435 /* Globals above */
1436 /***********************************************************************
1437  **********************************************************************
1438  **********************************************************************
1439  **********************************************************************
1440  **********************************************************************
1441  **********************************************************************/
1442 /* *ATMEL* style code - from the SAM4 driver code */
1443 
1450 static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
1451 {
1452  int r;
1453  r = target_read_u32(private->chip->target,
1454  private->controller_address + OFFSET_EFC_FSR,
1455  v);
1456  LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1457  (unsigned int)(*v),
1458  ((unsigned int)((*v >> 2) & 1)),
1459  ((unsigned int)((*v >> 1) & 1)),
1460  ((unsigned int)((*v >> 0) & 1)));
1461 
1462  return r;
1463 }
1464 
1470 static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
1471 {
1472  int r;
1473  uint32_t rv;
1474  r = target_read_u32(private->chip->target,
1475  private->controller_address + OFFSET_EFC_FRR,
1476  &rv);
1477  if (v)
1478  *v = rv;
1479  LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1480  return r;
1481 }
1482 
1483 static int efc_start_command(struct sam4_bank_private *private,
1484  unsigned command, unsigned argument)
1485 {
1486  uint32_t n, v;
1487  int r;
1488  int retry;
1489 
1490  retry = 0;
1491 do_retry:
1492 
1493  /* Check command & argument */
1494  switch (command) {
1495 
1496  case AT91C_EFC_FCMD_WP:
1497  case AT91C_EFC_FCMD_WPL:
1498  case AT91C_EFC_FCMD_EWP:
1499  case AT91C_EFC_FCMD_EWPL:
1500  /* case AT91C_EFC_FCMD_EPL: */
1501  case AT91C_EFC_FCMD_EPA:
1502  case AT91C_EFC_FCMD_SLB:
1503  case AT91C_EFC_FCMD_CLB:
1504  n = (private->size_bytes / private->page_size);
1505  if (argument >= n)
1506  LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1507  break;
1508 
1509  case AT91C_EFC_FCMD_SFB:
1510  case AT91C_EFC_FCMD_CFB:
1511  if (argument >= private->chip->details.n_gpnvms) {
1512  LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1513  private->chip->details.n_gpnvms);
1514  }
1515  break;
1516 
1517  case AT91C_EFC_FCMD_GETD:
1518  case AT91C_EFC_FCMD_EA:
1519  case AT91C_EFC_FCMD_GLB:
1520  case AT91C_EFC_FCMD_GFB:
1521  case AT91C_EFC_FCMD_STUI:
1522  case AT91C_EFC_FCMD_SPUI:
1523  if (argument != 0)
1524  LOG_ERROR("Argument is meaningless for cmd: %d", command);
1525  break;
1526  default:
1527  LOG_ERROR("Unknown command %d", command);
1528  break;
1529  }
1530 
1531  if (command == AT91C_EFC_FCMD_SPUI) {
1532  /* this is a very special situation. */
1533  /* Situation (1) - error/retry - see below */
1534  /* And we are being called recursively */
1535  /* Situation (2) - normal, finished reading unique id */
1536  } else {
1537  /* it should be "ready" */
1538  efc_get_status(private, &v);
1539  if (v & 1) {
1540  /* then it is ready */
1541  /* we go on */
1542  } else {
1543  if (retry) {
1544  /* we have done this before */
1545  /* the controller is not responding. */
1546  LOG_ERROR("flash controller(%d) is not ready! Error",
1547  private->bank_number);
1548  return ERROR_FAIL;
1549  } else {
1550  retry++;
1551  LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1552  private->bank_number);
1553  /* we do that by issuing the *STOP* command */
1554  efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
1555  /* above is recursive, and further recursion is blocked by */
1556  /* if (command == AT91C_EFC_FCMD_SPUI) above */
1557  goto do_retry;
1558  }
1559  }
1560  }
1561 
1562  v = (0x5A << 24) | (argument << 8) | command;
1563  LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1564  r = target_write_u32(private->bank->target,
1565  private->controller_address + OFFSET_EFC_FCR, v);
1566  if (r != ERROR_OK)
1567  LOG_DEBUG("Error Write failed");
1568  return r;
1569 }
1570 
1578 static int efc_perform_command(struct sam4_bank_private *private,
1579  unsigned command,
1580  unsigned argument,
1581  uint32_t *status)
1582 {
1583 
1584  int r;
1585  uint32_t v;
1586  int64_t ms_now, ms_end;
1587 
1588  /* default */
1589  if (status)
1590  *status = 0;
1591 
1592  r = efc_start_command(private, command, argument);
1593  if (r != ERROR_OK)
1594  return r;
1595 
1596  ms_end = 10000 + timeval_ms();
1597 
1598  do {
1599  r = efc_get_status(private, &v);
1600  if (r != ERROR_OK)
1601  return r;
1602  ms_now = timeval_ms();
1603  if (ms_now > ms_end) {
1604  /* error */
1605  LOG_ERROR("Command timeout");
1606  return ERROR_FAIL;
1607  }
1608  } while ((v & 1) == 0);
1609 
1610  /* error bits.. */
1611  if (status)
1612  *status = (v & 0x6);
1613  return ERROR_OK;
1614 
1615 }
1616 
1622 static int flashd_read_uid(struct sam4_bank_private *private)
1623 {
1624  int r;
1625  uint32_t v;
1626  int x;
1627  /* assume 0 */
1628  private->chip->cfg.unique_id[0] = 0;
1629  private->chip->cfg.unique_id[1] = 0;
1630  private->chip->cfg.unique_id[2] = 0;
1631  private->chip->cfg.unique_id[3] = 0;
1632 
1633  LOG_DEBUG("Begin");
1634  r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
1635  if (r < 0)
1636  return r;
1637 
1638  for (x = 0; x < 4; x++) {
1639  r = target_read_u32(private->chip->target,
1640  private->bank->base + (x * 4),
1641  &v);
1642  if (r < 0)
1643  return r;
1644  private->chip->cfg.unique_id[x] = v;
1645  }
1646 
1647  r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
1648  LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1649  r,
1650  (unsigned int)(private->chip->cfg.unique_id[0]),
1651  (unsigned int)(private->chip->cfg.unique_id[1]),
1652  (unsigned int)(private->chip->cfg.unique_id[2]),
1653  (unsigned int)(private->chip->cfg.unique_id[3]));
1654  return r;
1655 
1656 }
1657 
1662 static int flashd_erase_entire_bank(struct sam4_bank_private *private)
1663 {
1664  LOG_DEBUG("Here");
1665  return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
1666 }
1667 
1675 static int flashd_erase_pages(struct sam4_bank_private *private,
1676  int first_page,
1677  int num_pages,
1678  uint32_t *status)
1679 {
1680  LOG_DEBUG("Here");
1681  uint8_t erase_pages;
1682  switch (num_pages) {
1683  case 4:
1684  erase_pages = 0x00;
1685  break;
1686  case 8:
1687  erase_pages = 0x01;
1688  break;
1689  case 16:
1690  erase_pages = 0x02;
1691  break;
1692  case 32:
1693  erase_pages = 0x03;
1694  break;
1695  default:
1696  erase_pages = 0x00;
1697  break;
1698  }
1699 
1700  /* AT91C_EFC_FCMD_EPA
1701  * According to the datasheet FARG[15:2] defines the page from which
1702  * the erase will start.This page must be modulo 4, 8, 16 or 32
1703  * according to the number of pages to erase. FARG[1:0] defines the
1704  * number of pages to be erased. Previously (firstpage << 2) was used
1705  * to conform to this, seems it should not be shifted...
1706  */
1707  return efc_perform_command(private,
1708  /* send Erase Page */
1709  AT91C_EFC_FCMD_EPA,
1710  (first_page) | erase_pages,
1711  status);
1712 }
1713 
1720 /* ------------------------------------------------------------------------------ */
1721 static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere)
1722 {
1723  uint32_t v;
1724  int r;
1725 
1726  LOG_DEBUG("Here");
1727  if (private->bank_number != 0) {
1728  LOG_ERROR("GPNVM only works with Bank0");
1729  return ERROR_FAIL;
1730  }
1731 
1732  if (gpnvm >= private->chip->details.n_gpnvms) {
1733  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1734  gpnvm, private->chip->details.n_gpnvms);
1735  return ERROR_FAIL;
1736  }
1737 
1738  /* Get GPNVMs status */
1739  r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
1740  if (r != ERROR_OK) {
1741  LOG_ERROR("Failed");
1742  return r;
1743  }
1744 
1745  r = efc_get_result(private, &v);
1746 
1747  if (puthere) {
1748  /* Check if GPNVM is set */
1749  /* get the bit and make it a 0/1 */
1750  *puthere = (v >> gpnvm) & 1;
1751  }
1752 
1753  return r;
1754 }
1755 
1762 static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1763 {
1764  int r;
1765  unsigned v;
1766 
1767  LOG_DEBUG("Here");
1768  if (private->bank_number != 0) {
1769  LOG_ERROR("GPNVM only works with Bank0");
1770  return ERROR_FAIL;
1771  }
1772 
1773  if (gpnvm >= private->chip->details.n_gpnvms) {
1774  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1775  gpnvm, private->chip->details.n_gpnvms);
1776  return ERROR_FAIL;
1777  }
1778 
1779  r = flashd_get_gpnvm(private, gpnvm, &v);
1780  if (r != ERROR_OK) {
1781  LOG_DEBUG("Failed: %d", r);
1782  return r;
1783  }
1784  r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1785  LOG_DEBUG("End: %d", r);
1786  return r;
1787 }
1788 
1794 static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
1795 {
1796  int r;
1797  unsigned v;
1798 
1799  if (private->bank_number != 0) {
1800  LOG_ERROR("GPNVM only works with Bank0");
1801  return ERROR_FAIL;
1802  }
1803 
1804  if (gpnvm >= private->chip->details.n_gpnvms) {
1805  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1806  gpnvm, private->chip->details.n_gpnvms);
1807  return ERROR_FAIL;
1808  }
1809 
1810  r = flashd_get_gpnvm(private, gpnvm, &v);
1811  if (r != ERROR_OK)
1812  return r;
1813  if (v) {
1814  /* already set */
1815  r = ERROR_OK;
1816  } else {
1817  /* set it */
1818  r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1819  }
1820  return r;
1821 }
1822 
1828 static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
1829 {
1830  int r;
1831  LOG_DEBUG("Here");
1832  r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
1833  if (r == ERROR_OK) {
1834  efc_get_result(private, v);
1835  efc_get_result(private, v);
1836  efc_get_result(private, v);
1837  r = efc_get_result(private, v);
1838  }
1839  LOG_DEBUG("End: %d", r);
1840  return r;
1841 }
1842 
1850 static int flashd_unlock(struct sam4_bank_private *private,
1851  unsigned start_sector,
1852  unsigned end_sector)
1853 {
1854  int r;
1855  uint32_t status;
1856  uint32_t pg;
1857  uint32_t pages_per_sector;
1858 
1859  pages_per_sector = private->sector_size / private->page_size;
1860 
1861  /* Unlock all pages */
1862  while (start_sector <= end_sector) {
1863  pg = start_sector * pages_per_sector;
1864 
1865  r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
1866  if (r != ERROR_OK)
1867  return r;
1868  start_sector++;
1869  }
1870 
1871  return ERROR_OK;
1872 }
1873 
1880 static int flashd_lock(struct sam4_bank_private *private,
1881  unsigned start_sector,
1882  unsigned end_sector)
1883 {
1884  uint32_t status;
1885  uint32_t pg;
1886  uint32_t pages_per_sector;
1887  int r;
1888 
1889  pages_per_sector = private->sector_size / private->page_size;
1890 
1891  /* Lock all pages */
1892  while (start_sector <= end_sector) {
1893  pg = start_sector * pages_per_sector;
1894 
1895  r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
1896  if (r != ERROR_OK)
1897  return r;
1898  start_sector++;
1899  }
1900  return ERROR_OK;
1901 }
1902 
1903 /****** END SAM4 CODE ********/
1904 
1905 /* begin helpful debug code */
1906 /* print the fieldname, the field value, in dec & hex, and return field value */
1907 static uint32_t sam4_reg_fieldname(struct sam4_chip *chip,
1908  const char *regname,
1909  uint32_t value,
1910  unsigned shift,
1911  unsigned width)
1912 {
1913  uint32_t v;
1914  int hwidth, dwidth;
1915 
1916 
1917  /* extract the field */
1918  v = value >> shift;
1919  v = v & ((1 << width)-1);
1920  if (width <= 16) {
1921  hwidth = 4;
1922  dwidth = 5;
1923  } else {
1924  hwidth = 8;
1925  dwidth = 12;
1926  }
1927 
1928  /* show the basics */
1929  LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
1930  REG_NAME_WIDTH, regname,
1931  dwidth, v,
1932  hwidth, v);
1933  return v;
1934 }
1935 
1936 static const char _unknown[] = "unknown";
1937 static const char *const eproc_names[] = {
1938  "Cortex-M7", /* 0 */
1939  "arm946es", /* 1 */
1940  "arm7tdmi", /* 2 */
1941  "Cortex-M3", /* 3 */
1942  "arm920t", /* 4 */
1943  "arm926ejs", /* 5 */
1944  "Cortex-A5", /* 6 */
1945  "Cortex-M4", /* 7 */
1946  _unknown, /* 8 */
1947  _unknown, /* 9 */
1948  _unknown, /* 10 */
1949  _unknown, /* 11 */
1950  _unknown, /* 12 */
1951  _unknown, /* 13 */
1952  _unknown, /* 14 */
1953  _unknown, /* 15 */
1954 };
1955 
1956 #define nvpsize2 nvpsize /* these two tables are identical */
1957 static const char *const nvpsize[] = {
1958  "none", /* 0 */
1959  "8K bytes", /* 1 */
1960  "16K bytes", /* 2 */
1961  "32K bytes", /* 3 */
1962  _unknown, /* 4 */
1963  "64K bytes", /* 5 */
1964  _unknown, /* 6 */
1965  "128K bytes", /* 7 */
1966  "160K bytes", /* 8 */
1967  "256K bytes", /* 9 */
1968  "512K bytes", /* 10 */
1969  _unknown, /* 11 */
1970  "1024K bytes", /* 12 */
1971  _unknown, /* 13 */
1972  "2048K bytes", /* 14 */
1973  _unknown, /* 15 */
1974 };
1975 
1976 static const char *const sramsize[] = {
1977  "48K Bytes", /* 0 */
1978  "1K Bytes", /* 1 */
1979  "2K Bytes", /* 2 */
1980  "6K Bytes", /* 3 */
1981  "112K Bytes", /* 4 */
1982  "4K Bytes", /* 5 */
1983  "80K Bytes", /* 6 */
1984  "160K Bytes", /* 7 */
1985  "8K Bytes", /* 8 */
1986  "16K Bytes", /* 9 */
1987  "32K Bytes", /* 10 */
1988  "64K Bytes", /* 11 */
1989  "128K Bytes", /* 12 */
1990  "256K Bytes", /* 13 */
1991  "96K Bytes", /* 14 */
1992  "512K Bytes", /* 15 */
1993 
1994 };
1995 
1996 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1997  { 0x19, "AT91SAM9xx Series" },
1998  { 0x29, "AT91SAM9XExx Series" },
1999  { 0x34, "AT91x34 Series" },
2000  { 0x37, "CAP7 Series" },
2001  { 0x39, "CAP9 Series" },
2002  { 0x3B, "CAP11 Series" },
2003  { 0x3C, "ATSAM4E" },
2004  { 0x40, "AT91x40 Series" },
2005  { 0x42, "AT91x42 Series" },
2006  { 0x43, "SAMG51 Series"
2007  },
2008  { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2009  { 0x45, "SAMG55 Series (64-pin)" },
2010  { 0x47, "SAMG53 Series"
2011  },
2012  { 0x55, "AT91x55 Series" },
2013  { 0x60, "AT91SAM7Axx Series" },
2014  { 0x61, "AT91SAM7AQxx Series" },
2015  { 0x63, "AT91x63 Series" },
2016  { 0x64, "SAM4CxxC (100-pin version)" },
2017  { 0x66, "SAM4CxxE (144-pin version)" },
2018  { 0x70, "AT91SAM7Sxx Series" },
2019  { 0x71, "AT91SAM7XCxx Series" },
2020  { 0x72, "AT91SAM7SExx Series" },
2021  { 0x73, "AT91SAM7Lxx Series" },
2022  { 0x75, "AT91SAM7Xxx Series" },
2023  { 0x76, "AT91SAM7SLxx Series" },
2024  { 0x80, "ATSAM3UxC Series (100-pin version)" },
2025  { 0x81, "ATSAM3UxE Series (144-pin version)" },
2026  { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2027  { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2028  { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2029  { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2030  { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2031  { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2032  { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2033  { 0x92, "AT91x92 Series" },
2034  { 0x93, "ATSAM3NxA Series (48-pin version)" },
2035  { 0x94, "ATSAM3NxB Series (64-pin version)" },
2036  { 0x95, "ATSAM3NxC Series (100-pin version)" },
2037  { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2038  { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2039  { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2040  { 0xA5, "ATSAM5A" },
2041  { 0xF0, "AT75Cxx Series" },
2042  { -1, NULL },
2043 };
2044 
2045 static const char *const nvptype[] = {
2046  "rom", /* 0 */
2047  "romless or onchip flash", /* 1 */
2048  "embedded flash memory",/* 2 */
2049  "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2050  "sram emulating flash", /* 4 */
2051  _unknown, /* 5 */
2052  _unknown, /* 6 */
2053  _unknown, /* 7 */
2054 };
2055 
2056 static const char *_yes_or_no(uint32_t v)
2057 {
2058  if (v)
2059  return "YES";
2060  else
2061  return "NO";
2062 }
2063 
2064 static const char *const _rc_freq[] = {
2065  "4 MHz", "8 MHz", "12 MHz", "reserved"
2066 };
2067 
2068 static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
2069 {
2070  uint32_t v;
2071  uint32_t rcen;
2072 
2073  v = sam4_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2074  LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2075  v = sam4_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2076  LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2077  rcen = sam4_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2078  LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2079  v = sam4_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2080  LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2081 
2082  chip->cfg.rc_freq = 0;
2083  if (rcen) {
2084  switch (v) {
2085  default:
2086  chip->cfg.rc_freq = 0;
2087  break;
2088  case 0:
2089  chip->cfg.rc_freq = 4 * 1000 * 1000;
2090  break;
2091  case 1:
2092  chip->cfg.rc_freq = 8 * 1000 * 1000;
2093  break;
2094  case 2:
2095  chip->cfg.rc_freq = 12 * 1000 * 1000;
2096  break;
2097  }
2098  }
2099 
2100  v = sam4_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2101  LOG_USER("(startup clks, time= %f uSecs)",
2102  ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2103  v = sam4_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2104  LOG_USER("(mainosc source: %s)",
2105  v ? "external xtal" : "internal RC");
2106 
2107  v = sam4_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2108  LOG_USER("(clock failure enabled: %s)",
2109  _yes_or_no(v));
2110 }
2111 
2112 static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
2113 {
2114  int x;
2115  uint32_t v;
2116  const char *cp;
2117 
2118  sam4_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2119  LOG_USER_N("\n");
2120 
2121  v = sam4_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2122  LOG_USER("%s", eproc_names[v]);
2123 
2124  v = sam4_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2125  LOG_USER("%s", nvpsize[v]);
2126 
2127  v = sam4_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2128  LOG_USER("%s", nvpsize2[v]);
2129 
2130  v = sam4_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2131  LOG_USER("%s", sramsize[v]);
2132 
2133  v = sam4_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2134  cp = _unknown;
2135  for (x = 0; archnames[x].name; x++) {
2136  if (v == archnames[x].value) {
2137  cp = archnames[x].name;
2138  break;
2139  }
2140  }
2141 
2142  LOG_USER("%s", cp);
2143 
2144  v = sam4_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2145  LOG_USER("%s", nvptype[v]);
2146 
2147  v = sam4_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2148  LOG_USER("(exists: %s)", _yes_or_no(v));
2149 }
2150 
2151 static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
2152 {
2153  uint32_t v;
2154 
2155  v = sam4_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2156  LOG_USER("(main ready: %s)", _yes_or_no(v));
2157 
2158  v = sam4_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2159 
2160  v = (v * chip->cfg.slow_freq) / 16;
2161  chip->cfg.mainosc_freq = v;
2162 
2163  LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2164  _tomhz(v),
2165  (uint32_t)(chip->cfg.slow_freq / 1000),
2166  (uint32_t)(chip->cfg.slow_freq % 1000));
2167 }
2168 
2169 static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
2170 {
2171  uint32_t mula, diva;
2172 
2173  diva = sam4_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2174  LOG_USER_N("\n");
2175  mula = sam4_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2176  LOG_USER_N("\n");
2177  chip->cfg.plla_freq = 0;
2178  if (mula == 0)
2179  LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2180  else if (diva == 0)
2181  LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2182  else if (diva >= 1) {
2183  chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2184  LOG_USER("\tPLLA Freq: %3.03f MHz",
2185  _tomhz(chip->cfg.plla_freq));
2186  }
2187 }
2188 
2189 static void sam4_explain_mckr(struct sam4_chip *chip)
2190 {
2191  uint32_t css, pres, fin = 0;
2192  int pdiv = 0;
2193  const char *cp = NULL;
2194 
2195  css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2196  switch (css & 3) {
2197  case 0:
2198  fin = chip->cfg.slow_freq;
2199  cp = "slowclk";
2200  break;
2201  case 1:
2202  fin = chip->cfg.mainosc_freq;
2203  cp = "mainosc";
2204  break;
2205  case 2:
2206  fin = chip->cfg.plla_freq;
2207  cp = "plla";
2208  break;
2209  case 3:
2210  if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2211  fin = 480 * 1000 * 1000;
2212  cp = "upll";
2213  } else {
2214  fin = 0;
2215  cp = "upll (*ERROR* UPLL is disabled)";
2216  }
2217  break;
2218  default:
2219  assert(0);
2220  break;
2221  }
2222 
2223  LOG_USER("%s (%3.03f Mhz)",
2224  cp,
2225  _tomhz(fin));
2226  pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2227  switch (pres & 0x07) {
2228  case 0:
2229  pdiv = 1;
2230  cp = "selected clock";
2231  break;
2232  case 1:
2233  pdiv = 2;
2234  cp = "clock/2";
2235  break;
2236  case 2:
2237  pdiv = 4;
2238  cp = "clock/4";
2239  break;
2240  case 3:
2241  pdiv = 8;
2242  cp = "clock/8";
2243  break;
2244  case 4:
2245  pdiv = 16;
2246  cp = "clock/16";
2247  break;
2248  case 5:
2249  pdiv = 32;
2250  cp = "clock/32";
2251  break;
2252  case 6:
2253  pdiv = 64;
2254  cp = "clock/64";
2255  break;
2256  case 7:
2257  pdiv = 6;
2258  cp = "clock/6";
2259  break;
2260  default:
2261  assert(0);
2262  break;
2263  }
2264  LOG_USER("(%s)", cp);
2265  fin = fin / pdiv;
2266  /* sam4 has a *SINGLE* clock - */
2267  /* other at91 series parts have divisors for these. */
2268  chip->cfg.cpu_freq = fin;
2269  chip->cfg.mclk_freq = fin;
2270  chip->cfg.fclk_freq = fin;
2271  LOG_USER("\t\tResult CPU Freq: %3.03f",
2272  _tomhz(fin));
2273 }
2274 
2275 #if 0
2276 static struct sam4_chip *target2sam4(struct target *target)
2277 {
2278  struct sam4_chip *chip;
2279 
2280  if (!target)
2281  return NULL;
2282 
2283  chip = all_sam4_chips;
2284  while (chip) {
2285  if (chip->target == target)
2286  break; /* return below */
2287  else
2288  chip = chip->next;
2289  }
2290  return chip;
2291 }
2292 #endif
2293 
2294 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
2295 {
2296  /* this function exists to help */
2297  /* keep funky offsetof() errors */
2298  /* and casting from causing bugs */
2299 
2300  /* By using prototypes - we can detect what would */
2301  /* be casting errors. */
2302 
2303  return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2304 }
2305 
2306 
2307 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2308  struct sam4_cfg, \
2309  NAME), # NAME, FUNC }
2310 static const struct sam4_reg_list sam4_all_regs[] = {
2311  SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2312  SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2313  SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2314  SAM4_ENTRY(CKGR_UCKR, NULL),
2315  SAM4_ENTRY(PMC_FSMR, NULL),
2316  SAM4_ENTRY(PMC_FSPR, NULL),
2317  SAM4_ENTRY(PMC_IMR, NULL),
2318  SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2319  SAM4_ENTRY(PMC_PCK0, NULL),
2320  SAM4_ENTRY(PMC_PCK1, NULL),
2321  SAM4_ENTRY(PMC_PCK2, NULL),
2322  SAM4_ENTRY(PMC_PCSR, NULL),
2323  SAM4_ENTRY(PMC_SCSR, NULL),
2324  SAM4_ENTRY(PMC_SR, NULL),
2325  SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2326  SAM4_ENTRY(CHIPID_EXID, NULL),
2327  /* TERMINATE THE LIST */
2328  { .name = NULL }
2329 };
2330 #undef SAM4_ENTRY
2331 
2332 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2333 {
2334  return bank->driver_priv;
2335 }
2336 
2341 static const struct sam4_reg_list *sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
2342 {
2343  const struct sam4_reg_list *reg;
2344 
2345  reg = &(sam4_all_regs[0]);
2346  while (reg->name) {
2347  uint32_t *possible;
2348 
2349  /* calculate where this one go.. */
2350  /* it is "possibly" this register. */
2351 
2352  possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2353 
2354  /* well? Is it this register */
2355  if (possible == goes_here) {
2356  /* Jump for joy! */
2357  return reg;
2358  }
2359 
2360  /* next... */
2361  reg++;
2362  }
2363  /* This is *TOTAL*PANIC* - we are totally screwed. */
2364  LOG_ERROR("INVALID SAM4 REGISTER");
2365  return NULL;
2366 }
2367 
2368 static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
2369 {
2370  const struct sam4_reg_list *reg;
2371  int r;
2372 
2373  reg = sam4_get_reg(chip, goes_here);
2374  if (!reg)
2375  return ERROR_FAIL;
2376 
2377  r = target_read_u32(chip->target, reg->address, goes_here);
2378  if (r != ERROR_OK) {
2379  LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2380  reg->name, (unsigned)(reg->address), r);
2381  }
2382  return r;
2383 }
2384 
2385 static int sam4_read_all_regs(struct sam4_chip *chip)
2386 {
2387  int r;
2388  const struct sam4_reg_list *reg;
2389 
2390  reg = &(sam4_all_regs[0]);
2391  while (reg->name) {
2392  r = sam4_read_this_reg(chip,
2393  sam4_get_reg_ptr(&(chip->cfg), reg));
2394  if (r != ERROR_OK) {
2395  LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2396  reg->name, ((unsigned)(reg->address)), r);
2397  return r;
2398  }
2399  reg++;
2400  }
2401 
2402  return ERROR_OK;
2403 }
2404 
2405 static int sam4_get_info(struct sam4_chip *chip)
2406 {
2407  const struct sam4_reg_list *reg;
2408  uint32_t regval;
2409  int r;
2410 
2411  r = sam4_read_all_regs(chip);
2412  if (r != ERROR_OK)
2413  return r;
2414 
2415  reg = &(sam4_all_regs[0]);
2416  while (reg->name) {
2417  /* display all regs */
2418  LOG_DEBUG("Start: %s", reg->name);
2419  regval = *sam4_get_reg_ptr(&(chip->cfg), reg);
2420  LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2421  REG_NAME_WIDTH,
2422  reg->name,
2423  reg->address,
2424  regval);
2425  if (reg->explain_func)
2426  (*(reg->explain_func))(chip);
2427  LOG_DEBUG("End: %s", reg->name);
2428  reg++;
2429  }
2430  LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2431  LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2432  LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2433  LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2434  LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2435 
2436  LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2437  chip->cfg.unique_id[0],
2438  chip->cfg.unique_id[1],
2439  chip->cfg.unique_id[2],
2440  chip->cfg.unique_id[3]);
2441 
2442  return ERROR_OK;
2443 }
2444 
2445 static int sam4_protect_check(struct flash_bank *bank)
2446 {
2447  int r;
2448  uint32_t v[4] = {0};
2449  unsigned x;
2450  struct sam4_bank_private *private;
2451 
2452  LOG_DEBUG("Begin");
2453  if (bank->target->state != TARGET_HALTED) {
2454  LOG_ERROR("Target not halted");
2455  return ERROR_TARGET_NOT_HALTED;
2456  }
2457 
2458  private = get_sam4_bank_private(bank);
2459  if (!private) {
2460  LOG_ERROR("no private for this bank?");
2461  return ERROR_FAIL;
2462  }
2463  if (!(private->probed))
2464  return ERROR_FLASH_BANK_NOT_PROBED;
2465 
2466  r = flashd_get_lock_bits(private, v);
2467  if (r != ERROR_OK) {
2468  LOG_DEBUG("Failed: %d", r);
2469  return r;
2470  }
2471 
2472  for (x = 0; x < private->nsectors; x++)
2473  bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2474  LOG_DEBUG("Done");
2475  return ERROR_OK;
2476 }
2477 
2478 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2479 {
2480  struct sam4_chip *chip;
2481 
2482  chip = all_sam4_chips;
2483 
2484  /* is this an existing chip? */
2485  while (chip) {
2486  if (chip->target == bank->target)
2487  break;
2488  chip = chip->next;
2489  }
2490 
2491  if (!chip) {
2492  /* this is a *NEW* chip */
2493  chip = calloc(1, sizeof(struct sam4_chip));
2494  if (!chip) {
2495  LOG_ERROR("NO RAM!");
2496  return ERROR_FAIL;
2497  }
2498  chip->target = bank->target;
2499  /* insert at head */
2500  chip->next = all_sam4_chips;
2501  all_sam4_chips = chip;
2502  chip->target = bank->target;
2503  /* assumption is this runs at 32khz */
2504  chip->cfg.slow_freq = 32768;
2505  chip->probed = false;
2506  }
2507 
2508  switch (bank->base) {
2509  default:
2510  LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2511  "[at91sam4s series] )",
2512  ((unsigned int)(bank->base)),
2513  ((unsigned int)(FLASH_BANK_BASE_S)));
2514  return ERROR_FAIL;
2515 
2516  /* at91sam4s series only has bank 0*/
2517  /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2518  case FLASH_BANK_BASE_S:
2519  case FLASH_BANK_BASE_C:
2520  bank->driver_priv = &(chip->details.bank[0]);
2521  bank->bank_number = 0;
2522  chip->details.bank[0].chip = chip;
2523  chip->details.bank[0].bank = bank;
2524  break;
2525 
2526  /* Bank 1 of at91sam4sd/at91sam4c32 series */
2527  case FLASH_BANK1_BASE_1024K_SD:
2528  case FLASH_BANK1_BASE_2048K_SD:
2529  case FLASH_BANK1_BASE_C32:
2530  bank->driver_priv = &(chip->details.bank[1]);
2531  bank->bank_number = 1;
2532  chip->details.bank[1].chip = chip;
2533  chip->details.bank[1].bank = bank;
2534  break;
2535  }
2536 
2537  /* we initialize after probing. */
2538  return ERROR_OK;
2539 }
2540 
2546 static void sam4_free_driver_priv(struct flash_bank *bank)
2547 {
2548  struct sam4_chip *chip = all_sam4_chips;
2549  while (chip) {
2550  struct sam4_chip *next = chip->next;
2551  free(chip);
2552  chip = next;
2553  }
2554  all_sam4_chips = NULL;
2555 }
2556 
2557 static int sam4_get_details(struct sam4_bank_private *private)
2558 {
2559  const struct sam4_chip_details *details;
2560  struct sam4_chip *chip;
2561  struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2562  unsigned x;
2563 
2564  LOG_DEBUG("Begin");
2565  details = all_sam4_details;
2566  while (details->name) {
2567  /* Compare cidr without version bits */
2568  if (details->chipid_cidr == (private->chip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2569  break;
2570  else
2571  details++;
2572  }
2573  if (!details->name) {
2574  LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2575  (unsigned int)(private->chip->cfg.CHIPID_CIDR));
2576  /* Help the victim, print details about the chip */
2577  LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2578  private->chip->cfg.CHIPID_CIDR);
2579  sam4_explain_chipid_cidr(private->chip);
2580  return ERROR_FAIL;
2581  } else {
2582  LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
2583  }
2584 
2585  /* DANGER: THERE ARE DRAGONS HERE */
2586 
2587  /* get our chip - it is going */
2588  /* to be over-written shortly */
2589  chip = private->chip;
2590 
2591  /* Note that, in reality: */
2592  /* */
2593  /* private = &(chip->details.bank[0]) */
2594  /* or private = &(chip->details.bank[1]) */
2595  /* */
2596 
2597  /* save the "bank" pointers */
2598  for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2599  saved_banks[x] = chip->details.bank[x].bank;
2600 
2601  /* Overwrite the "details" structure. */
2602  memcpy(&(private->chip->details),
2603  details,
2604  sizeof(private->chip->details));
2605 
2606  /* now fix the ghosted pointers */
2607  for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2608  chip->details.bank[x].chip = chip;
2609  chip->details.bank[x].bank = saved_banks[x];
2610  }
2611 
2612  /* update the *BANK*SIZE* */
2613 
2614  LOG_DEBUG("End");
2615  return ERROR_OK;
2616 }
2617 
2618 static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
2619 {
2620  struct sam4_bank_private *private;
2621  int k = bank->size / 1024;
2622 
2623  private = get_sam4_bank_private(bank);
2624  if (!private)
2625  return ERROR_FAIL;
2626 
2627  command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
2628  private->chip->details.name,
2629  private->bank_number,
2630  k,
2631  bank->base);
2632 
2633  return ERROR_OK;
2634 }
2635 
2636 static int sam4_probe(struct flash_bank *bank)
2637 {
2638  int r;
2639  struct sam4_bank_private *private;
2640 
2641 
2642  LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
2643  if (bank->target->state != TARGET_HALTED) {
2644  LOG_ERROR("Target not halted");
2645  return ERROR_TARGET_NOT_HALTED;
2646  }
2647 
2648  private = get_sam4_bank_private(bank);
2649  if (!private) {
2650  LOG_ERROR("Invalid/unknown bank number");
2651  return ERROR_FAIL;
2652  }
2653 
2654  r = sam4_read_all_regs(private->chip);
2655  if (r != ERROR_OK)
2656  return r;
2657 
2658  LOG_DEBUG("Here");
2659  if (private->chip->probed)
2660  r = sam4_get_info(private->chip);
2661  else
2662  r = sam4_get_details(private);
2663  if (r != ERROR_OK)
2664  return r;
2665 
2666  /* update the flash bank size */
2667  for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2668  if (bank->base == private->chip->details.bank[x].base_address) {
2669  bank->size = private->chip->details.bank[x].size_bytes;
2670  LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
2671  TARGET_ADDR_FMT ", idx %d", bank->base,
2672  bank->base + bank->size, x);
2673  break;
2674  }
2675  }
2676 
2677  if (!bank->sectors) {
2678  bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
2679  if (!bank->sectors) {
2680  LOG_ERROR("No memory!");
2681  return ERROR_FAIL;
2682  }
2683  bank->num_sectors = private->nsectors;
2684 
2685  for (unsigned int x = 0; x < bank->num_sectors; x++) {
2686  bank->sectors[x].size = private->sector_size;
2687  bank->sectors[x].offset = x * (private->sector_size);
2688  /* mark as unknown */
2689  bank->sectors[x].is_erased = -1;
2690  bank->sectors[x].is_protected = -1;
2691  }
2692  }
2693 
2694  private->probed = true;
2695 
2696  r = sam4_protect_check(bank);
2697  if (r != ERROR_OK)
2698  return r;
2699 
2700  LOG_DEBUG("Bank = %d, nbanks = %d",
2701  private->bank_number, private->chip->details.n_banks);
2702  if ((private->bank_number + 1) == private->chip->details.n_banks) {
2703  /* read unique id, */
2704  /* it appears to be associated with the *last* flash bank. */
2705  flashd_read_uid(private);
2706  }
2707 
2708  return r;
2709 }
2710 
2711 static int sam4_auto_probe(struct flash_bank *bank)
2712 {
2713  struct sam4_bank_private *private;
2714 
2715  private = get_sam4_bank_private(bank);
2716  if (private && private->probed)
2717  return ERROR_OK;
2718 
2719  return sam4_probe(bank);
2720 }
2721 
2722 static int sam4_erase(struct flash_bank *bank, unsigned int first,
2723  unsigned int last)
2724 {
2725  struct sam4_bank_private *private;
2726  int r;
2727  int page_count;
2728  /*16 pages equals 8KB - Same size as a lock region*/
2729  page_count = 16;
2730  uint32_t status;
2731 
2732  LOG_DEBUG("Here");
2733  if (bank->target->state != TARGET_HALTED) {
2734  LOG_ERROR("Target not halted");
2735  return ERROR_TARGET_NOT_HALTED;
2736  }
2737 
2738  r = sam4_auto_probe(bank);
2739  if (r != ERROR_OK) {
2740  LOG_DEBUG("Here,r=%d", r);
2741  return r;
2742  }
2743 
2744  private = get_sam4_bank_private(bank);
2745  if (!(private->probed))
2746  return ERROR_FLASH_BANK_NOT_PROBED;
2747 
2748  if ((first == 0) && ((last + 1) == private->nsectors)) {
2749  /* whole chip */
2750  LOG_DEBUG("Here");
2751  return flashd_erase_entire_bank(private);
2752  }
2753  LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2754  LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
2755  for (unsigned int i = first; i <= last; i++) {
2756  /*16 pages equals 8KB - Same size as a lock region*/
2757  r = flashd_erase_pages(private, (i * page_count), page_count, &status);
2758  LOG_INFO("Erasing sector: 0x%08x", i);
2759  if (r != ERROR_OK)
2760  LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2761  i);
2762  if (status & (1 << 2)) {
2763  LOG_ERROR("SAM4: Lock Region %u is locked", i);
2764  return ERROR_FAIL;
2765  }
2766  if (status & (1 << 1)) {
2767  LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
2768  return ERROR_FAIL;
2769  }
2770  }
2771 
2772  return ERROR_OK;
2773 }
2774 
2775 static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
2776  unsigned int last)
2777 {
2778  struct sam4_bank_private *private;
2779  int r;
2780 
2781  LOG_DEBUG("Here");
2782  if (bank->target->state != TARGET_HALTED) {
2783  LOG_ERROR("Target not halted");
2784  return ERROR_TARGET_NOT_HALTED;
2785  }
2786 
2787  private = get_sam4_bank_private(bank);
2788  if (!(private->probed))
2789  return ERROR_FLASH_BANK_NOT_PROBED;
2790 
2791  if (set)
2792  r = flashd_lock(private, first, last);
2793  else
2794  r = flashd_unlock(private, first, last);
2795  LOG_DEBUG("End: r=%d", r);
2796 
2797  return r;
2798 
2799 }
2800 
2801 static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf)
2802 {
2803  uint32_t adr;
2804  int r;
2805 
2806  adr = pagenum * private->page_size;
2807  adr = adr + private->base_address;
2808 
2809  r = target_read_memory(private->chip->target,
2810  adr,
2811  4, /* THIS*MUST*BE* in 32bit values */
2812  private->page_size / 4,
2813  buf);
2814  if (r != ERROR_OK)
2815  LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2816  (unsigned int)(adr));
2817  return r;
2818 }
2819 
2820 static int sam4_set_wait(struct sam4_bank_private *private)
2821 {
2822  uint32_t fmr; /* EEFC Flash Mode Register */
2823  int r;
2824 
2825  /* Get flash mode register value */
2826  r = target_read_u32(private->chip->target, private->controller_address, &fmr);
2827  if (r != ERROR_OK) {
2828  LOG_ERROR("Error Read failed: read flash mode register");
2829  return r;
2830  }
2831 
2832  /* Clear flash wait state field */
2833  fmr &= 0xfffff0ff;
2834 
2835  /* set FWS (flash wait states) field in the FMR (flash mode register) */
2836  fmr |= (private->flash_wait_states << 8);
2837 
2838  LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2839  r = target_write_u32(private->bank->target, private->controller_address, fmr);
2840  if (r != ERROR_OK)
2841  LOG_ERROR("Error Write failed: set flash mode register");
2842 
2843  return r;
2844 }
2845 
2846 static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf)
2847 {
2848  uint32_t adr;
2849  uint32_t status;
2850  int r;
2851 
2852  adr = pagenum * private->page_size;
2853  adr = (adr + private->base_address);
2854 
2855  /* 1st sector 8kBytes - page 0 - 15*/
2856  /* 2nd sector 8kBytes - page 16 - 30*/
2857  /* 3rd sector 48kBytes - page 31 - 127*/
2858  LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2859  r = target_write_memory(private->chip->target,
2860  adr,
2861  4, /* THIS*MUST*BE* in 32bit values */
2862  private->page_size / 4,
2863  buf);
2864  if (r != ERROR_OK) {
2865  LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2866  (unsigned int)(adr));
2867  return r;
2868  }
2869 
2870  r = efc_perform_command(private,
2871  /* send Erase & Write Page */
2872  AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2873  pagenum,
2874  &status);
2875 
2876  if (r != ERROR_OK)
2877  LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2878  (unsigned int)(adr));
2879  if (status & (1 << 2)) {
2880  LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2881  return ERROR_FAIL;
2882  }
2883  if (status & (1 << 1)) {
2884  LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2885  return ERROR_FAIL;
2886  }
2887  return ERROR_OK;
2888 }
2889 
2890 static int sam4_write(struct flash_bank *bank,
2891  const uint8_t *buffer,
2892  uint32_t offset,
2893  uint32_t count)
2894 {
2895  int n;
2896  unsigned page_cur;
2897  unsigned page_end;
2898  int r;
2899  unsigned page_offset;
2900  struct sam4_bank_private *private;
2901  uint8_t *pagebuffer;
2902 
2903  /* in case we bail further below, set this to null */
2904  pagebuffer = NULL;
2905 
2906  /* ignore dumb requests */
2907  if (count == 0) {
2908  r = ERROR_OK;
2909  goto done;
2910  }
2911 
2912  if (bank->target->state != TARGET_HALTED) {
2913  LOG_ERROR("Target not halted");
2914  r = ERROR_TARGET_NOT_HALTED;
2915  goto done;
2916  }
2917 
2918  private = get_sam4_bank_private(bank);
2919  if (!(private->probed)) {
2920  r = ERROR_FLASH_BANK_NOT_PROBED;
2921  goto done;
2922  }
2923 
2924  if ((offset + count) > private->size_bytes) {
2925  LOG_ERROR("Flash write error - past end of bank");
2926  LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2927  (unsigned int)(offset),
2928  (unsigned int)(count),
2929  (unsigned int)(private->size_bytes));
2930  r = ERROR_FAIL;
2931  goto done;
2932  }
2933 
2934  pagebuffer = malloc(private->page_size);
2935  if (!pagebuffer) {
2936  LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
2937  r = ERROR_FAIL;
2938  goto done;
2939  }
2940 
2941  r = sam4_set_wait(private);
2942  if (r != ERROR_OK)
2943  goto done;
2944 
2945  /* what page do we start & end in? */
2946  page_cur = offset / private->page_size;
2947  page_end = (offset + count - 1) / private->page_size;
2948 
2949  LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2950  LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2951 
2952  /* Special case: all one page */
2953  /* */
2954  /* Otherwise: */
2955  /* (1) non-aligned start */
2956  /* (2) body pages */
2957  /* (3) non-aligned end. */
2958 
2959  /* Handle special case - all one page. */
2960  if (page_cur == page_end) {
2961  LOG_DEBUG("Special case, all in one page");
2962  r = sam4_page_read(private, page_cur, pagebuffer);
2963  if (r != ERROR_OK)
2964  goto done;
2965 
2966  page_offset = (offset & (private->page_size-1));
2967  memcpy(pagebuffer + page_offset,
2968  buffer,
2969  count);
2970 
2971  r = sam4_page_write(private, page_cur, pagebuffer);
2972  if (r != ERROR_OK)
2973  goto done;
2974  r = ERROR_OK;
2975  goto done;
2976  }
2977 
2978  /* non-aligned start */
2979  page_offset = offset & (private->page_size - 1);
2980  if (page_offset) {
2981  LOG_DEBUG("Not-Aligned start");
2982  /* read the partial */
2983  r = sam4_page_read(private, page_cur, pagebuffer);
2984  if (r != ERROR_OK)
2985  goto done;
2986 
2987  /* over-write with new data */
2988  n = (private->page_size - page_offset);
2989  memcpy(pagebuffer + page_offset,
2990  buffer,
2991  n);
2992 
2993  r = sam4_page_write(private, page_cur, pagebuffer);
2994  if (r != ERROR_OK)
2995  goto done;
2996 
2997  count -= n;
2998  offset += n;
2999  buffer += n;
3000  page_cur++;
3001  }
3002 
3003  /* By checking that offset is correct here, we also
3004  fix a clang warning */
3005  assert(offset % private->page_size == 0);
3006 
3007  /* intermediate large pages */
3008  /* also - the final *terminal* */
3009  /* if that terminal page is a full page */
3010  LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3011  (int)page_cur, (int)page_end, (unsigned int)(count));
3012 
3013  while ((page_cur < page_end) &&
3014  (count >= private->page_size)) {
3015  r = sam4_page_write(private, page_cur, buffer);
3016  if (r != ERROR_OK)
3017  goto done;
3018  count -= private->page_size;
3019  buffer += private->page_size;
3020  page_cur += 1;
3021  }
3022 
3023  /* terminal partial page? */
3024  if (count) {
3025  LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3026  /* we have a partial page */
3027  r = sam4_page_read(private, page_cur, pagebuffer);
3028  if (r != ERROR_OK)
3029  goto done;
3030  /* data goes at start */
3031  memcpy(pagebuffer, buffer, count);
3032  r = sam4_page_write(private, page_cur, pagebuffer);
3033  if (r != ERROR_OK)
3034  goto done;
3035  }
3036  LOG_DEBUG("Done!");
3037  r = ERROR_OK;
3038 done:
3039  free(pagebuffer);
3040  return r;
3041 }
3042 
3043 COMMAND_HANDLER(sam4_handle_info_command)
3044 {
3045  struct sam4_chip *chip;
3046  chip = get_current_sam4(CMD);
3047  if (!chip)
3048  return ERROR_OK;
3049 
3050  unsigned x;
3051  int r;
3052 
3053  /* bank0 must exist before we can do anything */
3054  if (!chip->details.bank[0].bank) {
3055  x = 0;
3056 need_define:
3057  command_print(CMD,
3058  "Please define bank %d via command: flash bank %s ... ",
3059  x,
3060  at91sam4_flash.name);
3061  return ERROR_FAIL;
3062  }
3063 
3064  /* if bank 0 is not probed, then probe it */
3065  if (!(chip->details.bank[0].probed)) {
3066  r = sam4_auto_probe(chip->details.bank[0].bank);
3067  if (r != ERROR_OK)
3068  return ERROR_FAIL;
3069  }
3070  /* above guarantees the "chip details" structure is valid */
3071  /* and thus, bank private areas are valid */
3072  /* and we have a SAM4 chip, what a concept! */
3073 
3074  /* auto-probe other banks, 0 done above */
3075  for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3076  /* skip banks not present */
3077  if (!(chip->details.bank[x].present))
3078  continue;
3079 
3080  if (!chip->details.bank[x].bank)
3081  goto need_define;
3082 
3083  if (chip->details.bank[x].probed)
3084  continue;
3085 
3086  r = sam4_auto_probe(chip->details.bank[x].bank);
3087  if (r != ERROR_OK)
3088  return r;
3089  }
3090 
3091  r = sam4_get_info(chip);
3092  if (r != ERROR_OK) {
3093  LOG_DEBUG("Sam4Info, Failed %d", r);
3094  return r;
3095  }
3096 
3097  return ERROR_OK;
3098 }
3099 
3100 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3101 {
3102  unsigned x, v;
3103  int r, who;
3104  struct sam4_chip *chip;
3105 
3106  chip = get_current_sam4(CMD);
3107  if (!chip)
3108  return ERROR_OK;
3109 
3110  if (chip->target->state != TARGET_HALTED) {
3111  LOG_ERROR("sam4 - target not halted");
3112  return ERROR_TARGET_NOT_HALTED;
3113  }
3114 
3115  if (!chip->details.bank[0].bank) {
3116  command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3117  at91sam4_flash.name);
3118  return ERROR_FAIL;
3119  }
3120  if (!chip->details.bank[0].probed) {
3121  r = sam4_auto_probe(chip->details.bank[0].bank);
3122  if (r != ERROR_OK)
3123  return r;
3124  }
3125 
3126  switch (CMD_ARGC) {
3127  default:
3128  return ERROR_COMMAND_SYNTAX_ERROR;
3129  case 0:
3130  goto showall;
3131  case 1:
3132  who = -1;
3133  break;
3134  case 2:
3135  if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
3136  who = -1;
3137  else {
3138  uint32_t v32;
3139  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3140  who = v32;
3141  }
3142  break;
3143  }
3144 
3145  if (strcmp("show", CMD_ARGV[0]) == 0) {
3146  if (who == -1) {
3147 showall:
3148  r = ERROR_OK;
3149  for (x = 0; x < chip->details.n_gpnvms; x++) {
3150  r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3151  if (r != ERROR_OK)
3152  break;
3153  command_print(CMD, "sam4-gpnvm%u: %u", x, v);
3154  }
3155  return r;
3156  }
3157  if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3158  r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3159  if (r == ERROR_OK)
3160  command_print(CMD, "sam4-gpnvm%u: %u", who, v);
3161  return r;
3162  } else {
3163  command_print(CMD, "sam4-gpnvm invalid GPNVM: %u", who);
3164  return ERROR_COMMAND_SYNTAX_ERROR;
3165  }
3166  }
3167 
3168  if (who == -1) {
3169  command_print(CMD, "Missing GPNVM number");
3170  return ERROR_COMMAND_SYNTAX_ERROR;
3171  }
3172 
3173  if (strcmp("set", CMD_ARGV[0]) == 0)
3174  r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3175  else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3176  (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3177  r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3178  else {
3179  command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3180  r = ERROR_COMMAND_SYNTAX_ERROR;
3181  }
3182  return r;
3183 }
3184 
3185 COMMAND_HANDLER(sam4_handle_slowclk_command)
3186 {
3187  struct sam4_chip *chip;
3188 
3189  chip = get_current_sam4(CMD);
3190  if (!chip)
3191  return ERROR_OK;
3192 
3193  switch (CMD_ARGC) {
3194  case 0:
3195  /* show */
3196  break;
3197  case 1:
3198  {
3199  /* set */
3200  uint32_t v;
3201  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3202  if (v > 200000) {
3203  /* absurd slow clock of 200Khz? */
3204  command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3205  return ERROR_COMMAND_SYNTAX_ERROR;
3206  }
3207  chip->cfg.slow_freq = v;
3208  break;
3209  }
3210  default:
3211  /* error */
3212  command_print(CMD, "Too many parameters");
3213  return ERROR_COMMAND_SYNTAX_ERROR;
3214  }
3215  command_print(CMD, "Slowclk freq: %d.%03dkhz",
3216  (int)(chip->cfg.slow_freq / 1000),
3217  (int)(chip->cfg.slow_freq % 1000));
3218  return ERROR_OK;
3219 }
3220 
3221 static const struct command_registration at91sam4_exec_command_handlers[] = {
3222  {
3223  .name = "gpnvm",
3224  .handler = sam4_handle_gpnvm_command,
3225  .mode = COMMAND_EXEC,
3226  .usage = "[('clr'|'set'|'show') bitnum]",
3227  .help = "Without arguments, shows all bits in the gpnvm "
3228  "register. Otherwise, clears, sets, or shows one "
3229  "General Purpose Non-Volatile Memory (gpnvm) bit.",
3230  },
3231  {
3232  .name = "info",
3233  .handler = sam4_handle_info_command,
3234  .mode = COMMAND_EXEC,
3235  .help = "Print information about the current at91sam4 chip "
3236  "and its flash configuration.",
3237  .usage = "",
3238  },
3239  {
3240  .name = "slowclk",
3241  .handler = sam4_handle_slowclk_command,
3242  .mode = COMMAND_EXEC,
3243  .usage = "[clock_hz]",
3244  .help = "Display or set the slowclock frequency "
3245  "(default 32768 Hz).",
3246  },
3247  COMMAND_REGISTRATION_DONE
3248 };
3249 static const struct command_registration at91sam4_command_handlers[] = {
3250  {
3251  .name = "at91sam4",
3252  .mode = COMMAND_ANY,
3253  .help = "at91sam4 flash command group",
3254  .usage = "",
3255  .chain = at91sam4_exec_command_handlers,
3256  },
3257  COMMAND_REGISTRATION_DONE
3258 };
3259 
3260 const struct flash_driver at91sam4_flash = {
3261  .name = "at91sam4",
3262  .commands = at91sam4_command_handlers,
3263  .flash_bank_command = sam4_flash_bank_command,
3264  .erase = sam4_erase,
3265  .protect = sam4_protect,
3266  .write = sam4_write,
3267  .read = default_flash_read,
3268  .probe = sam4_probe,
3269  .auto_probe = sam4_auto_probe,
3270  .erase_check = default_flash_blank_check,
3271  .protect_check = sam4_protect_check,
3272  .info = sam4_info,
3273  .free_driver_priv = sam4_free_driver_priv,
3274 };
FLASH_BANK0_BASE_C32
#define FLASH_BANK0_BASE_C32
Definition: at91sam4.c:39
efc_start_command
static int efc_start_command(struct sam4_bank_private *private, unsigned command, unsigned argument)
Definition: at91sam4.c:1483
FLASH_BANK1_BASE_2048K_SD
#define FLASH_BANK1_BASE_2048K_SD
Definition: at91sam4.c:36
AT91C_EFC_FCMD_WPL
#define AT91C_EFC_FCMD_WPL
Definition: at91sam4.c:44
AT91C_EFC_FCMD_GLB
#define AT91C_EFC_FCMD_GLB
Definition: at91sam4.c:53
FLASH_BANK_BASE_S
#define FLASH_BANK_BASE_S
Definition: at91sam4.c:28
sam4_get_reg
static const struct sam4_reg_list * sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
Given a pointer to where it goes in the structure, determine the register name, address from the all ...
Definition: at91sam4.c:2341
eproc_names
static const char *const eproc_names[]
Definition: at91sam4.c:1937
AT91C_EFC_FCMD_EWPL
#define AT91C_EFC_FCMD_EWPL
Definition: at91sam4.c:46
flashd_get_gpnvm
static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere)
Gets current GPNVM state.
Definition: at91sam4.c:1721
efc_perform_command
static int efc_perform_command(struct sam4_bank_private *private, unsigned command, unsigned argument, uint32_t *status)
Performs the given command and wait until its completion (or an error).
Definition: at91sam4.c:1578
all_sam4_details
static const struct sam4_chip_details all_sam4_details[]
Definition: at91sam4.c:224
REG_NAME_WIDTH
#define REG_NAME_WIDTH
Definition: at91sam4.c:25
flashd_lock
static int flashd_lock(struct sam4_bank_private *private, unsigned start_sector, unsigned end_sector)
Locks regions.
Definition: at91sam4.c:1880
sam4_write
static int sam4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: at91sam4.c:2890
COMMAND_HANDLER
COMMAND_HANDLER(sam4_handle_info_command)
Definition: at91sam4.c:3043
sam4_info
static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: at91sam4.c:2618
sam4_explain_chipid_cidr
static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
Definition: at91sam4.c:2112
_unknown
static const char _unknown[]
Definition: at91sam4.c:1936
OFFSET_EFC_FRR
#define OFFSET_EFC_FRR
Definition: at91sam4.c:63
sam4_auto_probe
static int sam4_auto_probe(struct flash_bank *bank)
Definition: at91sam4.c:2711
_yes_or_no
static const char * _yes_or_no(uint32_t v)
Definition: at91sam4.c:2056
get_sam4_bank_private
static struct sam4_bank_private * get_sam4_bank_private(struct flash_bank *bank)
Definition: at91sam4.c:2332
sam4_explain_ckgr_plla
static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
Definition: at91sam4.c:2169
AT91C_EFC_FCMD_SFB
#define AT91C_EFC_FCMD_SFB
Definition: at91sam4.c:54
sam4_reg_fieldname
static uint32_t sam4_reg_fieldname(struct sam4_chip *chip, const char *regname, uint32_t value, unsigned shift, unsigned width)
Definition: at91sam4.c:1907
AT91C_EFC_FCMD_EA
#define AT91C_EFC_FCMD_EA
Definition: at91sam4.c:47
sam4_get_details
static int sam4_get_details(struct sam4_bank_private *private)
Definition: at91sam4.c:2557
FLASH_BANK1_BASE_1024K_SD
#define FLASH_BANK1_BASE_1024K_SD
Definition: at91sam4.c:34
AT91C_EFC_FCMD_EPA
#define AT91C_EFC_FCMD_EPA
Definition: at91sam4.c:50
all_sam4_chips
static struct sam4_chip * all_sam4_chips
Definition: at91sam4.c:188
sam4_read_this_reg
static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
Definition: at91sam4.c:2368
AT91C_EFC_FCMD_GFB
#define AT91C_EFC_FCMD_GFB
Definition: at91sam4.c:56
sam4_explain_ckgr_mor
static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
Definition: at91sam4.c:2068
SAM4_ENTRY
#define SAM4_ENTRY(NAME, FUNC)
Definition: at91sam4.c:2307
sam4_get_reg_ptr
static uint32_t * sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
Definition: at91sam4.c:2294
FLASH_BANK_BASE_C
#define FLASH_BANK_BASE_C
Definition: at91sam4.c:29
flashd_set_gpnvm
static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
Sets the selected GPNVM bit.
Definition: at91sam4.c:1794
sam4_all_regs
static const struct sam4_reg_list sam4_all_regs[]
Definition: at91sam4.c:2310
sam4_protect_check
static int sam4_protect_check(struct flash_bank *bank)
Definition: at91sam4.c:2445
get_current_sam4
static struct sam4_chip * get_current_sam4(struct command_invocation *cmd)
Definition: at91sam4.c:190
efc_get_status
static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
Get the current status of the EEFC and the value of some status bits (LOCKE, PROGE).
Definition: at91sam4.c:1450
nvpsize
static const char *const nvpsize[]
Definition: at91sam4.c:1957
sam4_explain_mckr
static void sam4_explain_mckr(struct sam4_chip *chip)
Definition: at91sam4.c:2189
AT91C_EFC_FCMD_EWP
#define AT91C_EFC_FCMD_EWP
Definition: at91sam4.c:45
_tomhz
static float _tomhz(uint32_t freq_hz)
Definition: at91sam4.c:67
sam4_page_write
static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf)
Definition: at91sam4.c:2846
at91sam4_exec_command_handlers
static const struct command_registration at91sam4_exec_command_handlers[]
Definition: at91sam4.c:3221
AT91C_EFC_FCMD_WP
#define AT91C_EFC_FCMD_WP
Definition: at91sam4.c:43
flashd_get_lock_bits
static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
Returns a bit field (at most 64) of locked regions within a page.
Definition: at91sam4.c:1828
sam4_page_read
static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf)
Definition: at91sam4.c:2801
flashd_read_uid
static int flashd_read_uid(struct sam4_bank_private *private)
Read the unique ID.
Definition: at91sam4.c:1622
SAM4_MAX_FLASH_BANKS
#define SAM4_MAX_FLASH_BANKS
Definition: at91sam4.c:167
flashd_clr_gpnvm
static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
Clears the selected GPNVM bit.
Definition: at91sam4.c:1762
at91sam4_command_handlers
static const struct command_registration at91sam4_command_handlers[]
Definition: at91sam4.c:3249
nvptype
static const char *const nvptype[]
Definition: at91sam4.c:2045
FLASH_BANK1_BASE_C32
#define FLASH_BANK1_BASE_C32
Definition: at91sam4.c:40
sam4_explain_ckgr_mcfr
static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
Definition: at91sam4.c:2151
OFFSET_EFC_FCR
#define OFFSET_EFC_FCR
Definition: at91sam4.c:61
FLASH_BANK0_BASE_SD
#define FLASH_BANK0_BASE_SD
Definition: at91sam4.c:32
SAM4_N_NVM_BITS
#define SAM4_N_NVM_BITS
Definition: at91sam4.c:162
nvpsize2
#define nvpsize2
Definition: at91sam4.c:1956
OFFSET_EFC_FSR
#define OFFSET_EFC_FSR
Definition: at91sam4.c:62
sam4_set_wait
static int sam4_set_wait(struct sam4_bank_private *private)
Definition: at91sam4.c:2820
AT91C_EFC_FCMD_STUI
#define AT91C_EFC_FCMD_STUI
Definition: at91sam4.c:57
sam4_free_driver_priv
static void sam4_free_driver_priv(struct flash_bank *bank)
Remove all chips from the internal list without distinguishing which one is owned by this bank.
Definition: at91sam4.c:2546
AT91C_EFC_FCMD_GETD
#define AT91C_EFC_FCMD_GETD
Definition: at91sam4.c:42
flashd_erase_pages
static int flashd_erase_pages(struct sam4_bank_private *private, int first_page, int num_pages, uint32_t *status)
Erases the entire flash.
Definition: at91sam4.c:1675
sam4_protect
static int sam4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: at91sam4.c:2775
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
Definition: at91sam4.c:2478
efc_get_result
static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
Get the result of the last executed command.
Definition: at91sam4.c:1470
sam4_read_all_regs
static int sam4_read_all_regs(struct sam4_chip *chip)
Definition: at91sam4.c:2385
sramsize
static const char *const sramsize[]
Definition: at91sam4.c:1976
at91sam4_flash
const struct flash_driver at91sam4_flash
Definition: at91sam4.c:3260
sam4_probe
static int sam4_probe(struct flash_bank *bank)
Definition: at91sam4.c:2636
AT91C_EFC_FCMD_SPUI
#define AT91C_EFC_FCMD_SPUI
Definition: at91sam4.c:58
AT91C_EFC_FCMD_CLB
#define AT91C_EFC_FCMD_CLB
Definition: at91sam4.c:52
flashd_erase_entire_bank
static int flashd_erase_entire_bank(struct sam4_bank_private *private)
Erases the entire flash.
Definition: at91sam4.c:1662
sam4_get_info
static int sam4_get_info(struct sam4_chip *chip)
Definition: at91sam4.c:2405
AT91C_EFC_FCMD_SLB
#define AT91C_EFC_FCMD_SLB
Definition: at91sam4.c:51
flashd_unlock
static int flashd_unlock(struct sam4_bank_private *private, unsigned start_sector, unsigned end_sector)
Unlocks all the regions in the given address range.
Definition: at91sam4.c:1850
sam4_erase
static int sam4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: at91sam4.c:2722
_rc_freq
static const char *const _rc_freq[]
Definition: at91sam4.c:2064
AT91C_EFC_FCMD_CFB
#define AT91C_EFC_FCMD_CFB
Definition: at91sam4.c:55
CKGR_MOR
#define CKGR_MOR
Definition: at91sam7.c:45
PMC_MCKR
#define PMC_MCKR
Definition: at91sam7.c:50
CKGR_MCFR
#define CKGR_MCFR
Definition: at91sam7.c:44
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:450
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
width
unsigned short width
Definition: embeddedice.c:47
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_NOT_PROBED
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:380
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:126
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:161
LOG_USER_N
#define LOG_USER_N(expr ...)
Definition: log.h:129
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:123
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:117
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:109
ERROR_OK
#define ERROR_OK
Definition: log.h:155
archnames::name
const char * name
Definition: at91sam3.c:2496
archnames::value
unsigned value
Definition: at91sam3.c:2496
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:228
command_registration::name
const char * name
Definition: command.h:229
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
reg
Definition: register.h:111
reg::name
const char * name
Definition: register.h:113
sam4_bank_private
Definition: at91sam4.c:127
sam4_bank_private::controller_address
uint32_t controller_address
Definition: at91sam4.c:140
sam4_bank_private::nsectors
unsigned nsectors
Definition: at91sam4.c:145
sam4_bank_private::size_bytes
unsigned size_bytes
Definition: at91sam4.c:144
sam4_bank_private::chip
struct sam4_chip * chip
Definition: at91sam4.c:136
sam4_bank_private::probed
bool probed
Definition: at91sam4.c:128
sam4_bank_private::sector_size
unsigned sector_size
Definition: at91sam4.c:146
sam4_bank_private::base_address
uint32_t base_address
Definition: at91sam4.c:141
sam4_bank_private::flash_wait_states
uint32_t flash_wait_states
Definition: at91sam4.c:142
sam4_bank_private::page_size
unsigned page_size
Definition: at91sam4.c:147
sam4_bank_private::present
bool present
Definition: at91sam4.c:143
sam4_bank_private::bank
struct flash_bank * bank
Definition: at91sam4.c:138
sam4_bank_private::bank_number
unsigned bank_number
Definition: at91sam4.c:139
sam4_cfg
Definition: at91sam4.c:76
sam4_cfg::rc_freq
uint32_t rc_freq
Definition: at91sam4.c:80
sam4_cfg::unique_id
uint32_t unique_id[4]
Definition: at91sam4.c:77
sam4_cfg::fclk_freq
uint32_t fclk_freq
Definition: at91sam4.c:85
sam4_cfg::PMC_IMR
uint32_t PMC_IMR
Definition: at91sam4.c:120
sam4_cfg::CHIPID_CIDR
uint32_t CHIPID_CIDR
Definition: at91sam4.c:92
sam4_cfg::CKGR_UCKR
uint32_t CKGR_UCKR
Definition: at91sam4.c:102
sam4_cfg::PMC_MCKR
uint32_t PMC_MCKR
Definition: at91sam4.c:110
sam4_cfg::PMC_FSPR
uint32_t PMC_FSPR
Definition: at91sam4.c:124
sam4_cfg::PMC_PCK2
uint32_t PMC_PCK2
Definition: at91sam4.c:116
sam4_cfg::mainosc_freq
uint32_t mainosc_freq
Definition: at91sam4.c:81
sam4_cfg::pclk2_freq
uint32_t pclk2_freq
Definition: at91sam4.c:88
sam4_cfg::pclk0_freq
uint32_t pclk0_freq
Definition: at91sam4.c:86
sam4_cfg::mclk_freq
uint32_t mclk_freq
Definition: at91sam4.c:83
sam4_cfg::pclk1_freq
uint32_t pclk1_freq
Definition: at91sam4.c:87
sam4_cfg::slow_freq
uint32_t slow_freq
Definition: at91sam4.c:79
sam4_cfg::PMC_PCK0
uint32_t PMC_PCK0
Definition: at91sam4.c:112
sam4_cfg::CHIPID_EXID
uint32_t CHIPID_EXID
Definition: at91sam4.c:94
sam4_cfg::cpu_freq
uint32_t cpu_freq
Definition: at91sam4.c:84
sam4_cfg::PMC_FSMR
uint32_t PMC_FSMR
Definition: at91sam4.c:122
sam4_cfg::plla_freq
uint32_t plla_freq
Definition: at91sam4.c:82
sam4_cfg::PMC_SCSR
uint32_t PMC_SCSR
Definition: at91sam4.c:98
sam4_cfg::CKGR_MCFR
uint32_t CKGR_MCFR
Definition: at91sam4.c:106
sam4_cfg::CKGR_PLLAR
uint32_t CKGR_PLLAR
Definition: at91sam4.c:108
sam4_cfg::CKGR_MOR
uint32_t CKGR_MOR
Definition: at91sam4.c:104
sam4_cfg::PMC_PCK1
uint32_t PMC_PCK1
Definition: at91sam4.c:114
sam4_cfg::PMC_PCSR
uint32_t PMC_PCSR
Definition: at91sam4.c:100
sam4_cfg::PMC_SR
uint32_t PMC_SR
Definition: at91sam4.c:118
sam4_chip_details
Definition: at91sam4.c:150
sam4_chip_details::chipid_cidr
uint32_t chipid_cidr
Definition: at91sam4.c:158
sam4_chip_details::n_banks
unsigned n_banks
Definition: at91sam4.c:166
sam4_chip_details::n_gpnvms
unsigned n_gpnvms
Definition: at91sam4.c:161
sam4_chip_details::total_sram_size
unsigned total_sram_size
Definition: at91sam4.c:165
sam4_chip_details::name
const char * name
Definition: at91sam4.c:159
sam4_chip_details::bank
struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS]
Definition: at91sam4.c:169
sam4_chip_details::total_flash_size
unsigned total_flash_size
Definition: at91sam4.c:164
sam4_chip_details::gpnvm
unsigned gpnvm[SAM4_N_NVM_BITS]
Definition: at91sam4.c:163
sam4_chip
Definition: at91sam4.c:172
sam4_chip::probed
bool probed
Definition: at91sam4.c:174
sam4_chip::cfg
struct sam4_cfg cfg
Definition: at91sam4.c:179
sam4_chip::details
struct sam4_chip_details details
Definition: at91sam4.c:177
sam4_chip::next
struct sam4_chip * next
Definition: at91sam4.c:173
sam4_chip::target
struct target * target
Definition: at91sam4.c:178
sam4_reg_list
Definition: at91sam4.c:183
sam4_reg_list::name
const char * name
Definition: at91sam4.c:184
sam4_reg_list::struct_offset
size_t struct_offset
Definition: at91sam4.c:184
sam4_reg_list::address
uint32_t address
Definition: at91sam4.c:184
sam4_reg_list::explain_func
void(* explain_func)(struct sam4_chip *chip)
Definition: at91sam4.c:185
target
Definition: target.h:120
target::state
enum target_state state
Definition: target.h:162
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1334
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2616
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1306
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:536
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:792
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:55
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:342
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22