OpenOCD
armv4_5.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2009 by Øyvind Harboe *
11  * oyvind.harboe@zylin.com *
12  ***************************************************************************/
13 
14 #ifndef OPENOCD_TARGET_ARMV4_5_H
15 #define OPENOCD_TARGET_ARMV4_5_H
16 
17 /* This stuff "knows" that its callers aren't talking
18  * to microcontroller profile (current Cortex-M) parts.
19  * We want to phase it out so core code can be shared.
20  */
21 
22 /* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
23  * index into the armv4_5_core_reg_map array. Its remaining users are
24  * remnants which could as easily walk * the register cache directly as
25  * use the expensive ARMV4_5_CORE_REG_MODE() macro.
26  */
29 
30 extern const int armv4_5_core_reg_map[9][17];
31 
32 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
33  (cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
34 
35 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
36 enum { ARMV4_5_CPSR = 31, };
37 
38 #endif /* OPENOCD_TARGET_ARMV4_5_H */
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
enum arm_mode mode
Definition: armv4_5.c:277
int arm_mode_to_number(enum arm_mode mode)
Map PSR mode bits to linear number indexing armv4_5_core_reg_map.
Definition: armv4_5.c:192
@ ARMV4_5_CPSR
Definition: armv4_5.h:36
const int armv4_5_core_reg_map[9][17]
Definition: armv4_5.c:403
enum arm_mode armv4_5_number_to_mode(int number)
Map linear number indexing armv4_5_core_reg_map to PSR mode bits.
Definition: armv4_5.c:223
enum esirisc_reg_num number
Definition: esirisc.c:87