OpenOCD
arc_jtag.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2013-2014,2019-2020 Synopsys, Inc. *
5  * Frank Dols <frank.dols@synopsys.com> *
6  * Mischa Jonker <mischa.jonker@synopsys.com> *
7  * Anton Kolesov <anton.kolesov@synopsys.com> *
8  * Evgeniy Didin <didin@synopsys.com> *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "arc.h"
16 
17 /*
18  * This functions sets instruction register in TAP. TAP end state is always
19  * IRPAUSE.
20  *
21  * @param jtag_info
22  * @param new_instr Instruction to write to instruction register.
23  */
24 static void arc_jtag_enque_write_ir(struct arc_jtag *jtag_info, uint32_t
25  new_instr)
26 {
27  uint32_t current_instr;
28  struct jtag_tap *tap;
29  uint8_t instr_buffer[sizeof(uint32_t)] = {0};
30 
31  assert(jtag_info);
32  assert(jtag_info->tap);
33 
34  tap = jtag_info->tap;
35 
36  /* Do not set instruction if it is the same as current. */
37  current_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length);
38  if (current_instr == new_instr)
39  return;
40 
41  struct scan_field field = {
42  .num_bits = tap->ir_length,
43  .out_value = instr_buffer
44  };
45  buf_set_u32(instr_buffer, 0, field.num_bits, new_instr);
46 
47  /* From code in src/jtag/drivers/driver.c it look like that fields are
48  * copied so it is OK that field in this function is allocated in stack and
49  * thus this memory will be repurposed before jtag_execute_queue() will be
50  * invoked. */
51  jtag_add_ir_scan(tap, &field, TAP_IRPAUSE);
52 }
53 
68 static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data,
69  tap_state_t end_state)
70 {
71 
72  assert(jtag_info);
73  assert(jtag_info->tap);
74 
75  struct scan_field field = {
76  .num_bits = 32,
77  .in_value = data
78  };
79 
80  jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
81 }
82 
90 static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data,
91  tap_state_t end_state)
92 {
93  uint8_t out_value[sizeof(uint32_t)] = {0};
94 
95  assert(jtag_info);
96  assert(jtag_info->tap);
97 
98  buf_set_u32(out_value, 0, 32, data);
99 
100  struct scan_field field = {
101  .num_bits = 32,
102  .out_value = out_value
103  };
104 
105  jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
106 }
107 
108 
118 static void arc_jtag_enque_set_transaction(struct arc_jtag *jtag_info,
119  uint32_t new_trans, tap_state_t end_state)
120 {
121  uint8_t out_value[sizeof(uint32_t)] = {0};
122 
123  assert(jtag_info);
124  assert(jtag_info->tap);
125 
126  /* No need to do anything. */
127  if (jtag_info->cur_trans == new_trans)
128  return;
129 
130  /* Set instruction. We used to call write_ir at upper levels, however
131  * write_ir-write_transaction were constantly in pair, so to avoid code
132  * duplication this function does it self. For this reasons it is "set"
133  * instead of "write". */
136  struct scan_field field = {
138  .out_value = out_value
139  };
140 
141  jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
142  jtag_info->cur_trans = new_trans;
143 }
144 
149 static void arc_jtag_enque_reset_transaction(struct arc_jtag *jtag_info)
150 {
152 }
153 
154 static void arc_jtag_enque_status_read(struct arc_jtag * const jtag_info,
155  uint8_t * const buffer)
156 {
157  assert(jtag_info);
158  assert(jtag_info->tap);
159  assert(buffer);
160 
161  /* first writing code(0x8) of jtag status register in IR */
163  /* Now reading dr performs jtag status register read */
165 }
166 
167 /* ----- Exported JTAG functions ------------------------------------------- */
168 
169 int arc_jtag_startup(struct arc_jtag *jtag_info)
170 {
171  assert(jtag_info);
172 
174 
175  return jtag_execute_queue();
176 }
177 
179 int arc_jtag_status(struct arc_jtag * const jtag_info, uint32_t * const value)
180 {
181  uint8_t buffer[sizeof(uint32_t)];
182 
183  assert(jtag_info);
184  assert(jtag_info->tap);
185 
186  /* Fill command queue. */
190 
191  /* Execute queue. */
193 
194  /* Parse output. */
195  *value = buf_get_u32(buffer, 0, 32);
196 
197  return ERROR_OK;
198 }
199 /* Helper function: Adding read/write register operation to queue */
200 static void arc_jtag_enque_register_rw(struct arc_jtag *jtag_info, uint32_t *addr,
201  uint8_t *read_buffer, const uint32_t *write_buffer, uint32_t count)
202 {
203  uint32_t i;
204 
205  for (i = 0; i < count; i++) {
206  /* ARC jtag has optimization which is to increment ADDRESS_REG performing
207  * each transaction. Making sequential reads/writes we can set address for
208  * only first register in sequence, and than do read/write in cycle. */
209  if (i == 0 || (addr[i] != addr[i-1] + 1)) {
211  /* Going to TAP_IDLE state we initiate jtag transaction.
212  * Reading data we must go to TAP_IDLE, because further
213  * the data would be read. In case of write we go to TAP_DRPAUSE,
214  * because we need to write data to Data register first. */
215  if (write_buffer)
216  arc_jtag_enque_write_dr(jtag_info, addr[i], TAP_DRPAUSE);
217  else
218  arc_jtag_enque_write_dr(jtag_info, addr[i], TAP_IDLE);
220  }
221  if (write_buffer)
222  arc_jtag_enque_write_dr(jtag_info, *(write_buffer + i), TAP_IDLE);
223  else
224  arc_jtag_enque_read_dr(jtag_info, read_buffer + i * 4, TAP_IDLE);
225  }
226  /* To prevent pollution of next register due to optimization it is necessary *
227  * to reset transaction */
229 }
230 
242 static int arc_jtag_write_registers(struct arc_jtag *jtag_info, uint32_t type,
243  uint32_t *addr, uint32_t count, const uint32_t *buffer)
244 {
245  LOG_DEBUG("Writing to %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32
246  ";buffer[0]=0x%08" PRIx32,
247  (type == ARC_JTAG_CORE_REG ? "core" : "aux"), *addr, count, *buffer);
248 
249  if (!count) {
250  LOG_ERROR("Trying to write 0 registers");
251  return ERROR_FAIL;
252  }
253 
255 
256  /* What registers are we writing to? */
257  const uint32_t transaction = (type == ARC_JTAG_CORE_REG ?
259  arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE);
260 
262 
263  return jtag_execute_queue();
264 }
265 
277 static int arc_jtag_read_registers(struct arc_jtag *jtag_info, uint32_t type,
278  uint32_t *addr, uint32_t count, uint32_t *buffer)
279 {
280  int retval;
281  uint32_t i;
282 
283  assert(jtag_info);
284  assert(jtag_info->tap);
285 
286  LOG_DEBUG("Reading %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32,
287  (type == ARC_JTAG_CORE_REG ? "core" : "aux"), *addr, count);
288 
289  if (!count) {
290  LOG_ERROR("Trying to read 0 registers");
291  return ERROR_FAIL;
292  }
293 
295 
296  /* What type of registers we are reading? */
297  const uint32_t transaction = (type == ARC_JTAG_CORE_REG ?
299  arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE);
300 
301  uint8_t *data_buf = calloc(sizeof(uint8_t), count * 4);
302 
303  arc_jtag_enque_register_rw(jtag_info, addr, data_buf, NULL, count);
304 
305  retval = jtag_execute_queue();
306  if (retval != ERROR_OK) {
307  LOG_ERROR("Failed to execute jtag queue: %d", retval);
308  retval = ERROR_FAIL;
309  goto exit;
310  }
311 
312  /* Convert byte-buffers to host /presentation. */
313  for (i = 0; i < count; i++)
314  buffer[i] = buf_get_u32(data_buf + 4 * i, 0, 32);
315 
316  LOG_DEBUG("Read from register: buf[0]=0x%" PRIx32, buffer[0]);
317 
318 exit:
319  free(data_buf);
320 
321  return retval;
322 }
323 
324 
326 int arc_jtag_write_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
327  uint32_t value)
328 {
329  return arc_jtag_write_core_reg(jtag_info, &addr, 1, &value);
330 }
331 
342 int arc_jtag_write_core_reg(struct arc_jtag *jtag_info, uint32_t *addr,
343  uint32_t count, const uint32_t *buffer)
344 {
346  buffer);
347 }
348 
350 int arc_jtag_read_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
351  uint32_t *value)
352 {
353  return arc_jtag_read_core_reg(jtag_info, &addr, 1, value);
354 }
355 
366 int arc_jtag_read_core_reg(struct arc_jtag *jtag_info, uint32_t *addr,
367  uint32_t count, uint32_t *buffer)
368 {
370  buffer);
371 }
372 
374 int arc_jtag_write_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
375  uint32_t value)
376 {
377  return arc_jtag_write_aux_reg(jtag_info, &addr, 1, &value);
378 }
379 
390 int arc_jtag_write_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr,
391  uint32_t count, const uint32_t *buffer)
392 {
394  buffer);
395 }
396 
398 int arc_jtag_read_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
399  uint32_t *value)
400 {
401  return arc_jtag_read_aux_reg(jtag_info, &addr, 1, value);
402 }
403 
414 int arc_jtag_read_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr,
415  uint32_t count, uint32_t *buffer)
416 {
418  buffer);
419 }
420 
436 int arc_jtag_write_memory(struct arc_jtag *jtag_info, uint32_t addr,
437  uint32_t count, const uint32_t *buffer)
438 {
439  assert(jtag_info);
440  assert(buffer);
441 
442  LOG_DEBUG("Writing to memory: addr=0x%08" PRIx32 ";count=%" PRIu32 ";buffer[0]=0x%08" PRIx32,
443  addr, count, *buffer);
444 
445  /* No need to waste time on useless operations. */
446  if (!count)
447  return ERROR_OK;
448 
449  /* We do not know where we come from. */
451 
452  /* We want to write to memory. */
454 
455  /* Set target memory address of the first word. */
458 
459  /* Start sending words. Address is auto-incremented on 4bytes by HW. */
461 
462  uint32_t i;
463  for (i = 0; i < count; i++)
464  arc_jtag_enque_write_dr(jtag_info, *(buffer + i), TAP_IDLE);
465 
466  return jtag_execute_queue();
467 }
468 
484 int arc_jtag_read_memory(struct arc_jtag *jtag_info, uint32_t addr,
485  uint32_t count, uint32_t *buffer, bool slow_memory)
486 {
487  uint8_t *data_buf;
488  uint32_t i;
489  int retval = ERROR_OK;
490 
491 
492  assert(jtag_info);
493  assert(jtag_info->tap);
494 
495  LOG_DEBUG("Reading memory: addr=0x%" PRIx32 ";count=%" PRIu32 ";slow=%c",
496  addr, count, slow_memory ? 'Y' : 'N');
497 
498  if (!count)
499  return ERROR_OK;
500 
501  data_buf = calloc(sizeof(uint8_t), count * 4);
503 
504  /* We are reading from memory. */
506 
507  /* Read data */
508  for (i = 0; i < count; i++) {
509  /* When several words are read at consequent addresses we can
510  * rely on ARC JTAG auto-incrementing address. That means that
511  * address can be set only once, for a first word. However it
512  * has been noted that at least in some cases when reading from
513  * DDR, JTAG returns 0 instead of a real value. To workaround
514  * this issue we need to do totally non-required address
515  * writes, which however resolve a problem by introducing
516  * delay. See STAR 9000832538... */
517  if (slow_memory || i == 0) {
518  /* Set address */
520  arc_jtag_enque_write_dr(jtag_info, addr + i * 4, TAP_IDLE);
521 
523  }
524  arc_jtag_enque_read_dr(jtag_info, data_buf + i * 4, TAP_IDLE);
525  }
526  retval = jtag_execute_queue();
527  if (retval != ERROR_OK) {
528  LOG_ERROR("Failed to execute jtag queue: %d", retval);
529  retval = ERROR_FAIL;
530  goto exit;
531  }
532 
533  /* Convert byte-buffers to host presentation. */
534  for (i = 0; i < count; i++)
535  buffer[i] = buf_get_u32(data_buf + 4*i, 0, 32);
536 
537 exit:
538  free(data_buf);
539 
540  return retval;
541 }
#define CHECK_RETVAL(action)
Definition: arc.h:246
int arc_jtag_startup(struct arc_jtag *jtag_info)
Definition: arc_jtag.c:169
int arc_jtag_write_core_reg(struct arc_jtag *jtag_info, uint32_t *addr, uint32_t count, const uint32_t *buffer)
Write core registers.
Definition: arc_jtag.c:342
int arc_jtag_read_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr, uint32_t *value)
Wrapper function to ease reading of one core register.
Definition: arc_jtag.c:350
int arc_jtag_status(struct arc_jtag *const jtag_info, uint32_t *const value)
Read STATUS register.
Definition: arc_jtag.c:179
int arc_jtag_read_memory(struct arc_jtag *jtag_info, uint32_t addr, uint32_t count, uint32_t *buffer, bool slow_memory)
Read a sequence of 4-byte words from target memory.
Definition: arc_jtag.c:484
int arc_jtag_write_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr, uint32_t value)
Wrapper function to ease writing of one AUX register.
Definition: arc_jtag.c:374
static void arc_jtag_enque_set_transaction(struct arc_jtag *jtag_info, uint32_t new_trans, tap_state_t end_state)
Set transaction in command register.
Definition: arc_jtag.c:118
static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data, tap_state_t end_state)
Read 4-byte word from data register.
Definition: arc_jtag.c:68
static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data, tap_state_t end_state)
Write 4-byte word to data register.
Definition: arc_jtag.c:90
int arc_jtag_write_memory(struct arc_jtag *jtag_info, uint32_t addr, uint32_t count, const uint32_t *buffer)
Write a sequence of 4-byte words into target memory.
Definition: arc_jtag.c:436
static void arc_jtag_enque_write_ir(struct arc_jtag *jtag_info, uint32_t new_instr)
Definition: arc_jtag.c:24
int arc_jtag_write_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr, uint32_t value)
Wrapper function to ease writing of one core register.
Definition: arc_jtag.c:326
static void arc_jtag_enque_register_rw(struct arc_jtag *jtag_info, uint32_t *addr, uint8_t *read_buffer, const uint32_t *write_buffer, uint32_t count)
Definition: arc_jtag.c:200
int arc_jtag_read_core_reg(struct arc_jtag *jtag_info, uint32_t *addr, uint32_t count, uint32_t *buffer)
Read core registers.
Definition: arc_jtag.c:366
static void arc_jtag_enque_reset_transaction(struct arc_jtag *jtag_info)
Run reset through transaction set.
Definition: arc_jtag.c:149
static int arc_jtag_read_registers(struct arc_jtag *jtag_info, uint32_t type, uint32_t *addr, uint32_t count, uint32_t *buffer)
Read registers.
Definition: arc_jtag.c:277
int arc_jtag_read_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr, uint32_t *value)
Wrapper function to ease reading of one AUX register.
Definition: arc_jtag.c:398
static int arc_jtag_write_registers(struct arc_jtag *jtag_info, uint32_t type, uint32_t *addr, uint32_t count, const uint32_t *buffer)
Write registers.
Definition: arc_jtag.c:242
int arc_jtag_write_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr, uint32_t count, const uint32_t *buffer)
Write AUX registers.
Definition: arc_jtag.c:390
static void arc_jtag_enque_status_read(struct arc_jtag *const jtag_info, uint8_t *const buffer)
Definition: arc_jtag.c:154
int arc_jtag_read_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr, uint32_t count, uint32_t *buffer)
Read AUX registers.
Definition: arc_jtag.c:414
#define ARC_JTAG_READ_FROM_CORE_REG
Definition: arc_jtag.h:31
#define ARC_JTAG_WRITE_TO_AUX_REG
Definition: arc_jtag.h:28
#define ARC_JTAG_DATA_REG
Definition: arc_jtag.h:20
#define ARC_JTAG_ADDRESS_REG
Definition: arc_jtag.h:19
#define ARC_TRANSACTION_CMD_REG
Definition: arc_jtag.h:14
#define ARC_JTAG_AUX_REG
Definition: arc_jtag.h:35
#define ARC_JTAG_WRITE_TO_CORE_REG
Definition: arc_jtag.h:27
#define ARC_JTAG_CMD_NOP
Definition: arc_jtag.h:29
#define ARC_JTAG_WRITE_TO_MEMORY
Definition: arc_jtag.h:26
#define ARC_JTAG_STATUS_REG
Definition: arc_jtag.h:18
#define ARC_JTAG_CORE_REG
Definition: arc_jtag.h:34
#define ARC_JTAG_READ_FROM_MEMORY
Definition: arc_jtag.h:30
#define ARC_TRANSACTION_CMD_REG_LENGTH
Definition: arc_jtag.h:15
#define ARC_JTAG_READ_FROM_AUX_REG
Definition: arc_jtag.h:32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
uint8_t type
Definition: esp_usb_jtag.c:0
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
Definition: jtag/core.c:374
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
@ TAP_DRPAUSE
Definition: jtag.h:43
@ TAP_IDLE
Definition: jtag.h:52
@ TAP_IRPAUSE
Definition: jtag.h:51
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
uint32_t addr
Definition: nuttx.c:65
struct jtag_tap * tap
Definition: arc_jtag.h:39
uint32_t cur_trans
Definition: arc_jtag.h:40
Definition: jtag.h:100
uint8_t * cur_instr
current instruction
Definition: jtag.h:131
int ir_length
size of instruction register
Definition: jtag.h:109
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
#define NULL
Definition: usb.h:16
uint8_t count[4]
Definition: vdebug.c:22