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Functions | |
| static void | init_shared_reg_info (struct target *target) |
| struct reg * | riscv_reg_impl_cache_entry (const struct target *target, uint32_t number) |
| Return the entry in the register cache of the target. More... | |
| int | riscv_reg_impl_expose_csrs (const struct target *target) |
Expose additional CSRs, as specified by riscv_info_t::expose_csr list. More... | |
| static bool | riscv_reg_impl_gdb_regno_cacheable (enum gdb_regno regno, bool is_write) |
| If write is true: return true iff we are guaranteed that the register will contain exactly the value we just wrote when it's read. More... | |
| bool | riscv_reg_impl_gdb_regno_exist (const struct target *target, uint32_t regno) |
| For most registers, returns whether they exist or not. More... | |
| struct target * | riscv_reg_impl_get_target (const struct reg *reg) |
| Return the target that owns the cache entry. More... | |
| void | riscv_reg_impl_hide_csrs (const struct target *target) |
Hide additional CSRs, as specified by riscv_info_t::hide_csr list. More... | |
| int | riscv_reg_impl_init_cache (struct target *target) |
| Initialize register cache. More... | |
| int | riscv_reg_impl_init_cache_entry (struct target *target, uint32_t regno, bool exist, const struct reg_arch_type *reg_type) |
| Initialize register. More... | |
| static void | riscv_reg_impl_init_vector_reg_type (const struct target *target) |
TODO: vector register type description can be moved into riscv013_info_t, since 0.11 targets do not support access to vector registers. More... | |
| static bool | riscv_reg_impl_is_initialized (const struct reg *reg) |
| This file describes the helpers to use during register cache initialization of a RISC-V target. More... | |
| int | riscv_reg_impl_set_exist (const struct target *target, uint32_t regno, bool exist) |
| Mark register as existing or not. More... | |
Function Documentation
◆ init_shared_reg_info()
|
inlinestatic |
Definition at line 60 of file riscv_reg_impl.h.
References info, RISCV_INFO, and target.
Referenced by riscv011_reg_init_all(), and riscv013_reg_examine_all().
◆ riscv_reg_impl_cache_entry()
Return the entry in the register cache of the target.
Definition at line 571 of file riscv_reg.c.
References reg_cache::num_regs, number, target::reg_cache, and reg_cache::reg_list.
Referenced by init_cache_entry(), reg_exists(), resize_reg(), riscv011_reg_init_all(), riscv013_reg_save(), riscv_reg_cache_any_dirty(), riscv_reg_flush_all(), riscv_reg_get(), riscv_reg_impl_expose_csrs(), riscv_reg_impl_hide_csrs(), riscv_reg_impl_init_cache_entry(), riscv_reg_impl_set_exist(), and riscv_set_or_write_register().
◆ riscv_reg_impl_expose_csrs()
| int riscv_reg_impl_expose_csrs | ( | const struct target * | target | ) |
Expose additional CSRs, as specified by riscv_info_t::expose_csr list.
Definition at line 709 of file riscv_reg.c.
References ERROR_FAIL, ERROR_OK, reg::exist, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, range_list_t::high, info, list_for_each_entry, LOG_TARGET_DEBUG, LOG_TARGET_WARNING, range_list_t::low, reg::name, RISCV_INFO, riscv_reg_impl_cache_entry(), and riscv_reg_impl_set_exist().
Referenced by riscv011_reg_init_all(), and riscv013_reg_examine_all().
◆ riscv_reg_impl_gdb_regno_cacheable()
|
inlinestatic |
If write is true: return true iff we are guaranteed that the register will contain exactly the value we just wrote when it's read.
If write is false: return true iff we are guaranteed that the register will read the same value in the future as the value we just read.
Definition at line 182 of file riscv_reg_impl.h.
References GDB_REGNO_DCSR, GDB_REGNO_DPC, GDB_REGNO_DSCRATCH0, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_MEPC, GDB_REGNO_MISA, GDB_REGNO_SATP, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, GDB_REGNO_TSELECT, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_VL, GDB_REGNO_VLENB, GDB_REGNO_VSTART, GDB_REGNO_VTYPE, GDB_REGNO_VXRM, GDB_REGNO_VXSAT, GDB_REGNO_XPR31, and GDB_REGNO_ZERO.
Referenced by riscv013_reg_get(), riscv013_reg_save(), riscv013_reg_set(), riscv_reg_get(), and riscv_set_or_write_register().
◆ riscv_reg_impl_gdb_regno_exist()
| bool riscv_reg_impl_gdb_regno_exist | ( | const struct target * | target, |
| uint32_t | regno | ||
| ) |
For most registers, returns whether they exist or not.
For some registers the "exist" bit should be set explicitly.
Definition at line 368 of file riscv_reg.c.
References CSR_CYCLEH, CSR_FCSR, CSR_FFLAGS, CSR_FRM, CSR_HIDELEGH, CSR_HPMCOUNTER10H, CSR_HPMCOUNTER11H, CSR_HPMCOUNTER12H, CSR_HPMCOUNTER13H, CSR_HPMCOUNTER14H, CSR_HPMCOUNTER15H, CSR_HPMCOUNTER16H, CSR_HPMCOUNTER17H, CSR_HPMCOUNTER18H, CSR_HPMCOUNTER19H, CSR_HPMCOUNTER20H, CSR_HPMCOUNTER21H, CSR_HPMCOUNTER22H, CSR_HPMCOUNTER23H, CSR_HPMCOUNTER24H, CSR_HPMCOUNTER25H, CSR_HPMCOUNTER26H, CSR_HPMCOUNTER27H, CSR_HPMCOUNTER28H, CSR_HPMCOUNTER29H, CSR_HPMCOUNTER30H, CSR_HPMCOUNTER31H, CSR_HPMCOUNTER3H, CSR_HPMCOUNTER4H, CSR_HPMCOUNTER5H, CSR_HPMCOUNTER6H, CSR_HPMCOUNTER7H, CSR_HPMCOUNTER8H, CSR_HPMCOUNTER9H, CSR_HVICTL, CSR_HVIEN, CSR_HVIENH, CSR_HVIPH, CSR_HVIPRIO1, CSR_HVIPRIO1H, CSR_HVIPRIO2, CSR_HVIPRIO2H, CSR_INSTRETH, CSR_MCOUNTEREN, CSR_MCYCLEH, CSR_MEDELEG, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MIDELEG, CSR_MIDELEGH, CSR_MIEH, CSR_MINSTRETH, CSR_MIPH, CSR_MIREG, CSR_MISELECT, CSR_MVIEN, CSR_MVIENH, CSR_MVIP, CSR_MVIPH, CSR_PMPCFG1, CSR_PMPCFG3, CSR_SATP, CSR_SCAUSE, CSR_SCOUNTEREN, CSR_SEPC, CSR_SIE, CSR_SIEH, CSR_SIP, CSR_SIPH, CSR_SIREG, CSR_SISELECT, CSR_SSCRATCH, CSR_SSTATUS, CSR_STOPEI, CSR_STOPI, CSR_STVAL, CSR_STVEC, CSR_TIMEH, CSR_VCSR, CSR_VL, CSR_VSIEH, CSR_VSIPH, CSR_VSIREG, CSR_VSISELECT, CSR_VSTART, CSR_VSTOPEI, CSR_VSTOPI, CSR_VTYPE, CSR_VXRM, CSR_VXSAT, GDB_REGNO_COUNT, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_MTOPEI, GDB_REGNO_MTOPI, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_VLENB, GDB_REGNO_XPR15, GDB_REGNO_XPR31, is_known_standard_csr(), reg_exists(), riscv_supports_extension(), riscv_xlen(), and vlenb_exists().
Referenced by init_cache_entry(), and riscv011_reg_init_all().
◆ riscv_reg_impl_get_target()
Return the target that owns the cache entry.
Definition at line 207 of file riscv_reg.c.
References reg::arch_info, and riscv_reg_impl_is_initialized().
Referenced by riscv011_reg_get(), riscv011_reg_set(), riscv013_reg_get(), and riscv013_reg_set().
◆ riscv_reg_impl_hide_csrs()
| void riscv_reg_impl_hide_csrs | ( | const struct target * | target | ) |
Hide additional CSRs, as specified by riscv_info_t::hide_csr list.
Definition at line 736 of file riscv_reg.c.
References reg::exist, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, reg::hidden, range_list_t::high, info, list_for_each_entry, LOG_TARGET_DEBUG, range_list_t::low, reg::name, RISCV_INFO, and riscv_reg_impl_cache_entry().
Referenced by riscv011_reg_init_all(), and riscv013_reg_examine_all().
◆ riscv_reg_impl_init_cache()
| int riscv_reg_impl_init_cache | ( | struct target * | target | ) |
Initialize register cache.
Note, that each specific register cache entry is not initialized by this function.
Definition at line 678 of file riscv_reg.c.
References ERROR_FAIL, ERROR_OK, GDB_REGNO_COUNT, info, init_custom_register_names(), LOG_TARGET_DEBUG, LOG_TARGET_ERROR, reg_cache::name, reg_cache::num_regs, target::reg_cache, reg_cache::reg_list, RISCV_INFO, and riscv_reg_free_all().
Referenced by riscv011_reg_init_all(), and riscv013_reg_examine_all().
◆ riscv_reg_impl_init_cache_entry()
| int riscv_reg_impl_init_cache_entry | ( | struct target * | target, |
| uint32_t | regno, | ||
| bool | exist, | ||
| const struct reg_arch_type * | reg_type | ||
| ) |
Initialize register.
Definition at line 608 of file riscv_reg.c.
References reg::arch_info, reg::caller_save, riscv_reg_info_t::custom_number, reg::dirty, ERROR_FAIL, ERROR_OK, reg::exist, reg::feature, gdb_regno_caller_save(), GDB_REGNO_COUNT, gdb_regno_custom_number(), gdb_regno_feature(), gdb_regno_group(), gdb_regno_reg_data_type(), gdb_regno_size(), reg::group, reg::hidden, info, LOG_ERROR, reg::name, reg::number, reg::reg_data_type, resize_reg(), RISCV_INFO, riscv_reg_gdb_regno_name(), riscv_reg_impl_cache_entry(), riscv_reg_impl_is_initialized(), target, riscv_reg_info_t::target, reg::type, and reg::valid.
Referenced by assume_reg_exist(), init_cache_entry(), and riscv011_reg_init_all().
◆ riscv_reg_impl_init_vector_reg_type()
|
inlinestatic |
TODO: vector register type description can be moved into riscv013_info_t, since 0.11 targets do not support access to vector registers.
Definition at line 69 of file riscv_reg_impl.h.
References info, NULL, REG_TYPE_ARCH_DEFINED, REG_TYPE_CLASS_UNION, REG_TYPE_CLASS_VECTOR, REG_TYPE_UINT128, REG_TYPE_UINT16, REG_TYPE_UINT32, REG_TYPE_UINT64, REG_TYPE_UINT8, RISCV_INFO, riscv_vlenb(), and reg_data_type::type.
Referenced by riscv013_reg_examine_all().
◆ riscv_reg_impl_is_initialized()
|
inlinestatic |
This file describes the helpers to use during register cache initialization of a RISC-V target.
Each cache entry proceedes through the following stages:
- not allocated before
riscv_reg_impl_init_cache() - not initialized before the call to
riscv_reg_impl_init_cache_entry()with appropriate regno. - initialized until
riscv_reg_free_all()is called.
Definition at line 19 of file riscv_reg_impl.h.
References reg::arch_info, reg::dirty, reg::exist, reg::feature, reg::valid, and reg::value.
Referenced by init_cache_entry(), reg_exists(), resize_reg(), riscv011_reg_init_all(), riscv_reg_cache_any_dirty(), riscv_reg_get(), riscv_reg_impl_get_target(), riscv_reg_impl_init_cache_entry(), riscv_reg_impl_set_exist(), and riscv_set_or_write_register().
◆ riscv_reg_impl_set_exist()
| int riscv_reg_impl_set_exist | ( | const struct target * | target, |
| uint32_t | regno, | ||
| bool | exist | ||
| ) |
Mark register as existing or not.
Definition at line 601 of file riscv_reg.c.
References reg::exist, resize_reg(), riscv_reg_impl_cache_entry(), riscv_reg_impl_is_initialized(), and reg::size.
Referenced by examine_mtopi(), examine_vlenb(), and riscv_reg_impl_expose_csrs().
