17 #define PM_ACT_CFG0 0x400043A0
18 #define PM_ACT_CFG12 0x400043AC
19 #define SPC_CPU_DATA 0x40004720
20 #define SPC_SR 0x40004722
21 #define PRT1_PC2 0x4000500A
22 #define PHUB_CH0_BASIC_CFG 0x40007010
23 #define PHUB_CH0_ACTION 0x40007014
24 #define PHUB_CH0_BASIC_STATUS 0x40007018
25 #define PHUB_CH1_BASIC_CFG 0x40007020
26 #define PHUB_CH1_ACTION 0x40007024
27 #define PHUB_CH1_BASIC_STATUS 0x40007028
28 #define PHUB_CFGMEM0_CFG0 0x40007600
29 #define PHUB_CFGMEM0_CFG1 0x40007604
30 #define PHUB_CFGMEM1_CFG0 0x40007608
31 #define PHUB_CFGMEM1_CFG1 0x4000760C
32 #define PHUB_TDMEM0_ORIG_TD0 0x40007800
33 #define PHUB_TDMEM0_ORIG_TD1 0x40007804
34 #define PHUB_TDMEM1_ORIG_TD0 0x40007808
35 #define PHUB_TDMEM1_ORIG_TD1 0x4000780C
36 #define PANTHER_DEVICE_ID 0x4008001C
41 #define NVL_META_BASE 0x90000000
43 #define PM_ACT_CFG12_EN_EE (1 << 4)
48 #define SPC_LOAD_BYTE 0x00
49 #define SPC_LOAD_MULTI_BYTE 0x01
50 #define SPC_LOAD_ROW 0x02
51 #define SPC_READ_BYTE 0x03
52 #define SPC_READ_MULTI_BYTE 0x04
53 #define SPC_WRITE_ROW 0x05
54 #define SPC_WRITE_USER_NVL 0x06
55 #define SPC_PRG_ROW 0x07
56 #define SPC_ERASE_SECTOR 0x08
57 #define SPC_ERASE_ALL 0x09
58 #define SPC_READ_HIDDEN_ROW 0x0A
59 #define SPC_PROGRAM_PROTECT_ROW 0x0B
60 #define SPC_GET_CHECKSUM 0x0C
61 #define SPC_GET_TEMP 0x0E
62 #define SPC_READ_VOLATILE_BYTE 0x10
64 #define SPC_ARRAY_ALL 0x3F
65 #define SPC_ARRAY_EEPROM 0x40
66 #define SPC_ARRAY_NVL_USER 0x80
67 #define SPC_ARRAY_NVL_WO 0xF8
69 #define SPC_ROW_PROTECTION 0
71 #define SPC_OPCODE_LEN 3
73 #define SPC_SR_DATA_READY (1 << 0)
74 #define SPC_SR_IDLE (1 << 1)
76 #define PM_ACT_CFG0_EN_CLK_SPC (1 << 3)
78 #define PHUB_CHX_BASIC_CFG_EN (1 << 0)
79 #define PHUB_CHX_BASIC_CFG_WORK_SEP (1 << 5)
81 #define PHUB_CHX_ACTION_CPU_REQ (1 << 0)
83 #define PHUB_CFGMEMX_CFG0 (1 << 7)
85 #define PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST (0xff << 16)
86 #define PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR (1 << 24)
88 #define NVL_3_ECCEN (1 << 3)
91 #define ROW_ECC_SIZE 32
92 #define ROWS_PER_SECTOR 64
93 #define SECTOR_SIZE (ROWS_PER_SECTOR * ROW_SIZE)
94 #define ROWS_PER_BLOCK 256
95 #define BLOCK_SIZE (ROWS_PER_BLOCK * ROW_SIZE)
96 #define SECTORS_PER_BLOCK (BLOCK_SIZE / SECTOR_SIZE)
97 #define EEPROM_ROW_SIZE 16
98 #define EEPROM_SECTOR_SIZE (ROWS_PER_SECTOR * EEPROM_ROW_SIZE)
99 #define EEPROM_BLOCK_SIZE (ROWS_PER_BLOCK * EEPROM_ROW_SIZE)
101 #define PART_NUMBER_LEN (17 + 1)
117 { .
id = 0x2E11F069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
118 { .id = 0x2E120069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
119 { .id = 0x2E123069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
120 { .id = 0x2E124069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
121 { .id = 0x2E126069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
122 { .id = 0x2E127069, .fam = 8, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
123 { .id = 0x2E117069, .fam = 8, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
124 { .id = 0x2E118069, .fam = 8, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
125 { .id = 0x2E119069, .fam = 8, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
126 { .id = 0x2E11C069, .fam = 8, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
127 { .id = 0x2E114069, .fam = 8, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
128 { .id = 0x2E115069, .fam = 8, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
129 { .id = 0x2E116069, .fam = 8, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
130 { .id = 0x2E160069, .fam = 8, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
132 { .id = 0x2E161069, .fam = 8, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
134 { .id = 0x2E1D2069, .fam = 8, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
135 { .id = 0x2E1D6069, .fam = 8, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
138 { .id = 0x2E10A069, .fam = 6, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
139 { .id = 0x2E10D069, .fam = 6, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
140 { .id = 0x2E10E069, .fam = 6, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
141 { .id = 0x2E106069, .fam = 6, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
142 { .id = 0x2E108069, .fam = 6, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
143 { .id = 0x2E109069, .fam = 6, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
144 { .id = 0x2E101069, .fam = 6, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
145 { .id = 0x2E104069, .fam = 6, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
147 { .id = 0x2E105069, .fam = 6, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
148 { .id = 0x2E128069, .fam = 6, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
150 { .id = 0x2E122069, .fam = 6, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
151 { .id = 0x2E129069, .fam = 6, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
152 { .id = 0x2E163069, .fam = 6, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
153 { .id = 0x2E156069, .fam = 6, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
154 { .id = 0x2E1D3069, .fam = 6, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
157 { .id = 0x2E11A069, .fam = 4, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
158 { .id = 0x2E16A069, .fam = 4, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
159 { .id = 0x2E12A069, .fam = 4, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
160 { .id = 0x2E103069, .fam = 4, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
161 { .id = 0x2E16C069, .fam = 4, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
162 { .id = 0x2E102069, .fam = 4, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
163 { .id = 0x2E148069, .fam = 4, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
164 { .id = 0x2E155069, .fam = 4, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
165 { .id = 0x2E16B069, .fam = 4, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
166 { .id = 0x2E12B069, .fam = 4, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
167 { .id = 0x2E168069, .fam = 4, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
168 { .id = 0x2E178069, .fam = 4, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
169 { .id = 0x2E15D069, .fam = 4, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
170 { .id = 0x2E1D4069, .fam = 4, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
173 { .id = 0x2E11E069, .fam = 2, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
174 { .id = 0x2E12F069, .fam = 2, .speed_mhz = 67, .flash_kb = 256, .eeprom_kb = 2 },
175 { .id = 0x2E133069, .fam = 2, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
176 { .id = 0x2E159069, .fam = 2, .speed_mhz = 67, .flash_kb = 128, .eeprom_kb = 2 },
177 { .id = 0x2E11D069, .fam = 2, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
178 { .id = 0x2E121069, .fam = 2, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
179 { .id = 0x2E184069, .fam = 2, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
180 { .id = 0x2E196069, .fam = 2, .speed_mhz = 67, .flash_kb = 64, .eeprom_kb = 2 },
181 { .id = 0x2E132069, .fam = 2, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
182 { .id = 0x2E138069, .fam = 2, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
183 { .id = 0x2E13A069, .fam = 2, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
184 { .id = 0x2E152069, .fam = 2, .speed_mhz = 67, .flash_kb = 32, .eeprom_kb = 2 },
185 { .id = 0x2E15F069, .fam = 2, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
186 { .id = 0x2E15A069, .fam = 2, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
187 { .id = 0x2E1D5069, .fam = 2, .speed_mhz = 80, .flash_kb = 256, .eeprom_kb = 2 },
192 strcpy(str,
"CY8Cabcdefg-LPxxx");
195 str[5] =
'0' + dev->
fam;
256 LOG_DEBUG(
"PANTHER_DEVICE_ID = 0x%08" PRIX32, device_id);
265 LOG_ERROR(
"Device 0x%08" PRIX32
" not supported", device_id);
305 uint8_t *buf, uint8_t opcode)
359 uint8_t array_id, uint8_t
offset, uint8_t value)
384 uint8_t array_id,
const uint8_t *data,
unsigned row_size)
396 for (i = 0; i < row_size; i++) {
410 uint8_t array_id, uint8_t
offset, uint8_t *data)
440 uint8_t array_id, uint16_t row_id,
const uint8_t *temp)
490 uint8_t array_id, uint8_t row_id)
527 uint8_t array_id, uint8_t row_id, uint8_t *data)
589 uint8_t array_id, uint8_t
offset, uint8_t *data)
652 LOG_WARNING(
"There is no erase operation for NV Latches");
658 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
659 bank->sectors[i].is_erased = 0;
665 const uint8_t *
buffer, uint32_t
offset, uint32_t byte_count)
668 uint8_t *current_data, val;
669 bool write_required =
false, pullup_needed =
false, ecc_changed =
false;
673 if (
offset != 0 || byte_count !=
bank->size) {
674 LOG_ERROR(
"NVL can only be written in whole");
678 current_data = calloc(1,
bank->size);
686 for (i =
offset; i < byte_count; i++) {
687 if (current_data[i] !=
buffer[i]) {
688 write_required =
true;
692 if (((
buffer[2] & 0x80) == 0x80) && ((current_data[0] & 0x0C) != 0x08))
693 pullup_needed =
true;
694 if (((
buffer[3] ^ current_data[3]) & 0x08) == 0x08)
698 if (!write_required) {
699 LOG_INFO(
"Unchanged, skipping NVL write");
713 for (i =
offset; i < byte_count; i++) {
724 LOG_ERROR(
"Failed to load NVL byte %" PRIu32
": "
725 "expected 0x%02" PRIx8
", read 0x%02" PRIx8,
738 LOG_WARNING(
"Reset failed after enabling or disabling ECC");
762 if (psoc_nvl_bank->
probed)
776 bank->num_sectors = 1;
777 bank->sectors = calloc(
bank->num_sectors,
779 bank->sectors[0].offset = 0;
780 bank->sectors[0].size = 4;
781 bank->sectors[0].is_erased = -1;
782 bank->sectors[0].is_protected = -1;
784 psoc_nvl_bank->
probed =
true;
793 if (psoc_nvl_bank->
probed)
807 psoc_nvl_bank->
probed =
false;
809 bank->driver_priv = psoc_nvl_bank;
815 .
name =
"psoc5lp_nvl",
816 .flash_bank_command = psoc5lp_nvl_flash_bank_command,
841 for (
unsigned int i = first; i <= last; i++) {
852 const uint8_t *
buffer, uint32_t
offset, uint32_t byte_count)
860 LOG_ERROR(
"Writes must be row-aligned, got offset 0x%08" PRIx32,
867 LOG_ERROR(
"Unable to read Die temperature");
870 LOG_DEBUG(
"Get_Temp: sign 0x%02" PRIx8
", magnitude 0x%02" PRIx8,
888 if (byte_count > 0) {
891 memcpy(buf,
buffer, byte_count);
892 memset(buf + byte_count,
bank->default_padded_value,
925 uint32_t flash_addr =
bank->base;
929 if (psoc_eeprom_bank->
probed)
953 bank->sectors = calloc(
bank->num_sectors,
955 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
957 bank->sectors[i].offset = flash_addr -
bank->base;
958 bank->sectors[i].is_erased = -1;
959 bank->sectors[i].is_protected = -1;
961 flash_addr +=
bank->sectors[i].size;
964 bank->default_padded_value =
bank->erased_value = 0x00;
966 psoc_eeprom_bank->
probed =
true;
975 if (psoc_eeprom_bank->
probed)
986 if (!psoc_eeprom_bank)
989 psoc_eeprom_bank->
probed =
false;
992 bank->driver_priv = psoc_eeprom_bank;
998 .
name =
"psoc5lp_eeprom",
999 .flash_bank_command = psoc5lp_eeprom_flash_bank_command,
1032 if (last >= first +
bank->num_sectors / 2) {
1033 LOG_DEBUG(
"Skipping duplicate erase of sectors %u to %u",
1034 first +
bank->num_sectors / 2, last);
1035 last = first + (
bank->num_sectors / 2) - 1;
1038 if (last >=
bank->num_sectors / 2) {
1039 LOG_WARNING(
"Skipping erase of ECC region sectors %u to %u",
1040 bank->num_sectors / 2, last);
1041 last = (
bank->num_sectors / 2) - 1;
1045 for (
unsigned int i = first; i <= last; i++) {
1067 unsigned int num_sectors =
bank->num_sectors;
1076 for (
unsigned int i = 0; i < num_sectors; i++) {
1078 block_array[i].
size =
bank->sectors[i].size;
1079 block_array[i].
result = UINT32_MAX;
1082 bool fast_check =
true;
1083 for (
unsigned int i = 0; i < num_sectors; ) {
1085 block_array + i, num_sectors - i,
1086 bank->erased_value);
1099 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
1100 bank->sectors[i].is_erased =
1101 (block_array[i].
result != 1)
1106 for (
unsigned int i = 0; i < num_sectors; i++)
1107 bank->sectors[i].is_erased = block_array[i].
result;
1111 LOG_ERROR(
"Can't run erase check - add working memory");
1120 uint32_t
offset, uint32_t byte_count)
1124 struct working_area *code_area, *even_row_area, *odd_row_area;
1127 unsigned array_id, row;
1131 LOG_ERROR(
"Writing to ECC not supported");
1136 LOG_ERROR(
"Writes must be row-aligned, got offset 0x%08" PRIx32,
1149 LOG_ERROR(
"Unable to read Die temperature");
1152 LOG_DEBUG(
"Get_Temp: sign 0x%02" PRIx8
", magnitude 0x%02" PRIx8,
1159 LOG_ERROR(
"Could not allocate working area for program SRAM");
1162 assert(code_area->
address < 0x20000000);
1168 LOG_ERROR(
"Could not allocate working area for even row");
1169 goto err_alloc_even;
1171 assert(even_row_area->
address >= 0x20000000);
1176 LOG_ERROR(
"Could not allocate working area for odd row");
1179 assert(odd_row_area->
address >= 0x20000000);
1183 row < ROWS_PER_BLOCK && byte_count > 0; row++) {
1184 bool even_row = (row % 2 == 0);
1185 struct working_area *data_area = even_row ? even_row_area : odd_row_area;
1189 array_id, row, data_area->
address);
1222 sizeof(ecc_bytes), ecc_bytes);
1227 for (i = 0; i < 3; i++)
1243 (even_row ? 0 : 1) << 8);
1287 goto err_dma_action;
1311 unsigned i, k, num_sectors;
1331 for (
unsigned int j = 0; j < num_sectors; j++) {
1337 ecc_sector = &
bank->sectors[
bank->num_sectors + sector_nr];
1339 ecc_sector = &
bank->sectors[
bank->num_sectors / 2 + sector_nr];
1342 for (k = protection_bytes_per_sector * j;
1343 k < protection_bytes_per_sector * (j + 1); k++) {
1345 LOG_DEBUG(
"row[%u][%02u] = 0x%02" PRIx8, i, k, row_data[k]);
1346 if (row_data[k] != 0x00) {
1375 uint32_t flash_addr =
bank->base;
1376 uint8_t nvl[4], temp[2];
1384 if (!psoc_bank->
device) {
1394 if (!psoc_bank->
probed) {
1402 LOG_ERROR(
"Unable to read Die temperature");
1406 bank->sectors = calloc(
bank->num_sectors * 2,
1408 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
1410 bank->sectors[i].offset = flash_addr -
bank->base;
1411 bank->sectors[i].is_erased = -1;
1412 bank->sectors[i].is_protected = -1;
1414 flash_addr +=
bank->sectors[i].size;
1416 flash_addr = 0x48000000;
1417 for (
unsigned int i =
bank->num_sectors; i < bank->num_sectors * 2; i++) {
1419 bank->sectors[i].offset = flash_addr -
bank->base;
1420 bank->sectors[i].is_erased = -1;
1421 bank->sectors[i].is_protected = -1;
1423 flash_addr +=
bank->sectors[i].size;
1426 bank->default_padded_value =
bank->erased_value = 0x00;
1428 psoc_bank->
probed =
true;
1434 LOG_DEBUG(
"NVL[%d] = 0x%02" PRIx8, 3, nvl[3]);
1438 bank->num_sectors *= 2;
1477 psoc_bank->
probed =
false;
1480 bank->driver_priv = psoc_bank;
1487 .
name =
"mass_erase",
1488 .handler = psoc5lp_handle_mass_erase_command,
1491 .help =
"Erase all flash data and ECC/configuration bytes, "
1492 "all flash protection rows, "
1493 "and all row latches in all flash arrays on the device.",
1502 .help =
"PSoC 5LP flash command group",
1512 .flash_bank_command = psoc5lp_flash_bank_command,
int armv7m_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Checks an array of memory regions whether they are erased.
static const struct device_t * device
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_FLASH_OPER_UNSUPPORTED
#define ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
#define ERROR_FLASH_DST_OUT_OF_BANK
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
static int psoc5lp_nvl_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
static int psoc5lp_spc_load_byte(struct target *target, uint8_t array_id, uint8_t offset, uint8_t value)
static int psoc5lp_find_device(struct target *target, const struct psoc5lp_device **device)
#define PM_ACT_CFG0_EN_CLK_SPC
#define SPC_ARRAY_NVL_USER
static int psoc5lp_probe(struct flash_bank *bank)
#define PHUB_TDMEM1_ORIG_TD1
#define PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR
#define SPC_WRITE_USER_NVL
static int psoc5lp_eeprom_probe(struct flash_bank *bank)
static void psoc5lp_spc_write_opcode_buffer(struct target *target, uint8_t *buf, uint8_t opcode)
#define PHUB_CH1_BASIC_CFG
#define SECTORS_PER_BLOCK
#define PHUB_CHX_BASIC_CFG_WORK_SEP
#define PHUB_CFGMEM0_CFG1
static const struct psoc5lp_device psoc5lp_devices[]
#define PHUB_CH0_BASIC_STATUS
#define PHUB_CHX_BASIC_CFG_EN
static int psoc5lp_protect_check(struct flash_bank *bank)
static int psoc5lp_spc_write_row(struct target *target, uint8_t array_id, uint16_t row_id, const uint8_t *temp)
static int psoc5lp_spc_erase_all(struct target *target)
static int psoc5lp_spc_read_byte(struct target *target, uint8_t array_id, uint8_t offset, uint8_t *data)
static int psoc5lp_nvl_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static const struct command_registration psoc5lp_command_handlers[]
#define PHUB_CH1_BASIC_STATUS
#define PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST
#define SPC_ROW_PROTECTION
static int psoc5lp_nvl_auto_probe(struct flash_bank *bank)
static int psoc5lp_spc_write_opcode(struct target *target, uint8_t opcode)
static int psoc5lp_nvl_probe(struct flash_bank *bank)
static int psoc5lp_spc_busy_wait_idle(struct target *target)
#define PHUB_TDMEM1_ORIG_TD0
static int psoc5lp_spc_write_user_nvl(struct target *target, uint8_t array_id)
FLASH_BANK_COMMAND_HANDLER(psoc5lp_nvl_flash_bank_command)
static int psoc5lp_eeprom_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
const struct flash_driver psoc5lp_flash
#define SPC_READ_VOLATILE_BYTE
#define PHUB_CFGMEMX_CFG0
static void psoc5lp_get_part_number(const struct psoc5lp_device *dev, char *str)
#define PANTHER_DEVICE_ID
#define SPC_SR_DATA_READY
static int psoc5lp_spc_busy_wait_data(struct target *target)
COMMAND_HANDLER(psoc5lp_handle_mass_erase_command)
static int psoc5lp_get_device_id(struct target *target, uint32_t *id)
#define PHUB_CFGMEM1_CFG0
#define PHUB_TDMEM0_ORIG_TD1
#define PHUB_TDMEM0_ORIG_TD0
static int psoc5lp_eeprom_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static int psoc5lp_spc_erase_sector(struct target *target, uint8_t array_id, uint8_t row_id)
#define PHUB_CFGMEM1_CFG1
static int psoc5lp_spc_read_hidden_row(struct target *target, uint8_t array_id, uint8_t row_id, uint8_t *data)
static int psoc5lp_auto_probe(struct flash_bank *bank)
static const struct command_registration psoc5lp_exec_command_handlers[]
static int psoc5lp_nvl_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
const struct flash_driver psoc5lp_nvl_flash
const struct flash_driver psoc5lp_eeprom_flash
static int psoc5lp_eeprom_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t byte_count)
static int psoc5lp_spc_load_row(struct target *target, uint8_t array_id, const uint8_t *data, unsigned row_size)
static int psoc5lp_get_info_command(struct flash_bank *bank, struct command_invocation *cmd)
#define EEPROM_SECTOR_SIZE
static int psoc5lp_spc_read_volatile_byte(struct target *target, uint8_t array_id, uint8_t offset, uint8_t *data)
#define PM_ACT_CFG12_EN_EE
static int psoc5lp_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static int psoc5lp_erase_check(struct flash_bank *bank)
static int psoc5lp_spc_enable_clock(struct target *target)
static int psoc5lp_nvl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t byte_count)
#define PHUB_CHX_ACTION_CPU_REQ
static int psoc5lp_spc_get_temp(struct target *target, uint8_t samples, uint8_t *data)
static int psoc5lp_nvl_erase_check(struct flash_bank *bank)
#define PHUB_CH0_BASIC_CFG
static int psoc5lp_eeprom_auto_probe(struct flash_bank *bank)
static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t byte_count)
#define PHUB_CFGMEM0_CFG0
#define SPC_READ_HIDDEN_ROW
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
const struct psoc5lp_device * device
const struct psoc5lp_device * device
const struct psoc5lp_device * device
uint32_t working_area_size
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
int target_call_reset_callbacks(struct target *target, enum target_reset_mode reset_mode)
uint32_t target_get_working_area_avail(struct target *target)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
#define ERROR_TARGET_NOT_HALTED
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
#define DIV_ROUND_UP(m, n)
Rounds m up to the nearest multiple of n using division.