Include dependency graph for stmqspi.h:

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Macros
#define	IS_OCTOSPI (stmqspi_info->octo)

#define	OCTO_MAGIC_ID 0xA3C5DD01 /* Magic ID, deleted from RM, why? */

#define	OCTOSPI_8LINE_MODE 0x0F003F3FU /* 8 lines DTR for data, addr, instr */

#define	OCTOSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */

#define	OCTOSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */

#define	OCTOSPI_ALTB_MODE 0x001F0000U /* alternate byte mode */

#define	OCTOSPI_AR (0x048) /* Address register */

#define	OCTOSPI_CCR (0x100) /* Communication configuration register */

#define	OCTOSPI_CR (0x000) /* Control register */

#define	OCTOSPI_DCR1 (0x008) /* Device configuration register 1 */

#define	OCTOSPI_DCR2 (0x00C) /* Device configuration register 2 */

#define	OCTOSPI_DCR3 (0x010) /* Device configuration register 3 */

#define	OCTOSPI_DCYC_LEN 5 /* width of DCYC field */

#define	OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)

#define	OCTOSPI_DCYC_POS 0 /* bit position of DCYC */

#define	OCTOSPI_DDTR 27 /* DTR for data */

#define	OCTOSPI_DLR (0x040) /* Data length register */

#define	OCTOSPI_DQSEN 29 /* DQS enable */

#define	OCTOSPI_DR (0x050) /* Data register */

#define	OCTOSPI_FCR (0x024) /* Flag clear register */

#define	OCTOSPI_IR (0x110) /* Instruction register */

#define	OCTOSPI_ISIZE_MASK (0x30) /* ISIZE field */

#define	OCTOSPI_MAGIC (0x3FC) /* Magic ID register, deleted from RM, why? */

#define	OCTOSPI_MM_MODE 0x30000000U /* memory mapped mode */

#define	OCTOSPI_MTYP_LEN (3) /* width of MTYP field */

#define	OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)

#define	OCTOSPI_MTYP_POS (24) /* bit position of MTYP */

#define	OCTOSPI_NO_ADDR (~0x00000F00U) /* no address */

#define	OCTOSPI_NO_ALTB (~OCTOSPI_ALTB_MODE) /* no alternate */

#define	OCTOSPI_NO_DATA (~0x0F000000U) /* no data */

#define	OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */

#define	OCTOSPI_READ_MODE 0x10000000U /* indirect read mode */

#define	OCTOSPI_SR (0x020) /* Status register */

#define	OCTOSPI_TCR (0x108) /* Timing configuration register */

#define	OCTOSPI_WCCR (0x180) /* Write communication configuration register */

#define	OCTOSPI_WIR (0x190) /* Write instruction register */

#define	OCTOSPI_WRITE_MODE 0x00000000U /* indirect write mode */

#define	QSPI_4LINE_MODE 0x03000F00U /* 4 lines for data, addr, instr */

#define	QSPI_ABR (0x1C) /* Alternate bytes register */

#define	QSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */

#define	QSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */

#define	QSPI_ALTB_MODE 0x0003C000U /* alternate byte mode */

#define	QSPI_AR (0x18) /* Address register */

#define	QSPI_CCR (0x14) /* Communication configuration register */

#define	QSPI_CR (0x00) /* Control register */

#define	QSPI_DCR (0x04) /* Device configuration register */

#define	QSPI_DCYC_LEN 5 /* width of DCYC field */

#define	QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)

#define	QSPI_DCYC_POS 18 /* bit position of DCYC */

#define	QSPI_DDRM 31 /* position of DDRM bit */

#define	QSPI_DLR (0x10) /* Data length register */

#define	QSPI_DR (0x20) /* Data register */

#define	QSPI_FCR (0x0C) /* Flag clear register */

#define	QSPI_MM_MODE 0x0C000000U /* memory mapped mode */

#define	QSPI_NO_ADDR (~0x00000C00U) /* no address */

#define	QSPI_NO_ALTB (~QSPI_ALTB_MODE) /* no alternate */

#define	QSPI_NO_DATA (~0x03000000U) /* no data */

#define	QSPI_READ_MODE 0x04000000U /* indirect read mode */

#define	QSPI_SR (0x08) /* Status register */

#define	QSPI_WRITE_MODE 0x00000000U /* indirect write mode */

#define	SPI_ABORT 1 /* Abort bit */

#define	SPI_ADSIZE_POS 12 /* bit position of ADSIZE */

#define	SPI_AR (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)

#define	SPI_BUSY 5 /* Busy flag */

#define	SPI_CCR (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)

#define	SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)

#define	SPI_DCR (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)

#define	SPI_DLR (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)

#define	SPI_DMODE_POS 24 /* bit position of DMODE */

#define	SPI_DR (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)

#define	SPI_DUAL_FLASH 6 /* Dual flash mode */

#define	SPI_FCR (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)

#define	SPI_FSEL_FLASH 7 /* Select flash 2 */

#define	SPI_FSIZE_LEN 5 /* width of FSIZE field */

#define	SPI_FSIZE_POS 16 /* bit position of FSIZE */

#define	SPI_FTF 2 /* FIFO threshold flag */

#define	SPI_SR (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)

#define	SPI_TCF 1 /* Transfer complete flag */

Macro Definition Documentation

◆ IS_OCTOSPI

#define IS_OCTOSPI (stmqspi_info->octo)

Definition at line 104 of file stmqspi.h.

◆ OCTO_MAGIC_ID

#define OCTO_MAGIC_ID 0xA3C5DD01 /* Magic ID, deleted from RM, why? */

Definition at line 74 of file stmqspi.h.

◆ OCTOSPI_8LINE_MODE

#define OCTOSPI_8LINE_MODE 0x0F003F3FU /* 8 lines DTR for data, addr, instr */

Definition at line 88 of file stmqspi.h.

◆ OCTOSPI_ADDR3

#define OCTOSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */

Definition at line 92 of file stmqspi.h.

◆ OCTOSPI_ADDR4

#define OCTOSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */

Definition at line 93 of file stmqspi.h.

◆ OCTOSPI_ALTB_MODE

#define OCTOSPI_ALTB_MODE 0x001F0000U /* alternate byte mode */

Definition at line 87 of file stmqspi.h.

◆ OCTOSPI_AR

#define OCTOSPI_AR (0x048) /* Address register */

Definition at line 65 of file stmqspi.h.

◆ OCTOSPI_CCR

#define OCTOSPI_CCR (0x100) /* Communication configuration register */

Definition at line 67 of file stmqspi.h.

◆ OCTOSPI_CR

#define OCTOSPI_CR (0x000) /* Control register */

Definition at line 58 of file stmqspi.h.

◆ OCTOSPI_DCR1

#define OCTOSPI_DCR1 (0x008) /* Device configuration register 1 */

Definition at line 59 of file stmqspi.h.

◆ OCTOSPI_DCR2

#define OCTOSPI_DCR2 (0x00C) /* Device configuration register 2 */

Definition at line 60 of file stmqspi.h.

◆ OCTOSPI_DCR3

#define OCTOSPI_DCR3 (0x010) /* Device configuration register 3 */

Definition at line 61 of file stmqspi.h.

◆ OCTOSPI_DCYC_LEN

#define OCTOSPI_DCYC_LEN 5 /* width of DCYC field */

Definition at line 101 of file stmqspi.h.

◆ OCTOSPI_DCYC_MASK

#define OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)

Definition at line 102 of file stmqspi.h.

◆ OCTOSPI_DCYC_POS

#define OCTOSPI_DCYC_POS 0 /* bit position of DCYC */

Definition at line 100 of file stmqspi.h.

◆ OCTOSPI_DDTR

#define OCTOSPI_DDTR 27 /* DTR for data */

Definition at line 95 of file stmqspi.h.

◆ OCTOSPI_DLR

#define OCTOSPI_DLR (0x040) /* Data length register */

Definition at line 64 of file stmqspi.h.

◆ OCTOSPI_DQSEN

#define OCTOSPI_DQSEN 29 /* DQS enable */

Definition at line 94 of file stmqspi.h.

◆ OCTOSPI_DR

#define OCTOSPI_DR (0x050) /* Data register */

Definition at line 66 of file stmqspi.h.

◆ OCTOSPI_FCR

#define OCTOSPI_FCR (0x024) /* Flag clear register */

Definition at line 63 of file stmqspi.h.

◆ OCTOSPI_IR

#define OCTOSPI_IR (0x110) /* Instruction register */

Definition at line 69 of file stmqspi.h.

◆ OCTOSPI_ISIZE_MASK

#define OCTOSPI_ISIZE_MASK (0x30) /* ISIZE field */

Definition at line 97 of file stmqspi.h.

◆ OCTOSPI_MAGIC

#define OCTOSPI_MAGIC (0x3FC) /* Magic ID register, deleted from RM, why? */

Definition at line 72 of file stmqspi.h.

◆ OCTOSPI_MM_MODE

#define OCTOSPI_MM_MODE 0x30000000U /* memory mapped mode */

Definition at line 79 of file stmqspi.h.

◆ OCTOSPI_MTYP_LEN

#define OCTOSPI_MTYP_LEN (3) /* width of MTYP field */

Definition at line 83 of file stmqspi.h.

◆ OCTOSPI_MTYP_MASK

#define OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)

Definition at line 84 of file stmqspi.h.

◆ OCTOSPI_MTYP_POS

#define OCTOSPI_MTYP_POS (24) /* bit position of MTYP */

Definition at line 82 of file stmqspi.h.

◆ OCTOSPI_NO_ADDR

#define OCTOSPI_NO_ADDR (~0x00000F00U) /* no address */

Definition at line 91 of file stmqspi.h.

◆ OCTOSPI_NO_ALTB

#define OCTOSPI_NO_ALTB (~OCTOSPI_ALTB_MODE) /* no alternate */

Definition at line 90 of file stmqspi.h.

◆ OCTOSPI_NO_DATA

#define OCTOSPI_NO_DATA (~0x0F000000U) /* no data */

Definition at line 89 of file stmqspi.h.

◆ OCTOSPI_NO_DDTR

#define OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */

Definition at line 96 of file stmqspi.h.

◆ OCTOSPI_READ_MODE

#define OCTOSPI_READ_MODE 0x10000000U /* indirect read mode */

Definition at line 78 of file stmqspi.h.

◆ OCTOSPI_SR

#define OCTOSPI_SR (0x020) /* Status register */

Definition at line 62 of file stmqspi.h.

◆ OCTOSPI_TCR

#define OCTOSPI_TCR (0x108) /* Timing configuration register */

Definition at line 68 of file stmqspi.h.

◆ OCTOSPI_WCCR

#define OCTOSPI_WCCR (0x180) /* Write communication configuration register */

Definition at line 70 of file stmqspi.h.

◆ OCTOSPI_WIR

#define OCTOSPI_WIR (0x190) /* Write instruction register */

Definition at line 71 of file stmqspi.h.

◆ OCTOSPI_WRITE_MODE

#define OCTOSPI_WRITE_MODE 0x00000000U /* indirect write mode */

Definition at line 77 of file stmqspi.h.

◆ QSPI_4LINE_MODE

#define QSPI_4LINE_MODE 0x03000F00U /* 4 lines for data, addr, instr */

Definition at line 50 of file stmqspi.h.

◆ QSPI_ABR

#define QSPI_ABR (0x1C) /* Alternate bytes register */

Definition at line 21 of file stmqspi.h.

◆ QSPI_ADDR3

#define QSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */

Definition at line 54 of file stmqspi.h.

◆ QSPI_ADDR4

#define QSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */

Definition at line 55 of file stmqspi.h.

◆ QSPI_ALTB_MODE

#define QSPI_ALTB_MODE 0x0003C000U /* alternate byte mode */

Definition at line 49 of file stmqspi.h.

◆ QSPI_AR

#define QSPI_AR (0x18) /* Address register */

Definition at line 20 of file stmqspi.h.

◆ QSPI_CCR

#define QSPI_CCR (0x14) /* Communication configuration register */

Definition at line 19 of file stmqspi.h.

◆ QSPI_CR

#define QSPI_CR (0x00) /* Control register */

Definition at line 14 of file stmqspi.h.

◆ QSPI_DCR

#define QSPI_DCR (0x04) /* Device configuration register */

Definition at line 15 of file stmqspi.h.

◆ QSPI_DCYC_LEN

#define QSPI_DCYC_LEN 5 /* width of DCYC field */

Definition at line 42 of file stmqspi.h.

◆ QSPI_DCYC_MASK

#define QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)

Definition at line 43 of file stmqspi.h.

◆ QSPI_DCYC_POS

#define QSPI_DCYC_POS 18 /* bit position of DCYC */

Definition at line 41 of file stmqspi.h.

◆ QSPI_DDRM

#define QSPI_DDRM 31 /* position of DDRM bit */

Definition at line 39 of file stmqspi.h.

◆ QSPI_DLR

#define QSPI_DLR (0x10) /* Data length register */

Definition at line 18 of file stmqspi.h.

◆ QSPI_DR

#define QSPI_DR (0x20) /* Data register */

Definition at line 22 of file stmqspi.h.

◆ QSPI_FCR

#define QSPI_FCR (0x0C) /* Flag clear register */

Definition at line 17 of file stmqspi.h.

◆ QSPI_MM_MODE

#define QSPI_MM_MODE 0x0C000000U /* memory mapped mode */

Definition at line 48 of file stmqspi.h.

◆ QSPI_NO_ADDR

#define QSPI_NO_ADDR (~0x00000C00U) /* no address */

Definition at line 53 of file stmqspi.h.

◆ QSPI_NO_ALTB

#define QSPI_NO_ALTB (~QSPI_ALTB_MODE) /* no alternate */

Definition at line 52 of file stmqspi.h.

◆ QSPI_NO_DATA

#define QSPI_NO_DATA (~0x03000000U) /* no data */

Definition at line 51 of file stmqspi.h.

◆ QSPI_READ_MODE

#define QSPI_READ_MODE 0x04000000U /* indirect read mode */

Definition at line 47 of file stmqspi.h.

◆ QSPI_SR

#define QSPI_SR (0x08) /* Status register */

Definition at line 16 of file stmqspi.h.

◆ QSPI_WRITE_MODE

#define QSPI_WRITE_MODE 0x00000000U /* indirect write mode */

Definition at line 46 of file stmqspi.h.

◆ SPI_ABORT

#define SPI_ABORT 1 /* Abort bit */

Definition at line 27 of file stmqspi.h.

◆ SPI_ADSIZE_POS

#define SPI_ADSIZE_POS 12 /* bit position of ADSIZE */

Definition at line 44 of file stmqspi.h.

◆ SPI_AR

#define SPI_AR (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)

Definition at line 110 of file stmqspi.h.

◆ SPI_BUSY

#define SPI_BUSY 5 /* Busy flag */

Definition at line 34 of file stmqspi.h.

◆ SPI_CCR

#define SPI_CCR (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)

Definition at line 112 of file stmqspi.h.

◆ SPI_CR

#define SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)

Definition at line 105 of file stmqspi.h.

◆ SPI_DCR

#define SPI_DCR (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)

Definition at line 106 of file stmqspi.h.

◆ SPI_DLR

#define SPI_DLR (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)

Definition at line 109 of file stmqspi.h.

◆ SPI_DMODE_POS

#define SPI_DMODE_POS 24 /* bit position of DMODE */

Definition at line 40 of file stmqspi.h.

◆ SPI_DR

#define SPI_DR (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)

Definition at line 111 of file stmqspi.h.

◆ SPI_DUAL_FLASH

#define SPI_DUAL_FLASH 6 /* Dual flash mode */

Definition at line 26 of file stmqspi.h.

◆ SPI_FCR

#define SPI_FCR (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)

Definition at line 108 of file stmqspi.h.

◆ SPI_FSEL_FLASH

#define SPI_FSEL_FLASH 7 /* Select flash 2 */

Definition at line 25 of file stmqspi.h.

◆ SPI_FSIZE_LEN

#define SPI_FSIZE_LEN 5 /* width of FSIZE field */

Definition at line 31 of file stmqspi.h.

◆ SPI_FSIZE_POS

#define SPI_FSIZE_POS 16 /* bit position of FSIZE */

Definition at line 30 of file stmqspi.h.

◆ SPI_FTF

#define SPI_FTF 2 /* FIFO threshold flag */

Definition at line 35 of file stmqspi.h.

◆ SPI_SR

#define SPI_SR (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)

Definition at line 107 of file stmqspi.h.

◆ SPI_TCF

#define SPI_TCF 1 /* Transfer complete flag */

Definition at line 36 of file stmqspi.h.

Macros