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Data Structures | |
| struct | range_list_t |
| struct | riscv_bscan_tunneled_scan_context_t |
| struct | riscv_info |
| struct | riscv_reg_info_t |
| struct | riscv_sample_buf |
| struct | riscv_sample_config_t |
| struct | virt2phys_info_t |
Macros | |
| #define | DEFAULT_COMMAND_TIMEOUT_SEC 2 |
| #define | DEFAULT_RESET_TIMEOUT_SEC 30 |
| #define | PG_MAX_LEVEL 4 |
| #define | RISCV_COMMON_MAGIC 0x52495356U |
| #define | RISCV_INFO(R) struct riscv_info *R = riscv_info(target); |
| #define | RISCV_MAX_HARTS 1024 |
| #define | RISCV_MAX_HWBPS 16 |
| #define | RISCV_MAX_REGISTERS 5000 |
| #define | RISCV_MAX_TRIGGERS 32 |
| #define | RISCV_NUM_MEM_ACCESS_METHODS 3 |
| #define | RISCV_PGSHIFT 12 |
| #define | RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81 |
| #define | RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80 |
| #define | RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE) |
| #define | RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN) |
Typedefs | |
| typedef uint64_t | riscv_addr_t |
| typedef uint32_t | riscv_insn_t |
| typedef uint64_t | riscv_reg_t |
Functions | |
| COMMAND_HELPER (riscv_print_info_line, const char *section, const char *key, unsigned int value) | |
| uint32_t | dtmcontrol_scan_via_bscan (struct target *target, uint32_t out) |
| static bool | is_riscv (const struct riscv_info *riscv_info) |
| void | riscv_add_bscan_tunneled_scan (struct target *target, struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt) |
| int | riscv_add_watchpoint (struct target *target, struct watchpoint *watchpoint) |
| int | riscv_count_harts (struct target *target) |
| int | riscv_current_hartid (const struct target *target) |
| size_t | riscv_debug_buffer_size (struct target *target) |
| int | riscv_dmi_write_u64_bits (struct target *target) |
| int | riscv_enumerate_triggers (struct target *target) |
| Count triggers, and initialize trigger_count for each hart. More... | |
| int | riscv_execute_debug_buffer (struct target *target) |
| void | riscv_fill_dmi_nop_u64 (struct target *target, char *buf) |
| void | riscv_fill_dmi_read_u64 (struct target *target, char *buf, int a) |
| void | riscv_fill_dmi_write_u64 (struct target *target, char *buf, int a, uint64_t d) |
| int | riscv_get_register (struct target *target, riscv_reg_t *value, enum gdb_regno r) |
| Get register, from the cache if it's in there. More... | |
| int | riscv_halt (struct target *target) |
| static struct riscv_info * | riscv_info (const struct target *target) __attribute__((unused)) |
| int | riscv_init_registers (struct target *target) |
| bool | riscv_is_halted (struct target *target) |
| int | riscv_openocd_assert_reset (struct target *target) |
| int | riscv_openocd_deassert_reset (struct target *target) |
| int | riscv_openocd_poll (struct target *target) |
| int | riscv_openocd_step (struct target *target, int current, target_addr_t address, int handle_breakpoints) |
| int | riscv_read_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer) |
| Read one memory item using any memory access size that will work. More... | |
| riscv_insn_t | riscv_read_debug_buffer (struct target *target, int index) |
| int | riscv_remove_watchpoint (struct target *target, struct watchpoint *watchpoint) |
| int | riscv_select_current_hart (struct target *target) |
| enum semihosting_result | riscv_semihosting (struct target *target, int *retval) |
| Check for and process a semihosting request using the ARM protocol). More... | |
| void | riscv_semihosting_init (struct target *target) |
| Initialize RISC-V semihosting. More... | |
| int | riscv_set_current_hartid (struct target *target, int hartid) |
| int | riscv_set_register (struct target *target, enum gdb_regno i, riscv_reg_t v) |
| Set register, updating the cache. More... | |
| bool | riscv_supports_extension (struct target *target, char letter) |
| int | riscv_write_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer) |
| Write one memory item using any memory access size that will work. More... | |
| int | riscv_write_debug_buffer (struct target *target, int index, riscv_insn_t insn) |
| unsigned | riscv_xlen (const struct target *target) |
| int | riscv_xlen_of_hart (const struct target *target) |
| void | select_dmi_via_bscan (struct target *target) |
Variables | |
| int | bscan_tunnel_ir_width |
| struct scan_field * | bscan_tunneled_select_dmi |
| uint32_t | bscan_tunneled_select_dmi_num_fields |
| struct target_type | riscv011_target |
| struct target_type | riscv013_target |
| int | riscv_command_timeout_sec |
| bool | riscv_ebreakm |
| bool | riscv_ebreaks |
| bool | riscv_ebreaku |
| bool | riscv_enable_virtual |
| int | riscv_reset_timeout_sec |
| struct scan_field | select_dbus |
| struct scan_field | select_dtmcontrol |
| struct scan_field | select_idcode |
Macro Definition Documentation
◆ DEFAULT_COMMAND_TIMEOUT_SEC
◆ DEFAULT_RESET_TIMEOUT_SEC
◆ PG_MAX_LEVEL
◆ RISCV_COMMON_MAGIC
◆ RISCV_INFO
| #define RISCV_INFO | ( | R | ) | struct riscv_info *R = riscv_info(target); |
◆ RISCV_MAX_HARTS
◆ RISCV_MAX_HWBPS
◆ RISCV_MAX_REGISTERS
◆ RISCV_MAX_TRIGGERS
◆ RISCV_NUM_MEM_ACCESS_METHODS
◆ RISCV_PGSHIFT
◆ RISCV_SAMPLE_BUF_TIMESTAMP_AFTER
◆ RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE
◆ RISCV_SATP_MODE
| #define RISCV_SATP_MODE | ( | xlen | ) | ((xlen) == 32 ? SATP32_MODE : SATP64_MODE) |
◆ RISCV_SATP_PPN
| #define RISCV_SATP_PPN | ( | xlen | ) | ((xlen) == 32 ? SATP32_PPN : SATP64_PPN) |
Typedef Documentation
◆ riscv_addr_t
| typedef uint64_t riscv_addr_t |
◆ riscv_insn_t
| typedef uint32_t riscv_insn_t |
◆ riscv_reg_t
| typedef uint64_t riscv_reg_t |
Enumeration Type Documentation
◆ bscan_tunnel_type_t
| enum bscan_tunnel_type_t |
◆ riscv_halt_reason
| enum riscv_halt_reason |
◆ riscv_mem_access_method
Function Documentation
◆ COMMAND_HELPER()
| COMMAND_HELPER | ( | riscv_print_info_line | , |
| const char * | section, | ||
| const char * | key, | ||
| unsigned int | value | ||
| ) |
Definition at line 2837 of file riscv.c.
References CMD, and command_print().
◆ dtmcontrol_scan_via_bscan()
| uint32_t dtmcontrol_scan_via_bscan | ( | struct target * | target, |
| uint32_t | out | ||
| ) |
Definition at line 293 of file riscv.c.
References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_ir_width, bscan_tunnel_type, bscan_zero, buf_get_u32(), buf_set_u32(), ERROR_OK, scan_field::in_value, ir_dtmcontrol, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, NULL, scan_field::num_bits, scan_field::out_value, select_dmi_via_bscan(), select_user4, target::tap, and TAP_IDLE.
Referenced by dtmcontrol_scan().
◆ is_riscv()
|
inlinestatic |
Definition at line 273 of file riscv.h.
References riscv_info::common_magic, and RISCV_COMMON_MAGIC.
Referenced by fespi_write().
◆ riscv_add_bscan_tunneled_scan()
| void riscv_add_bscan_tunneled_scan | ( | struct target * | target, |
| struct scan_field * | field, | ||
| riscv_bscan_tunneled_scan_context_t * | ctxt | ||
| ) |
Definition at line 4415 of file riscv.c.
References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_type, bscan_zero, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), scan_field::num_bits, scan_field::out_value, select_user4, target::tap, TAP_IDLE, riscv_bscan_tunneled_scan_context_t::tunneled_dr, and riscv_bscan_tunneled_scan_context_t::tunneled_dr_width.
Referenced by dmi_scan(), and riscv_batch_run().
◆ riscv_add_watchpoint()
| int riscv_add_watchpoint | ( | struct target * | target, |
| struct watchpoint * | watchpoint | ||
| ) |
Definition at line 988 of file riscv.c.
References add_trigger(), ERROR_OK, watchpoint::is_set, and trigger_from_watchpoint().
Referenced by enable_triggers(), and strict_step().
◆ riscv_count_harts()
| int riscv_count_harts | ( | struct target * | target | ) |
Definition at line 3242 of file riscv.c.
References RISCV_INFO.
Referenced by deassert_reset(), and examine().
◆ riscv_current_hartid()
| int riscv_current_hartid | ( | const struct target * | target | ) |
Definition at line 3236 of file riscv.c.
References RISCV_INFO.
Referenced by register_read_direct(), register_write_direct(), riscv013_halt_reason(), riscv_hit_watchpoint(), riscv_openocd_poll(), and riscv_set_current_hartid().
◆ riscv_debug_buffer_size()
| size_t riscv_debug_buffer_size | ( | struct target * | target | ) |
Definition at line 3388 of file riscv.c.
References RISCV_INFO.
Referenced by riscv_program_ebreak(), riscv_program_exec(), and riscv_program_insert().
◆ riscv_dmi_write_u64_bits()
| int riscv_dmi_write_u64_bits | ( | struct target * | target | ) |
Definition at line 3431 of file riscv.c.
References RISCV_INFO.
Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().
◆ riscv_enumerate_triggers()
| int riscv_enumerate_triggers | ( | struct target * | target | ) |
Count triggers, and initialize trigger_count for each hart.
trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.
Definition at line 3444 of file riscv.c.
References ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, get_field, LOG_DEBUG, LOG_INFO, MCONTROL_DMODE, MCONTROL_TYPE, riscv_get_register(), RISCV_INFO, RISCV_MAX_TRIGGERS, riscv_set_register(), riscv_xlen(), target_name(), and type.
Referenced by add_trigger(), COMMAND_HANDLER(), disable_triggers(), handle_halt(), register_set(), and remove_trigger().
◆ riscv_execute_debug_buffer()
| int riscv_execute_debug_buffer | ( | struct target * | target | ) |
◆ riscv_fill_dmi_nop_u64()
| void riscv_fill_dmi_nop_u64 | ( | struct target * | target, |
| char * | buf | ||
| ) |
Definition at line 3425 of file riscv.c.
References RISCV_INFO.
Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().
◆ riscv_fill_dmi_read_u64()
| void riscv_fill_dmi_read_u64 | ( | struct target * | target, |
| char * | buf, | ||
| int | a | ||
| ) |
Definition at line 3419 of file riscv.c.
References RISCV_INFO.
Referenced by riscv_batch_add_dmi_read().
◆ riscv_fill_dmi_write_u64()
| void riscv_fill_dmi_write_u64 | ( | struct target * | target, |
| char * | buf, | ||
| int | a, | ||
| uint64_t | d | ||
| ) |
Definition at line 3413 of file riscv.c.
References RISCV_INFO.
Referenced by riscv_batch_add_dmi_write().
◆ riscv_get_register()
| int riscv_get_register | ( | struct target * | target, |
| riscv_reg_t * | value, | ||
| enum gdb_regno | r | ||
| ) |
Get register, from the cache if it's in there.
Definition at line 3331 of file riscv.c.
References buf_get_u64(), ERROR_FAIL, ERROR_OK, reg::exist, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_XPR15, GDB_REGNO_XPR31, keep_alive(), LOG_DEBUG, target::reg_cache, reg_cache::reg_list, RISCV_INFO, riscv_supports_extension(), reg::size, target_name(), reg::valid, and reg::value.
Referenced by add_trigger(), disable_triggers(), enable_triggers(), maybe_add_trigger_t1(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), register_get(), remove_trigger(), riscv_address_translate(), riscv_enumerate_triggers(), riscv_hit_watchpoint(), riscv_mmu(), riscv_program_exec(), and riscv_run_algorithm().
◆ riscv_halt()
| int riscv_halt | ( | struct target * | target | ) |
Definition at line 1226 of file riscv.c.
References target::coreid, ERROR_FAIL, ERROR_OK, foreach_smp_target, get_target_type(), target_type::halt, halt_finish(), halt_go(), halt_prep(), LOG_DEBUG, riscv_info::prepped, riscv_info(), RISCV_INFO, target::smp, target::smp_targets, and target_list::target.
Referenced by riscv013_step_or_resume_current_hart(), riscv_openocd_poll(), and riscv_run_algorithm().
◆ riscv_info()
|
inlinestatic |
Definition at line 266 of file riscv.h.
References target::arch_info.
Referenced by examine(), fespi_write(), riscv_halt(), riscv_openocd_poll(), riscv_resume(), and select_prepped_harts().
◆ riscv_init_registers()
| int riscv_init_registers | ( | struct target * | target | ) |
Definition at line 3787 of file riscv.c.
References reg::arch_info, ARRAY_SIZE, reg::caller_save, cmp_csr_info(), CSR_CYCLEH, CSR_FCSR, CSR_FFLAGS, CSR_FRM, CSR_HPMCOUNTER10H, CSR_HPMCOUNTER11H, CSR_HPMCOUNTER12H, CSR_HPMCOUNTER13H, CSR_HPMCOUNTER14H, CSR_HPMCOUNTER15H, CSR_HPMCOUNTER16H, CSR_HPMCOUNTER17H, CSR_HPMCOUNTER18H, CSR_HPMCOUNTER19H, CSR_HPMCOUNTER20H, CSR_HPMCOUNTER21H, CSR_HPMCOUNTER22H, CSR_HPMCOUNTER23H, CSR_HPMCOUNTER24H, CSR_HPMCOUNTER25H, CSR_HPMCOUNTER26H, CSR_HPMCOUNTER27H, CSR_HPMCOUNTER28H, CSR_HPMCOUNTER29H, CSR_HPMCOUNTER30H, CSR_HPMCOUNTER31H, CSR_HPMCOUNTER3H, CSR_HPMCOUNTER4H, CSR_HPMCOUNTER5H, CSR_HPMCOUNTER6H, CSR_HPMCOUNTER7H, CSR_HPMCOUNTER8H, CSR_HPMCOUNTER9H, CSR_INSTRETH, CSR_MCYCLEH, CSR_MEDELEG, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MIDELEG, CSR_MINSTRETH, CSR_PMPCFG1, CSR_PMPCFG3, CSR_SATP, CSR_SCAUSE, CSR_SCOUNTEREN, CSR_SEPC, CSR_SIE, CSR_SIP, CSR_SSCRATCH, CSR_SSTATUS, CSR_STVAL, CSR_STVEC, CSR_TIMEH, CSR_VL, CSR_VLENB, CSR_VSTART, CSR_VTYPE, CSR_VXRM, CSR_VXSAT, reg::dirty, DIV_ROUND_UP, ERROR_FAIL, ERROR_OK, reg::exist, reg::feature, reg_data_type_union::fields, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2, GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6, GDB_REGNO_A7, GDB_REGNO_COUNT, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_FA0, GDB_REGNO_FA1, GDB_REGNO_FA2, GDB_REGNO_FA3, GDB_REGNO_FA4, GDB_REGNO_FA5, GDB_REGNO_FA6, GDB_REGNO_FA7, GDB_REGNO_FP, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_FS0, GDB_REGNO_FS1, GDB_REGNO_FS10, GDB_REGNO_FS11, GDB_REGNO_FS2, GDB_REGNO_FS3, GDB_REGNO_FS4, GDB_REGNO_FS5, GDB_REGNO_FS6, GDB_REGNO_FS7, GDB_REGNO_FS8, GDB_REGNO_FS9, GDB_REGNO_FT0, GDB_REGNO_FT1, GDB_REGNO_FT10, GDB_REGNO_FT11, GDB_REGNO_FT2, GDB_REGNO_FT3, GDB_REGNO_FT4, GDB_REGNO_FT5, GDB_REGNO_FT6, GDB_REGNO_FT7, GDB_REGNO_FT8, GDB_REGNO_FT9, GDB_REGNO_GP, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_RA, GDB_REGNO_S1, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4, GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8, GDB_REGNO_S9, GDB_REGNO_SP, GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_T3, GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6, GDB_REGNO_TP, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_XPR15, GDB_REGNO_XPR31, GDB_REGNO_ZERO, reg::group, range_list_t::high, info, list_empty(), list_first_entry, list_for_each_entry, list_rotate_left(), LOG_DEBUG, range_list_t::low, reg_feature::name, reg::name, reg_cache::name, csr_info::name, range_list_t::name, NULL, reg_cache::num_regs, number, reg::number, target::reg_cache, reg::reg_data_type, reg_cache::reg_list, REG_TYPE_ARCH_DEFINED, REG_TYPE_CLASS_UNION, REG_TYPE_CLASS_VECTOR, REG_TYPE_IEEE_DOUBLE, REG_TYPE_IEEE_SINGLE, REG_TYPE_UINT128, REG_TYPE_UINT16, REG_TYPE_UINT32, REG_TYPE_UINT64, REG_TYPE_UINT8, riscv_free_registers(), RISCV_INFO, riscv_reg_arch_type, riscv_supports_extension(), riscv_xlen(), reg::size, target, riscv_reg_info_t::target, reg_data_type::type, reg::type, reg::valid, and reg::value.
Referenced by examine(), and init_target().
◆ riscv_is_halted()
| bool riscv_is_halted | ( | struct target * | target | ) |
Definition at line 3369 of file riscv.c.
Referenced by examine(), halt_prep(), register_write_direct(), riscv013_halt_go(), riscv013_step_or_resume_current_hart(), riscv_halt_go_all_harts(), riscv_resume_go_all_harts(), riscv_resume_prep_all_harts(), and riscv_step_rtos_hart().
◆ riscv_openocd_assert_reset()
| int riscv_openocd_assert_reset | ( | struct target * | target | ) |
◆ riscv_openocd_deassert_reset()
| int riscv_openocd_deassert_reset | ( | struct target * | target | ) |
◆ riscv_openocd_poll()
| int riscv_openocd_poll | ( | struct target * | target | ) |
Definition at line 2184 of file riscv.c.
References riscv_info::current_hartid, DBG_REASON_BREAKPOINT, DBG_REASON_NOTHALTED, target::debug_reason, ERROR_FAIL, ERROR_OK, foreach_smp_target, riscv_info::halt_reason, LOG_DEBUG, LOG_WARNING, riscv_current_hartid(), riscv_halt(), RISCV_HALT_BREAKPOINT, RISCV_HALT_GROUP, riscv_halt_reason(), riscv_info(), riscv_resume(), riscv_semihosting(), RPH_DISCOVERED_HALTED, RPH_DISCOVERED_RUNNING, RPH_ERROR, RPH_NO_CHANGE, sample_memory(), SEMIHOSTING_ERROR, SEMIHOSTING_HANDLED, SEMIHOSTING_NONE, SEMIHOSTING_WAITING, set_debug_reason(), target::smp, target::smp_targets, target::state, target_list::target, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_HALTED, and TARGET_RUNNING.
Referenced by old_or_new_riscv_poll().
◆ riscv_openocd_step()
| int riscv_openocd_step | ( | struct target * | target, |
| int | current, | ||
| target_addr_t | address, | ||
| int | handle_breakpoints | ||
| ) |
Definition at line 2303 of file riscv.c.
References DBG_REASON_SINGLESTEP, target::debug_reason, disable_triggers(), enable_triggers(), ERROR_FAIL, ERROR_OK, GDB_REGNO_PC, LOG_DEBUG, LOG_ERROR, target::reg_cache, register_cache_invalidate(), RISCV_MAX_HWBPS, riscv_set_register(), riscv_step_rtos_hart(), target::state, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_EVENT_RESUMED, TARGET_HALTED, and TARGET_RUNNING.
Referenced by old_or_new_riscv_step().
◆ riscv_read_by_any_size()
| int riscv_read_by_any_size | ( | struct target * | target, |
| target_addr_t | address, | ||
| uint32_t | size, | ||
| uint8_t * | buffer | ||
| ) |
Read one memory item using any memory access size that will work.
Read larger section of memory and pick out the required portion, if needed.
Definition at line 837 of file riscv.c.
References buffer, ERROR_FAIL, ERROR_OK, read_by_given_size(), and size.
Referenced by riscv_add_breakpoint().
◆ riscv_read_debug_buffer()
| riscv_insn_t riscv_read_debug_buffer | ( | struct target * | target, |
| int | index | ||
| ) |
◆ riscv_remove_watchpoint()
| int riscv_remove_watchpoint | ( | struct target * | target, |
| struct watchpoint * | watchpoint | ||
| ) |
Definition at line 1001 of file riscv.c.
References watchpoint::address, target::coreid, ERROR_OK, watchpoint::is_set, LOG_DEBUG, remove_trigger(), TARGET_PRIxADDR, and trigger_from_watchpoint().
Referenced by disable_triggers(), and strict_step().
◆ riscv_select_current_hart()
| int riscv_select_current_hart | ( | struct target * | target | ) |
Definition at line 1161 of file riscv.c.
References target::coreid, and riscv_set_current_hartid().
Referenced by halt_prep(), riscv013_get_register(), riscv013_get_register_buf(), riscv013_set_register_buf(), riscv_get_gdb_reg_list_internal(), riscv_halt_go_all_harts(), riscv_read_memory(), riscv_read_phys_memory(), riscv_resume_go_all_harts(), riscv_resume_prep_all_harts(), riscv_run_algorithm(), riscv_step_rtos_hart(), riscv_write_memory(), and riscv_write_phys_memory().
◆ riscv_semihosting()
| enum semihosting_result riscv_semihosting | ( | struct target * | target, |
| int * | retval | ||
| ) |
Check for and process a semihosting request using the ARM protocol).
This is meant to be called when the target is stopped due to a debug mode entry.
- Parameters
-
target Pointer to the target to process. retval Pointer to a location where the return code will be stored
- Returns
- non-zero value if a request was processed or an error encountered
Definition at line 42 of file riscv_semihosting.c.
References riscv_semihosting_post_result(), riscv_semihosting_setup(), and semihosting_common_init().
Referenced by handle_halt(), and riscv_openocd_poll().
◆ riscv_semihosting_init()
| void riscv_semihosting_init | ( | struct target * | target | ) |
Initialize RISC-V semihosting.
Use common ARM code.
Definition at line 42 of file riscv_semihosting.c.
Referenced by riscv_init_target().
◆ riscv_set_current_hartid()
| int riscv_set_current_hartid | ( | struct target * | target, |
| int | hartid | ||
| ) |
Definition at line 3210 of file riscv.c.
References ERROR_FAIL, ERROR_OK, LOG_DEBUG, riscv_current_hartid(), and RISCV_INFO.
Referenced by examine(), and riscv_select_current_hart().
◆ riscv_set_register()
| int riscv_set_register | ( | struct target * | target, |
| enum gdb_regno | regid, | ||
| riscv_reg_t | value | ||
| ) |
Set register, updating the cache.
Set register, updating the cache.
The new value may be cached, and may not be written until the hart is resumed.
Definition at line 3305 of file riscv.c.
References buf_set_u64(), ERROR_OK, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_XPR15, GDB_REGNO_XPR31, keep_alive(), LOG_DEBUG, reg::name, target::reg_cache, reg_cache::reg_list, RISCV_INFO, riscv_supports_extension(), reg::size, target_name(), reg::valid, and reg::value.
Referenced by add_trigger(), disable_triggers(), enable_triggers(), maybe_add_trigger_t1(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), read_memory_progbuf(), read_memory_progbuf_one(), register_set(), remove_trigger(), resume_prep(), riscv013_on_step_or_resume(), riscv_enumerate_triggers(), riscv_openocd_step(), riscv_program_exec(), and riscv_semihosting_post_result().
◆ riscv_supports_extension()
| bool riscv_supports_extension | ( | struct target * | target, |
| char | letter | ||
| ) |
Definition at line 3191 of file riscv.c.
References BIT, and RISCV_INFO.
Referenced by examine(), register_read_direct(), register_write_direct(), riscv_get_register(), riscv_init_registers(), and riscv_set_register().
◆ riscv_write_by_any_size()
| int riscv_write_by_any_size | ( | struct target * | target, |
| target_addr_t | address, | ||
| uint32_t | size, | ||
| uint8_t * | buffer | ||
| ) |
Write one memory item using any memory access size that will work.
Utilize read-modify-write, if needed.
Definition at line 805 of file riscv.c.
References buffer, ERROR_FAIL, ERROR_OK, size, and write_by_given_size().
Referenced by riscv_add_breakpoint(), and riscv_remove_breakpoint().
◆ riscv_write_debug_buffer()
| int riscv_write_debug_buffer | ( | struct target * | target, |
| int | index, | ||
| riscv_insn_t | insn | ||
| ) |
Definition at line 3394 of file riscv.c.
References ERROR_OK, and RISCV_INFO.
Referenced by riscv_program_write().
◆ riscv_xlen()
| unsigned riscv_xlen | ( | const struct target * | target | ) |
Definition at line 3204 of file riscv.c.
References RISCV_INFO.
Referenced by add_trigger(), cache_get(), cache_set(), COMMAND_HANDLER(), disable_triggers(), examine(), execute_resume(), fespi_write(), get_register(), handle_halt_routine(), load(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), mem_should_skip_abstract(), mem_should_skip_progbuf(), prep_for_vector_access(), read_memory_abstract(), read_memory_progbuf(), read_memory_progbuf_inner(), read_memory_progbuf_one(), register_read_direct(), register_size(), register_write(), register_write_direct(), riscv013_data_bits(), riscv013_get_register_buf(), riscv013_set_register_buf(), riscv_address_translate(), riscv_checksum_memory(), riscv_data_bits(), riscv_enumerate_triggers(), riscv_get_gdb_arch(), riscv_init_registers(), riscv_mmu(), riscv_program_init(), riscv_xlen_nonconst(), scans_add_read(), scans_new(), slot_offset(), step(), store(), write_memory_abstract(), and write_memory_progbuf().
◆ riscv_xlen_of_hart()
| int riscv_xlen_of_hart | ( | const struct target * | target | ) |
◆ select_dmi_via_bscan()
| void select_dmi_via_bscan | ( | struct target * | target | ) |
Definition at line 282 of file riscv.c.
References BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_data_register_select_dmi, bscan_tunnel_data_register_select_dmi_num_fields, bscan_tunnel_nested_tap_select_dmi, bscan_tunnel_nested_tap_select_dmi_num_fields, bscan_tunnel_type, jtag_add_dr_scan(), jtag_add_ir_scan(), select_user4, target::tap, and TAP_IDLE.
Referenced by dtmcontrol_scan_via_bscan(), and select_dmi().
Variable Documentation
◆ bscan_tunnel_ir_width
|
extern |
Definition at line 129 of file riscv.c.
Referenced by COMMAND_HANDLER(), dmi_scan(), dtmcontrol_scan(), dtmcontrol_scan_via_bscan(), riscv_batch_alloc(), riscv_batch_run(), riscv_init_target(), and select_dmi().
◆ bscan_tunneled_select_dmi
|
extern |
◆ bscan_tunneled_select_dmi_num_fields
|
extern |
◆ riscv011_target
|
extern |
Definition at line 2371 of file riscv-011.c.
Referenced by get_target_type().
◆ riscv013_target
|
extern |
Definition at line 4042 of file riscv-013.c.
Referenced by get_target_type().
◆ riscv_command_timeout_sec
|
extern |
Definition at line 203 of file riscv.c.
Referenced by COMMAND_HANDLER(), dmi_op(), dmstatus_read(), full_step(), read_sbcs_nonbusy(), riscv013_clear_abstract_error(), wait_for_authbusy(), wait_for_debugint_clear(), wait_for_idle(), wait_for_state(), and write_memory_bus_v1().
◆ riscv_ebreakm
|
extern |
Definition at line 209 of file riscv.c.
Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().
◆ riscv_ebreaks
|
extern |
Definition at line 210 of file riscv.c.
Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().
◆ riscv_ebreaku
|
extern |
Definition at line 211 of file riscv.c.
Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().
◆ riscv_enable_virtual
|
extern |
Definition at line 213 of file riscv.c.
Referenced by COMMAND_HANDLER(), examine(), modify_privilege(), read_memory_progbuf(), read_memory_progbuf_one(), and write_memory_progbuf().
◆ riscv_reset_timeout_sec
|
extern |
Definition at line 206 of file riscv.c.
Referenced by COMMAND_HANDLER(), and deassert_reset().
◆ select_dbus
|
extern |
Definition at line 117 of file riscv.c.
Referenced by assert_reset(), deassert_reset(), dtmcontrol_scan(), halt(), idcode_scan(), poll_target(), read_memory(), riscv011_resume(), riscv_init_target(), select_dmi(), step(), and write_memory().
◆ select_dtmcontrol
|
extern |
Definition at line 112 of file riscv.c.
Referenced by dtmcontrol_scan(), and riscv_init_target().
◆ select_idcode
|
extern |
Definition at line 122 of file riscv.c.
Referenced by idcode_scan(), and riscv_init_target().
