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Macros | |
| #define | CSR_CONFIG 0x05 |
| #define | CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */ |
| #define | CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */ |
| #define | CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */ |
| #define | CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */ |
| #define | CSR_CONFIG_DBG 0x0f /* Debug Configuration */ |
| #define | CSR_CONFIG_DC 0x06 /* Data Cache Configuration */ |
| #define | CSR_CONFIG_FREQ_N 0x13 /* Frequency [0..2] */ |
| #define | CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */ |
| #define | CSR_CONFIG_INT 0x07 /* Interrupt Configuration */ |
| #define | CSR_CONFIG_ISA_N 0x08 /* Instruction Set Configuration [0..6] */ |
| #define | CSR_CONFIG_MEM 0x04 /* Memory Configuration */ |
| #define | CSR_CONFIG_MID 0x10 /* Manufacturer ID */ |
| #define | CSR_CONFIG_MPID 0x12 /* Multiprocessor ID */ |
| #define | CSR_CONFIG_REV 0x11 /* Revision Number */ |
| #define | CSR_CONFIG_TRACE 0x16 /* Trace Configuration */ |
| #define | CSR_DEBUG 0x04 |
| #define | CSR_DEBUG_DBA_N 0x10 /* Data Breakpoint Address [0..7] */ |
| #define | CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */ |
| #define | CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */ |
| #define | CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */ |
| #define | CSR_DEBUG_DC 0x00 /* Debug Control */ |
| #define | CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */ |
| #define | CSR_DEBUG_IBA_N 0x08 /* Instruction Breakpoint Address [0..7] */ |
| #define | CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */ |
| #define | CSR_INTERRUPT 0x01 |
| #define | CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */ |
| #define | CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */ |
| #define | CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */ |
| #define | CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */ |
| #define | CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */ |
| #define | CSR_THREAD 0x00 |
| #define | CSR_THREAD_AC 0x03 /* Arithmetic Control */ |
| #define | CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */ |
| #define | CSR_THREAD_ECAS 0x0a /* Exception CAS */ |
| #define | CSR_THREAD_ED 0x0c /* Exception Data */ |
| #define | CSR_THREAD_EID 0x0b /* Exception ID */ |
| #define | CSR_THREAD_EPC 0x09 /* Exception PC */ |
| #define | CSR_THREAD_ETA 0x07 /* Exception Table Address */ |
| #define | CSR_THREAD_ETC 0x08 /* Exception TC */ |
| #define | CSR_THREAD_LA 0x05 /* Locked Address */ |
| #define | CSR_THREAD_LF 0x04 /* Locked Flag */ |
| #define | CSR_THREAD_PC 0x01 /* Program Counter */ |
| #define | CSR_THREAD_TC 0x00 /* Thread Control */ |
| #define | CSR_TRACE 0x09 |
| #define | CSR_TRACE_BUFFER_CUR 0x04 |
| #define | CSR_TRACE_BUFFER_END 0x03 |
| #define | CSR_TRACE_BUFFER_START 0x02 |
| #define | CSR_TRACE_CONTROL 0x00 |
| #define | CSR_TRACE_DELAY 0x0a |
| #define | CSR_TRACE_START_DATA 0x06 |
| #define | CSR_TRACE_START_MASK 0x07 |
| #define | CSR_TRACE_STATUS 0x01 |
| #define | CSR_TRACE_STOP_DATA 0x08 |
| #define | CSR_TRACE_STOP_MASK 0x09 |
| #define | CSR_TRACE_TRIGGER 0x05 |
Macro Definition Documentation
◆ CSR_CONFIG
| #define CSR_CONFIG 0x05 |
Definition at line 109 of file esirisc_regs.h.
◆ CSR_CONFIG_ARCH0
| #define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */ |
Definition at line 144 of file esirisc_regs.h.
◆ CSR_CONFIG_ARCH1
| #define CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */ |
Definition at line 145 of file esirisc_regs.h.
◆ CSR_CONFIG_ARCH2
| #define CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */ |
Definition at line 146 of file esirisc_regs.h.
◆ CSR_CONFIG_ARCH3
| #define CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */ |
Definition at line 147 of file esirisc_regs.h.
◆ CSR_CONFIG_DBG
| #define CSR_CONFIG_DBG 0x0f /* Debug Configuration */ |
Definition at line 153 of file esirisc_regs.h.
◆ CSR_CONFIG_DC
| #define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */ |
Definition at line 150 of file esirisc_regs.h.
◆ CSR_CONFIG_FREQ_N
| #define CSR_CONFIG_FREQ_N 0x13 /* Frequency [0..2] */ |
Definition at line 157 of file esirisc_regs.h.
◆ CSR_CONFIG_IC
| #define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */ |
Definition at line 149 of file esirisc_regs.h.
◆ CSR_CONFIG_INT
| #define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */ |
Definition at line 151 of file esirisc_regs.h.
◆ CSR_CONFIG_ISA_N
| #define CSR_CONFIG_ISA_N 0x08 /* Instruction Set Configuration [0..6] */ |
Definition at line 152 of file esirisc_regs.h.
◆ CSR_CONFIG_MEM
| #define CSR_CONFIG_MEM 0x04 /* Memory Configuration */ |
Definition at line 148 of file esirisc_regs.h.
◆ CSR_CONFIG_MID
| #define CSR_CONFIG_MID 0x10 /* Manufacturer ID */ |
Definition at line 154 of file esirisc_regs.h.
◆ CSR_CONFIG_MPID
| #define CSR_CONFIG_MPID 0x12 /* Multiprocessor ID */ |
Definition at line 156 of file esirisc_regs.h.
◆ CSR_CONFIG_REV
| #define CSR_CONFIG_REV 0x11 /* Revision Number */ |
Definition at line 155 of file esirisc_regs.h.
◆ CSR_CONFIG_TRACE
| #define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */ |
Definition at line 158 of file esirisc_regs.h.
◆ CSR_DEBUG
| #define CSR_DEBUG 0x04 |
Definition at line 108 of file esirisc_regs.h.
◆ CSR_DEBUG_DBA_N
| #define CSR_DEBUG_DBA_N 0x10 /* Data Breakpoint Address [0..7] */ |
Definition at line 141 of file esirisc_regs.h.
◆ CSR_DEBUG_DBC
| #define CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */ |
Definition at line 136 of file esirisc_regs.h.
◆ CSR_DEBUG_DBR
| #define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */ |
Definition at line 139 of file esirisc_regs.h.
◆ CSR_DEBUG_DBS
| #define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */ |
Definition at line 138 of file esirisc_regs.h.
◆ CSR_DEBUG_DC
| #define CSR_DEBUG_DC 0x00 /* Debug Control */ |
Definition at line 134 of file esirisc_regs.h.
◆ CSR_DEBUG_HWDC
| #define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */ |
Definition at line 137 of file esirisc_regs.h.
◆ CSR_DEBUG_IBA_N
| #define CSR_DEBUG_IBA_N 0x08 /* Instruction Breakpoint Address [0..7] */ |
Definition at line 140 of file esirisc_regs.h.
◆ CSR_DEBUG_IBC
| #define CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */ |
Definition at line 135 of file esirisc_regs.h.
◆ CSR_INTERRUPT
| #define CSR_INTERRUPT 0x01 |
Definition at line 107 of file esirisc_regs.h.
◆ CSR_INTERRUPT_IA
| #define CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */ |
Definition at line 128 of file esirisc_regs.h.
◆ CSR_INTERRUPT_IM
| #define CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */ |
Definition at line 129 of file esirisc_regs.h.
◆ CSR_INTERRUPT_IP
| #define CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */ |
Definition at line 127 of file esirisc_regs.h.
◆ CSR_INTERRUPT_IS
| #define CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */ |
Definition at line 130 of file esirisc_regs.h.
◆ CSR_INTERRUPT_IT
| #define CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */ |
Definition at line 131 of file esirisc_regs.h.
◆ CSR_THREAD
| #define CSR_THREAD 0x00 |
Definition at line 106 of file esirisc_regs.h.
◆ CSR_THREAD_AC
| #define CSR_THREAD_AC 0x03 /* Arithmetic Control */ |
Definition at line 116 of file esirisc_regs.h.
◆ CSR_THREAD_CAS
| #define CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */ |
Definition at line 115 of file esirisc_regs.h.
◆ CSR_THREAD_ECAS
| #define CSR_THREAD_ECAS 0x0a /* Exception CAS */ |
Definition at line 122 of file esirisc_regs.h.
◆ CSR_THREAD_ED
| #define CSR_THREAD_ED 0x0c /* Exception Data */ |
Definition at line 124 of file esirisc_regs.h.
◆ CSR_THREAD_EID
| #define CSR_THREAD_EID 0x0b /* Exception ID */ |
Definition at line 123 of file esirisc_regs.h.
◆ CSR_THREAD_EPC
| #define CSR_THREAD_EPC 0x09 /* Exception PC */ |
Definition at line 121 of file esirisc_regs.h.
◆ CSR_THREAD_ETA
| #define CSR_THREAD_ETA 0x07 /* Exception Table Address */ |
Definition at line 119 of file esirisc_regs.h.
◆ CSR_THREAD_ETC
| #define CSR_THREAD_ETC 0x08 /* Exception TC */ |
Definition at line 120 of file esirisc_regs.h.
◆ CSR_THREAD_LA
| #define CSR_THREAD_LA 0x05 /* Locked Address */ |
Definition at line 118 of file esirisc_regs.h.
◆ CSR_THREAD_LF
| #define CSR_THREAD_LF 0x04 /* Locked Flag */ |
Definition at line 117 of file esirisc_regs.h.
◆ CSR_THREAD_PC
| #define CSR_THREAD_PC 0x01 /* Program Counter */ |
Definition at line 114 of file esirisc_regs.h.
◆ CSR_THREAD_TC
| #define CSR_THREAD_TC 0x00 /* Thread Control */ |
Definition at line 113 of file esirisc_regs.h.
◆ CSR_TRACE
| #define CSR_TRACE 0x09 |
Definition at line 110 of file esirisc_regs.h.
◆ CSR_TRACE_BUFFER_CUR
| #define CSR_TRACE_BUFFER_CUR 0x04 |
Definition at line 165 of file esirisc_regs.h.
◆ CSR_TRACE_BUFFER_END
| #define CSR_TRACE_BUFFER_END 0x03 |
Definition at line 164 of file esirisc_regs.h.
◆ CSR_TRACE_BUFFER_START
| #define CSR_TRACE_BUFFER_START 0x02 |
Definition at line 163 of file esirisc_regs.h.
◆ CSR_TRACE_CONTROL
| #define CSR_TRACE_CONTROL 0x00 |
Definition at line 161 of file esirisc_regs.h.
◆ CSR_TRACE_DELAY
| #define CSR_TRACE_DELAY 0x0a |
Definition at line 171 of file esirisc_regs.h.
◆ CSR_TRACE_START_DATA
| #define CSR_TRACE_START_DATA 0x06 |
Definition at line 167 of file esirisc_regs.h.
◆ CSR_TRACE_START_MASK
| #define CSR_TRACE_START_MASK 0x07 |
Definition at line 168 of file esirisc_regs.h.
◆ CSR_TRACE_STATUS
| #define CSR_TRACE_STATUS 0x01 |
Definition at line 162 of file esirisc_regs.h.
◆ CSR_TRACE_STOP_DATA
| #define CSR_TRACE_STOP_DATA 0x08 |
Definition at line 169 of file esirisc_regs.h.
◆ CSR_TRACE_STOP_MASK
| #define CSR_TRACE_STOP_MASK 0x09 |
Definition at line 170 of file esirisc_regs.h.
◆ CSR_TRACE_TRIGGER
| #define CSR_TRACE_TRIGGER 0x05 |
Definition at line 166 of file esirisc_regs.h.
Enumeration Type Documentation
◆ esirisc_reg_num
| enum esirisc_reg_num |
Definition at line 12 of file esirisc_regs.h.
