Basic support for the 5680xx DSP from Freescale. The chip has two taps in the JTAG chain, the Master tap and the Core tap. In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction. More...

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Data Structures
struct	dsp5680xx_common

Macros
#define	DSP5680XX_ERROR_ENTER_DEBUG_MODE -12

#define	DSP5680XX_ERROR_EXIT_DEBUG_MODE -26

#define	DSP5680XX_ERROR_FLASHING -23

#define	DSP5680XX_ERROR_FLASHING_CRC -22

#define	DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT -21

#define	DSP5680XX_ERROR_FM_BUSY -17

#define	DSP5680XX_ERROR_FM_CMD_TIMED_OUT -18

#define	DSP5680XX_ERROR_FM_EXEC -19

#define	DSP5680XX_ERROR_FM_SET_CLK -20

#define	DSP5680XX_ERROR_HALT -25

#define	DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT -15

#define	DSP5680XX_ERROR_INVALID_IR_LEN -5

#define	DSP5680XX_ERROR_JTAG_COMM -1

#define	DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW -4

#define	DSP5680XX_ERROR_JTAG_DRSCAN -10

#define	DSP5680XX_ERROR_JTAG_INVALID_TAP -3

#define	DSP5680XX_ERROR_JTAG_IRSCAN -11

#define	DSP5680XX_ERROR_JTAG_RESET -2

#define	DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE -7

#define	DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER -6

#define	DSP5680XX_ERROR_JTAG_TAP_FIND_CORE -9

#define	DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER -8

#define	DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP -24

#define	DSP5680XX_ERROR_NOT_IN_DEBUG -28

#define	DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS -16

#define	DSP5680XX_ERROR_RESUME -13

#define	DSP5680XX_ERROR_TARGET_RUNNING -27

#define	DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD -100

#define	DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING -14

#define	DSP5680XX_JTAG_CORE_TAP_IRLEN 4

#define	DSP5680XX_JTAG_MASTER_TAP_IRLEN 8

#define	DSP5680XX_ONCE_NOREG 0x00 /* No register selected */

#define	DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */

#define	DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */

#define	DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */

#define	DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */

#define	DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */

#define	DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */

#define	DSP5680XX_ONCE_OCR_EX (1<<5)

#define	DSP5680XX_ONCE_OCR_GO (1<<6)

#define	DSP5680XX_ONCE_OCR_RW (1<<7)

#define	DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */

#define	DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */

#define	DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */

#define	DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */

#define	DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */

#define	DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */

#define	DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */

#define	DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)

#define	DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0\|DSP5680XX_ONCE_OSCR_OS1)

#define	DSP5680XX_ONCE_OSCR_NORMAL_M (0)

#define	DSP5680XX_ONCE_OSCR_OS0 (1<<4)

#define	DSP5680XX_ONCE_OSCR_OS1 (1<<5)
	RW Bit Definition 0 Write To the Register Specified by the RS[4:0] Bits. More...

#define	DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)

#define	DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */

#define	DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */

#define	DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */

#define	DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */

#define	DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */

#define	EONCE_STAT_MASK 0x30

#define	FLUSH_COUNT_FLASH 8192

#define	FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */

#define	HFM_BASE_ADDR

#define	HFM_CALCULATE_DATA_SIGNATURE 0x06

#define	HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66

#define	HFM_CLK_DEFAULT 0x27
	The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM. More...

#define	HFM_CLK_DIV 0x00 /* r/w */
	The following are register addresses, not memory addresses (though all registers are memory mapped) More...

#define	HFM_CMD 0x14 /* r/w */

#define	HFM_CNFG 0x01 /* r/w */

#define	HFM_DATA 0x18 /* r */

#define	HFM_ERASE_VERIFY 0x05

#define	HFM_EXEC_COMPLETE 0x40

#define	HFM_FLASH_BASE_ADDR 0x0

#define	HFM_LOCK_ADDR_H 0x1FF8

#define	HFM_LOCK_ADDR_L 0x1FF7

#define	HFM_LOCK_FLASH 0xE70A
	Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset. More...

#define	HFM_MASS_ERASE 0x41

#define	HFM_OPT1 0x1B /* r */

#define	HFM_PAGE_ERASE 0x40

#define	HFM_PROT 0x10 /* r/w */

#define	HFM_PROTB 0x11 /* r/w */

#define	HFM_SECHI 0x03 /* r */

#define	HFM_SECLO 0x04 /* r */

#define	HFM_SECTOR_COUNT 0x20

#define	HFM_SECTOR_SIZE 0x200 /* Size in bytes */

#define	HFM_SIZE_BYTES 0x4000 /* bytes */

#define	HFM_SIZE_WORDS 0x2000 /* words */

#define	HFM_TSTSIG 0x1D /* r */

#define	HFM_USTAT 0x13 /* r/w */

#define	HFM_USTAT_MASK_BLANK 0x4

#define	HFM_USTAT_MASK_PVIOL_ACCER 0x30

#define	HFM_WORD_PROGRAM 0x20

#define	JTAG_INSTR_BYPASS 0xF

#define	JTAG_INSTR_CLAMP 0x5

#define	JTAG_INSTR_DEBUG_REQUEST 0x7

#define	JTAG_INSTR_ENABLE_ONCE 0x6

#define	JTAG_INSTR_EXTEST 0x0

#define	JTAG_INSTR_EXTEST_PULLUP 0x3

#define	JTAG_INSTR_HIGHZ 0x4

#define	JTAG_INSTR_IDCODE 0x2

#define	JTAG_INSTR_SAMPLE_PRELOAD 0x1

#define	JTAG_STATUS_BUSY 0x09

#define	JTAG_STATUS_DEAD 0x0f

#define	JTAG_STATUS_DEBUG 0x0D

#define	JTAG_STATUS_MASK 0x0F

#define	JTAG_STATUS_NORMAL 0x01

#define	JTAG_STATUS_STOPWAIT 0x05

#define	MASTER_TAP_CMD_BYPASS 0xF

#define	MASTER_TAP_CMD_FLASH_ERASE 0x8

#define	MASTER_TAP_CMD_IDCODE 0x2

#define	MASTER_TAP_CMD_TLM_SEL 0x5

#define	MC568013_EONCE_OBASE_ADDR 0xFF

#define	MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */

#define	MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */

#define	MC568013_EONCE_TX_RX_ADDR 0xFFFE

#define	MC568013_SIM_BASE_ADDR 0xF140

#define	MC56803X_2X_SIM_BASE_ADDR 0xF100

#define	S_FILE_DATA_OFFSET 0x200000

#define	SIM_CMD_RESET 0x10

#define	TIME_DIV_FREESCALE 0.3

Functions
int	dsp5680xx_f_erase (struct target *target, int first, int last)
	Erases either a sector or the complete flash array. More...

int	dsp5680xx_f_erase_check (struct target target, uint8_t erased, uint32_t sector)
	The FM has the functionality of checking if the flash array is erased. More...

int	dsp5680xx_f_lock (struct target *target)
	Writes the flash security words with a specific value. More...

int	dsp5680xx_f_protect_check (struct target target, uint16_t protected)
	Reads the memory mapped protection register. More...

int	dsp5680xx_f_unlock (struct target *target)
	Executes a mass erase command. More...

int	dsp5680xx_f_wr (struct target target, const uint8_t buffer, uint32_t address, uint32_t count, int is_flash_lock)
	Writes to flash memory. More...

static struct dsp5680xx_common *	target_to_dsp5680xx (struct target *target)

Detailed Description

Basic support for the 5680xx DSP from Freescale. The chip has two taps in the JTAG chain, the Master tap and the Core tap. In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction.

Author: Rodrigo Rosa rodri.nosp@m.goro.nosp@m.sa.LG.nosp@m.@gma.nosp@m.il.co.nosp@m.m

Date: Thu Jun 9 18:54:38 2011

Definition in file dsp5680xx.h.

Macro Definition Documentation

◆ DSP5680XX_ERROR_ENTER_DEBUG_MODE

#define DSP5680XX_ERROR_ENTER_DEBUG_MODE -12

Definition at line 252 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_EXIT_DEBUG_MODE

#define DSP5680XX_ERROR_EXIT_DEBUG_MODE -26

Definition at line 266 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FLASHING

#define DSP5680XX_ERROR_FLASHING -23

Definition at line 263 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FLASHING_CRC

#define DSP5680XX_ERROR_FLASHING_CRC -22

Definition at line 262 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT

#define DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT -21

Definition at line 261 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FM_BUSY

#define DSP5680XX_ERROR_FM_BUSY -17

Definition at line 257 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FM_CMD_TIMED_OUT

#define DSP5680XX_ERROR_FM_CMD_TIMED_OUT -18

Definition at line 258 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FM_EXEC

#define DSP5680XX_ERROR_FM_EXEC -19

Definition at line 259 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_FM_SET_CLK

#define DSP5680XX_ERROR_FM_SET_CLK -20

Definition at line 260 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_HALT

#define DSP5680XX_ERROR_HALT -25

Definition at line 265 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT

#define DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT -15

Definition at line 255 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_INVALID_IR_LEN

#define DSP5680XX_ERROR_INVALID_IR_LEN -5

Definition at line 245 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_COMM

#define DSP5680XX_ERROR_JTAG_COMM -1

Definition at line 241 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW

#define DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW -4

Definition at line 244 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_DRSCAN

#define DSP5680XX_ERROR_JTAG_DRSCAN -10

Definition at line 250 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_INVALID_TAP

#define DSP5680XX_ERROR_JTAG_INVALID_TAP -3

Definition at line 243 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_IRSCAN

#define DSP5680XX_ERROR_JTAG_IRSCAN -11

Definition at line 251 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_RESET

#define DSP5680XX_ERROR_JTAG_RESET -2

Definition at line 242 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE

#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE -7

Definition at line 247 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER

#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER -6

Definition at line 246 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_TAP_FIND_CORE

#define DSP5680XX_ERROR_JTAG_TAP_FIND_CORE -9

Definition at line 249 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER

#define DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER -8

Definition at line 248 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP

#define DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP -24

Definition at line 264 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_NOT_IN_DEBUG

#define DSP5680XX_ERROR_NOT_IN_DEBUG -28

Definition at line 268 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS

#define DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS -16

Definition at line 256 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_RESUME

#define DSP5680XX_ERROR_RESUME -13

Definition at line 253 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_TARGET_RUNNING

#define DSP5680XX_ERROR_TARGET_RUNNING -27

Definition at line 267 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD

#define DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD -100

ERROR codes - enable automatic parsing of output

Definition at line 240 of file dsp5680xx.h.

◆ DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING

#define DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING -14

Definition at line 254 of file dsp5680xx.h.

◆ DSP5680XX_JTAG_CORE_TAP_IRLEN

#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4

JTAG

Definition at line 34 of file dsp5680xx.h.

◆ DSP5680XX_JTAG_MASTER_TAP_IRLEN

#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8

Definition at line 35 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_NOREG

#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */

Register Select Encoding (eonce_rev.1.0_0208081.pdf:14)

Definition at line 120 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OBAR

#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */

Definition at line 124 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OBAR1

#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */

Definition at line 137 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OBASE

#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */

Definition at line 125 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCNTR

#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */

Definition at line 122 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCNTR_C

#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */

Definition at line 132 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCR

#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */

Definition at line 121 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCR_EX

#define DSP5680XX_ONCE_OCR_EX (1<<5)

EOnCE control register info

Definition at line 74 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCR_GO

#define DSP5680XX_ONCE_OCR_GO (1<<6)

Definition at line 78 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OCR_RW

#define DSP5680XX_ONCE_OCR_RW (1<<7)

Definition at line 82 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OPABDR

#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */

Definition at line 138 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OPABER

#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */

Definition at line 135 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OPABFR

#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */

Definition at line 130 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OPDBR

#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */

Definition at line 128 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OPFIFO

#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */

Definition at line 136 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_ORX

#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */

Definition at line 131 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_ORX1

#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */

Definition at line 133 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_BUSY_M

#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)

Definition at line 107 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_DEBUG_M

#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)

Definition at line 109 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_NORMAL_M

#define DSP5680XX_ONCE_OSCR_NORMAL_M (0)

EOnCE Core Status - Describes the operating status of the core controller

Definition at line 103 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_OS0

#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)

Definition at line 94 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_OS1

#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)

RW Bit Definition 0 Write To the Register Specified by the RS[4:0] Bits.

1 ReadFrom the Register Specified by the RS[4:0] Bits

EOnCE Status Register

Definition at line 93 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSCR_STOPWAIT_M

#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)

Definition at line 105 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OSR

#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */

Definition at line 123 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OTBCR

#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */

Definition at line 134 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OTX

#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */

Definition at line 127 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OTX1

#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */

Definition at line 129 of file dsp5680xx.h.

◆ DSP5680XX_ONCE_OTXRXSR

#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */

Definition at line 126 of file dsp5680xx.h.

◆ EONCE_STAT_MASK

#define EONCE_STAT_MASK 0x30

Definition at line 111 of file dsp5680xx.h.

◆ FLUSH_COUNT_FLASH

#define FLUSH_COUNT_FLASH 8192

Definition at line 144 of file dsp5680xx.h.

◆ FLUSH_COUNT_READ_WRITE

#define FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */

Definition at line 143 of file dsp5680xx.h.

◆ HFM_BASE_ADDR

#define HFM_BASE_ADDR

Value:

0x0F400

Flashing (ref:MC56F801xRM.pdf:159)

Definition at line 163 of file dsp5680xx.h.

◆ HFM_CALCULATE_DATA_SIGNATURE

#define HFM_CALCULATE_DATA_SIGNATURE 0x06

Definition at line 150 of file dsp5680xx.h.

◆ HFM_CALCULATE_IFR_BLOCK_SIGNATURE

#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66

Definition at line 154 of file dsp5680xx.h.

◆ HFM_CLK_DEFAULT

#define HFM_CLK_DEFAULT 0x27

The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM.

This value was calculated using a spreadsheet tool available on the Freescale website under FAQ 25464.

Definition at line 191 of file dsp5680xx.h.

◆ HFM_CLK_DIV

#define HFM_CLK_DIV 0x00 /* r/w */

The following are register addresses, not memory addresses (though all registers are memory mapped)

Definition at line 168 of file dsp5680xx.h.

◆ HFM_CMD

#define HFM_CMD 0x14 /* r/w */

Definition at line 175 of file dsp5680xx.h.

◆ HFM_CNFG

#define HFM_CNFG 0x01 /* r/w */

Definition at line 169 of file dsp5680xx.h.

◆ HFM_DATA

#define HFM_DATA 0x18 /* r */

Definition at line 176 of file dsp5680xx.h.

◆ HFM_ERASE_VERIFY

#define HFM_ERASE_VERIFY 0x05

HFM (flash module) Commands (ref:MC56F801xRM.pdf:159)

Definition at line 149 of file dsp5680xx.h.

◆ HFM_EXEC_COMPLETE

#define HFM_EXEC_COMPLETE 0x40

Definition at line 180 of file dsp5680xx.h.

◆ HFM_FLASH_BASE_ADDR

#define HFM_FLASH_BASE_ADDR 0x0

Definition at line 193 of file dsp5680xx.h.

◆ HFM_LOCK_ADDR_H

#define HFM_LOCK_ADDR_H 0x1FF8

Definition at line 205 of file dsp5680xx.h.

◆ HFM_LOCK_ADDR_L

#define HFM_LOCK_ADDR_L 0x1FF7

Definition at line 204 of file dsp5680xx.h.

◆ HFM_LOCK_FLASH

#define HFM_LOCK_FLASH 0xE70A

Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.

Definition at line 203 of file dsp5680xx.h.

◆ HFM_MASS_ERASE

#define HFM_MASS_ERASE 0x41

Definition at line 153 of file dsp5680xx.h.

◆ HFM_OPT1

#define HFM_OPT1 0x1B /* r */

Definition at line 177 of file dsp5680xx.h.

◆ HFM_PAGE_ERASE

#define HFM_PAGE_ERASE 0x40

Definition at line 152 of file dsp5680xx.h.

◆ HFM_PROT

#define HFM_PROT 0x10 /* r/w */

Definition at line 172 of file dsp5680xx.h.

◆ HFM_PROTB

#define HFM_PROTB 0x11 /* r/w */

Definition at line 173 of file dsp5680xx.h.

◆ HFM_SECHI

#define HFM_SECHI 0x03 /* r */

Definition at line 170 of file dsp5680xx.h.

◆ HFM_SECLO

#define HFM_SECLO 0x04 /* r */

Definition at line 171 of file dsp5680xx.h.

◆ HFM_SECTOR_COUNT

#define HFM_SECTOR_COUNT 0x20

Definition at line 197 of file dsp5680xx.h.

◆ HFM_SECTOR_SIZE

#define HFM_SECTOR_SIZE 0x200 /* Size in bytes */

Definition at line 196 of file dsp5680xx.h.

◆ HFM_SIZE_BYTES

#define HFM_SIZE_BYTES 0x4000 /* bytes */

Definition at line 194 of file dsp5680xx.h.

◆ HFM_SIZE_WORDS

#define HFM_SIZE_WORDS 0x2000 /* words */

Definition at line 195 of file dsp5680xx.h.

◆ HFM_TSTSIG

#define HFM_TSTSIG 0x1D /* r */

Definition at line 178 of file dsp5680xx.h.

◆ HFM_USTAT

#define HFM_USTAT 0x13 /* r/w */

Definition at line 174 of file dsp5680xx.h.

◆ HFM_USTAT_MASK_BLANK

#define HFM_USTAT_MASK_BLANK 0x4

Definition at line 183 of file dsp5680xx.h.

◆ HFM_USTAT_MASK_PVIOL_ACCER

#define HFM_USTAT_MASK_PVIOL_ACCER 0x30

Definition at line 184 of file dsp5680xx.h.

◆ HFM_WORD_PROGRAM

#define HFM_WORD_PROGRAM 0x20

Definition at line 151 of file dsp5680xx.h.

◆ JTAG_INSTR_BYPASS

#define JTAG_INSTR_BYPASS 0xF

Definition at line 53 of file dsp5680xx.h.

◆ JTAG_INSTR_CLAMP

#define JTAG_INSTR_CLAMP 0x5

Definition at line 50 of file dsp5680xx.h.

◆ JTAG_INSTR_DEBUG_REQUEST

#define JTAG_INSTR_DEBUG_REQUEST 0x7

Definition at line 52 of file dsp5680xx.h.

◆ JTAG_INSTR_ENABLE_ONCE

#define JTAG_INSTR_ENABLE_ONCE 0x6

Definition at line 51 of file dsp5680xx.h.

◆ JTAG_INSTR_EXTEST

#define JTAG_INSTR_EXTEST 0x0

Definition at line 45 of file dsp5680xx.h.

◆ JTAG_INSTR_EXTEST_PULLUP

#define JTAG_INSTR_EXTEST_PULLUP 0x3

Definition at line 48 of file dsp5680xx.h.

◆ JTAG_INSTR_HIGHZ

#define JTAG_INSTR_HIGHZ 0x4

Definition at line 49 of file dsp5680xx.h.

◆ JTAG_INSTR_IDCODE

#define JTAG_INSTR_IDCODE 0x2

Definition at line 47 of file dsp5680xx.h.

◆ JTAG_INSTR_SAMPLE_PRELOAD

#define JTAG_INSTR_SAMPLE_PRELOAD 0x1

Definition at line 46 of file dsp5680xx.h.

◆ JTAG_STATUS_BUSY

#define JTAG_STATUS_BUSY 0x09

Definition at line 41 of file dsp5680xx.h.

◆ JTAG_STATUS_DEAD

#define JTAG_STATUS_DEAD 0x0f

Definition at line 43 of file dsp5680xx.h.

◆ JTAG_STATUS_DEBUG

#define JTAG_STATUS_DEBUG 0x0D

Definition at line 42 of file dsp5680xx.h.

◆ JTAG_STATUS_MASK

#define JTAG_STATUS_MASK 0x0F

Definition at line 37 of file dsp5680xx.h.

◆ JTAG_STATUS_NORMAL

#define JTAG_STATUS_NORMAL 0x01

Definition at line 39 of file dsp5680xx.h.

◆ JTAG_STATUS_STOPWAIT

#define JTAG_STATUS_STOPWAIT 0x05

Definition at line 40 of file dsp5680xx.h.

◆ MASTER_TAP_CMD_BYPASS

#define MASTER_TAP_CMD_BYPASS 0xF

Master TAP instructions from MC56F8000RM.pdf

Definition at line 62 of file dsp5680xx.h.

◆ MASTER_TAP_CMD_FLASH_ERASE

#define MASTER_TAP_CMD_FLASH_ERASE 0x8

Definition at line 65 of file dsp5680xx.h.

◆ MASTER_TAP_CMD_IDCODE

#define MASTER_TAP_CMD_IDCODE 0x2

Definition at line 63 of file dsp5680xx.h.

◆ MASTER_TAP_CMD_TLM_SEL

#define MASTER_TAP_CMD_TLM_SEL 0x5

Definition at line 64 of file dsp5680xx.h.

◆ MC568013_EONCE_OBASE_ADDR

#define MC568013_EONCE_OBASE_ADDR 0xFF

Register Memory Map (eonce_rev.1.0_0208081.pdf:16)

Definition at line 214 of file dsp5680xx.h.

◆ MC568013_EONCE_OCR

#define MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */

Definition at line 218 of file dsp5680xx.h.

◆ MC568013_EONCE_TX1_RX1_HIGH_ADDR

#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */

Definition at line 217 of file dsp5680xx.h.

◆ MC568013_EONCE_TX_RX_ADDR

#define MC568013_EONCE_TX_RX_ADDR 0xFFFE

Definition at line 216 of file dsp5680xx.h.

◆ MC568013_SIM_BASE_ADDR

#define MC568013_SIM_BASE_ADDR 0xF140

SIM addresses & commands (MC56F80xx.h from freescale)

Definition at line 227 of file dsp5680xx.h.

◆ MC56803X_2X_SIM_BASE_ADDR

#define MC56803X_2X_SIM_BASE_ADDR 0xF100

Definition at line 228 of file dsp5680xx.h.

◆ S_FILE_DATA_OFFSET

#define S_FILE_DATA_OFFSET 0x200000

Definition at line 27 of file dsp5680xx.h.

◆ SIM_CMD_RESET

#define SIM_CMD_RESET 0x10

Definition at line 230 of file dsp5680xx.h.

◆ TIME_DIV_FREESCALE

#define TIME_DIV_FREESCALE 0.3

Definition at line 28 of file dsp5680xx.h.

Function Documentation

◆ dsp5680xx_f_erase()

int dsp5680xx_f_erase	(	struct target *	target,
		int	first,
		int	last
	)

Erases either a sector or the complete flash array.

If either the range first-last covers the complete array or if first == 0 and last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased.

Parameters

target
first
last

Returns

Definition at line 1862 of file dsp5680xx.c.

References dsp5680xx_common::debug_mode_enabled, dsp5680xx_context, dsp5680xx_f_sim_reset(), dsp5680xx_halt(), erase_sector(), err_check_propagate, ERROR_OK, HFM_SECTOR_COUNT, mass_erase(), and set_fm_ck_div().

Referenced by dsp5680xx_flash_erase().

◆ dsp5680xx_f_erase_check()

int dsp5680xx_f_erase_check	(	struct target *	target,
		uint8_t *	erased,
		uint32_t	sector
	)

The FM has the functionality of checking if the flash array is erased.

This function executes it. It does not support individual sector analysis.

Parameters

target
erased
sector	This parameter is ignored because the FM does not support checking if individual sectors are erased.

Returns

Definition at line 1799 of file dsp5680xx.c.

References dsp5680xx_common::debug_mode_enabled, dsp5680xx_context, dsp5680xx_f_ex(), dsp5680xx_halt(), err_check_propagate, HFM_ERASE_VERIFY, HFM_FLASH_BASE_ADDR, HFM_SECTOR_SIZE, HFM_USTAT_MASK_BLANK, and set_fm_ck_div().

◆ dsp5680xx_f_lock()

int dsp5680xx_f_lock ( struct target * target )

Writes the flash security words with a specific value.

The chip's security will be enabled after the first reset following the execution of this function.

Parameters

target

Returns

Definition at line 2196 of file dsp5680xx.c.

References dsp5680xx_common::debug_mode_enabled, dsp5680xx_context, DSP5680XX_ERROR_JTAG_RESET, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER, dsp5680xx_f_wr(), jtag_tap::enabled, err_check, err_check_propagate, ERROR_FAIL, HFM_LOCK_ADDR_L, HFM_LOCK_FLASH, jtag_add_reset(), jtag_add_sleep(), jtag_tap_by_string(), reset_jtag(), target::state, switch_tap(), TARGET_RUNNING, and TIME_DIV_FREESCALE.

Referenced by dsp5680xx_flash_protect().

◆ dsp5680xx_f_protect_check()

int dsp5680xx_f_protect_check	(	struct target *	target,
		uint16_t *	protected
	)

Reads the memory mapped protection register.

A 1 implies the sector is protected, a 0 implies the sector is not protected.

Parameters

target
protected	Data read from the protection register.

Returns

Definition at line 1572 of file dsp5680xx.c.

References check_halt_and_debug, DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS, dsp5680xx_read_16_single(), err_check, err_check_propagate, ERROR_FAIL, HFM_BASE_ADDR, and HFM_PROT.

Referenced by dsp5680xx_flash_protect_check().

◆ dsp5680xx_f_unlock()

int dsp5680xx_f_unlock ( struct target * target )

Executes a mass erase command.

The must be done from the Master tap. It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp) before running this function. The flash array will be unsecured (and erased) after the first reset following the execution of this function.

Parameters

target

Returns

Definition at line 2095 of file dsp5680xx.c.

References dsp5680xx_common::debug_mode_enabled, dsp5680xx_context, dsp5680xx_drscan(), DSP5680XX_ERROR_JTAG_RESET, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER, dsp5680xx_irscan(), DSP5680XX_JTAG_CORE_TAP_IRLEN, DSP5680XX_JTAG_MASTER_TAP_IRLEN, jtag_tap::enabled, eonce_enter_debug_mode_without_reset(), err_check, err_check_propagate, ERROR_FAIL, ERROR_OK, HFM_CLK_DEFAULT, jtag_add_reset(), jtag_add_sleep(), JTAG_INSTR_DEBUG_REQUEST, jtag_tap_by_string(), LOG_WARNING, MASTER_TAP_CMD_FLASH_ERASE, reset_jtag(), target::state, switch_tap(), TARGET_RUNNING, and TIME_DIV_FREESCALE.

Referenced by dsp5680xx_flash_protect().

◆ dsp5680xx_f_wr()

int dsp5680xx_f_wr	(	struct target *	target,
		const uint8_t *	buffer,
		uint32_t	address,
		uint32_t	count,
		int	is_flash_lock
	)

Writes to flash memory.

Does not check if flash is erased, it's up to the user to erase the flash before running this function. The flashing algorithm runs from RAM, reading from a register to which this function writes to. The algorithm is open loop, there is no control to verify that the FM read the register before writing the next data. A closed loop approach was much slower, and the current implementation does not fail, and if it did the crc check would detect it, allowing to flash again.

Parameters

target
buffer
address	Word addressing.
count	In bytes.
is_flash_lock

Returns

Definition at line 1956 of file dsp5680xx.c.

References buffer, core_load_tx_rx_high_addr_to_r0(), core_move_long_to_r2, core_move_long_to_r3, core_move_value_at_r2_disp, core_tx_upper_data(), count, dsp5680xx_common::debug_mode_enabled, dsp5680xx_context, DSP5680XX_ERROR_FLASHING_CRC, DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT, dsp5680xx_execute_queue(), dsp5680xx_f_signature(), dsp5680xx_resume(), dsp5680xx_write(), eonce_enter_debug_mode(), err_check, err_check_propagate, ERROR_FAIL, ERROR_OK, dsp5680xx_common::flush, FLUSH_COUNT_FLASH, HFM_BASE_ADDR, HFM_CNFG, HFM_PROT, HFM_PROTB, HFM_SIZE_WORDS, HFM_USTAT, NULL, perl_crc(), pgm_write_pflash, pgm_write_pflash_length, and set_fm_ck_div().

Referenced by dsp5680xx_f_lock(), and dsp5680xx_flash_write().

◆ target_to_dsp5680xx()

static struct dsp5680xx_common* target_to_dsp5680xx ( struct target * target )

inlinestatic

Definition at line 279 of file dsp5680xx.h.

Data Structures

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ DSP5680XX_ERROR_ENTER_DEBUG_MODE

◆ DSP5680XX_ERROR_EXIT_DEBUG_MODE

◆ DSP5680XX_ERROR_FLASHING

◆ DSP5680XX_ERROR_FLASHING_CRC

◆ DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT

◆ DSP5680XX_ERROR_FM_BUSY

◆ DSP5680XX_ERROR_FM_CMD_TIMED_OUT

◆ DSP5680XX_ERROR_FM_EXEC

◆ DSP5680XX_ERROR_FM_SET_CLK

◆ DSP5680XX_ERROR_HALT

◆ DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT

◆ DSP5680XX_ERROR_INVALID_IR_LEN

◆ DSP5680XX_ERROR_JTAG_COMM

◆ DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW

◆ DSP5680XX_ERROR_JTAG_DRSCAN

◆ DSP5680XX_ERROR_JTAG_INVALID_TAP

◆ DSP5680XX_ERROR_JTAG_IRSCAN

◆ DSP5680XX_ERROR_JTAG_RESET

◆ DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE

◆ DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER

◆ DSP5680XX_ERROR_JTAG_TAP_FIND_CORE

◆ DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER

◆ DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP

◆ DSP5680XX_ERROR_NOT_IN_DEBUG

◆ DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS

◆ DSP5680XX_ERROR_RESUME

◆ DSP5680XX_ERROR_TARGET_RUNNING

◆ DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD

ERROR codes - enable automatic parsing of output

◆ DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING

◆ DSP5680XX_JTAG_CORE_TAP_IRLEN

JTAG

◆ DSP5680XX_JTAG_MASTER_TAP_IRLEN

◆ DSP5680XX_ONCE_NOREG

Register Select Encoding (eonce_rev.1.0_0208081.pdf:14)

◆ DSP5680XX_ONCE_OBAR

◆ DSP5680XX_ONCE_OBAR1

◆ DSP5680XX_ONCE_OBASE

◆ DSP5680XX_ONCE_OCNTR

◆ DSP5680XX_ONCE_OCNTR_C

◆ DSP5680XX_ONCE_OCR

◆ DSP5680XX_ONCE_OCR_EX

EOnCE control register info

◆ DSP5680XX_ONCE_OCR_GO

◆ DSP5680XX_ONCE_OCR_RW

◆ DSP5680XX_ONCE_OPABDR

◆ DSP5680XX_ONCE_OPABER

◆ DSP5680XX_ONCE_OPABFR

◆ DSP5680XX_ONCE_OPDBR

◆ DSP5680XX_ONCE_OPFIFO

◆ DSP5680XX_ONCE_ORX

◆ DSP5680XX_ONCE_ORX1

◆ DSP5680XX_ONCE_OSCR_BUSY_M

◆ DSP5680XX_ONCE_OSCR_DEBUG_M

◆ DSP5680XX_ONCE_OSCR_NORMAL_M

EOnCE Core Status - Describes the operating status of the core controller

◆ DSP5680XX_ONCE_OSCR_OS0

◆ DSP5680XX_ONCE_OSCR_OS1

1 ReadFrom the Register Specified by the RS[4:0] Bits

EOnCE Status Register

◆ DSP5680XX_ONCE_OSCR_STOPWAIT_M

◆ DSP5680XX_ONCE_OSR

◆ DSP5680XX_ONCE_OTBCR

◆ DSP5680XX_ONCE_OTX

◆ DSP5680XX_ONCE_OTX1

◆ DSP5680XX_ONCE_OTXRXSR

◆ EONCE_STAT_MASK

◆ FLUSH_COUNT_FLASH

◆ FLUSH_COUNT_READ_WRITE

◆ HFM_BASE_ADDR

Flashing (ref:MC56F801xRM.pdf:159)

◆ HFM_CALCULATE_DATA_SIGNATURE

◆ HFM_CALCULATE_IFR_BLOCK_SIGNATURE

◆ HFM_CLK_DEFAULT

◆ HFM_CLK_DIV