OpenOCD
armv8_dpm.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Copyright (C) 2009 by David Brownell
5  */
6 
7 #ifndef OPENOCD_TARGET_ARMV8_DPM_H
8 #define OPENOCD_TARGET_ARMV8_DPM_H
9 
10 #include "arm_dpm.h"
11 #include "helper/bits.h"
12 
13 /* forward-declare struct armv8_common */
14 struct armv8_common;
15 
24 int armv8_dpm_setup(struct arm_dpm *dpm);
25 int armv8_dpm_initialize(struct arm_dpm *dpm);
26 
28 int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
29 
30 
31 int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
32 
33 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
34  * Not all v7 bits are valid in v6.
35  */
36 #define DSCR_DEBUG_STATUS_MASK (0x1F << 0)
37 #define DSCR_ERR (0x1 << 6)
38 #define DSCR_SYS_ERROR_PEND (0x1 << 7)
39 #define DSCR_CUR_EL (0x3 << 8)
40 #define DSCR_EL_STATUS_MASK (0xF << 10)
41 #define DSCR_HDE (0x1 << 14)
42 #define DSCR_SDD (0x1 << 16)
43 #define DSCR_NON_SECURE (0x1 << 18)
44 #define DSCR_MA (0x1 << 20)
45 #define DSCR_TDA (0x1 << 21)
46 #define DSCR_INTDIS_MASK (0x3 << 22)
47 #define DSCR_ITE (0x1 << 24)
48 #define DSCR_PIPE_ADVANCE (0x1 << 25)
49 #define DSCR_TXU (0x1 << 26)
50 #define DSCR_RTO (0x1 << 27) /* bit 28 is reserved */
51 #define DSCR_ITO (0x1 << 28)
52 #define DSCR_DTR_TX_FULL (0x1 << 29)
53 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
54 
55 
56 
57 /* Methods of entry into debug mode */
58 #define DSCRV8_ENTRY_NON_DEBUG (0x2)
59 #define DSCRV8_ENTRY_RESTARTING (0x1)
60 #define DSCRV8_ENTRY_BKPT (0x7)
61 #define DSCRV8_ENTRY_EXT_DEBUG (0x13)
62 #define DSCRV8_ENTRY_HALT_STEP_NORMAL (0x1B)
63 #define DSCRV8_ENTRY_HALT_STEP_EXECLU (0x1F)
64 #define DSCRV8_ENTRY_OS_UNLOCK (0x23)
65 #define DSCRV8_ENTRY_RESET_CATCH (0x27)
66 #define DSCRV8_ENTRY_WATCHPOINT (0x2B)
67 #define DSCRV8_ENTRY_HLT (0x2F)
68 #define DSCRV8_ENTRY_SW_ACCESS_DBG (0x33)
69 #define DSCRV8_ENTRY_EXCEPTION_CATCH (0x37)
70 #define DSCRV8_ENTRY_HALT_STEP (0x3B)
71 #define DSCRV8_HALT_MASK (0x3C)
72 
73 /*DRCR registers*/
74 #define DRCR_CSE (1 << 2)
75 #define DRCR_CSPA (1 << 3)
76 #define DRCR_CBRRQ (1 << 4)
77 
78 
79 /* DTR modes */
80 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
81 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
82 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
83 
84 
85 /* DRCR (debug run control register) bits */
86 #define DRCR_HALT (1 << 0)
87 #define DRCR_RESTART (1 << 1)
88 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
89 
90 /* ECR (Execution Control Register) bits */
91 #define ECR_RCE BIT(1)
92 
93 /* ESR (Event Status Register) bits */
94 #define ESR_RC BIT(1)
95 
96 /* PRSR (processor debug status register) bits */
97 #define PRSR_PU (1 << 0)
98 #define PRSR_SPD (1 << 1)
99 #define PRSR_RESET (1 << 2)
100 #define PRSR_SR (1 << 3)
101 #define PRSR_HALT (1 << 4)
102 #define PRSR_OSLK (1 << 5)
103 #define PRSR_DLK (1 << 6)
104 #define PRSR_EDAD (1 << 7)
105 #define PRSR_SDAD (1 << 8)
106 #define PRSR_EPMAD (1 << 9)
107 #define PRSR_SPMAD (1 << 10)
108 #define PRSR_SDR (1 << 11)
109 
110 /* PRCR (processor debug control register) bits */
111 #define PRCR_CORENPDRQ (1 << 0)
112 #define PRCR_CWRR (1 << 2)
113 #define PRCR_COREPURQ (1 << 3)
114 
115 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
116 void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore);
118 
119 #endif /* OPENOCD_TARGET_ARM_DPM_H */
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:142
This is the interface to the Debug Programmers Model for ARMv6 and ARMv7 processors.
enum arm_mode mode
Definition: armv4_5.c:277
int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: armv8_dpm.c:863
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
Get core state from EDSCR, without necessity to retrieve CPSR.
Definition: armv8_dpm.c:41
int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
Definition: armv8_dpm.c:731
int armv8_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: armv8_dpm.c:1474
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: armv8_dpm.c:539
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr)
Definition: armv8_dpm.c:1342
void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
Definition: armv8_dpm.c:1286
int armv8_dpm_setup(struct arm_dpm *dpm)
This wraps an implementation of DPM primitives.
Definition: armv8_dpm.c:1392
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
struct arm_dpm dpm
Definition: armv8.h:187