I've checked in support for ARM926EJ-S based cores. This has only been tested with a LPC3180 yet, and the cache/MMU handling isn't tested at all, but basically it should work. Accessing CP15 registers works, and can be verified with the command "arm926ejs cp15 0 0 0 0" which does a CP15 read with opcode_1, opcode_2, Rn and Rm all set to zero, reading the ID code from CP15 c0. Information about the cache can also be retrieved using the command "arm926ejs cache_info".
Lots of people have asked for ARM926EJ-S support, and several parties wanted to get me a board to work with, but unfortunately none of them were able to make that happen.
Finally, my university bought a board with a LPC3180, and I would like to thank the University Of Applied Sciences Augsburg (FHA) and Prof. Dr. Hubert Högl for their continued support for the OpenOCD.
Windows binaries of the new OpenOCD release (currently SVN revision 128) will be available shortly on Michael Fischer's Yagarto webpage.
Best Regards,
Dominic Rath