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OpenOCD has different commands for NOR and NAND flash; the “flash” command works with NOR flash, while the “nand” command works with NAND flash. This partially reflects different hardware technologies: NOR flash usually supports direct CPU instruction and data bus access, while data from a NAND flash must be copied to memory before it can be used. (SPI flash must also be copied to memory before use.) However, the documentation also uses “flash” as a generic term; for example, “Put flash configuration in board-specific files”.
Flash Steps:
flash bank
flash subcommand
Many CPUs have the ability to “boot” from the first flash bank. This means that misprogramming that bank can “brick” a system, so that it can’t boot. JTAG tools, like OpenOCD, are often then used to “de-brick” the board by (re)installing working boot firmware.
Configures a flash bank which provides persistent storage for addresses from base to base + size - 1. These banks will often be visible to GDB through the target’s memory map. In some cases, configuring a flash bank will activate extra commands; see the driver-specific documentation.
cfi for external flash, or else
the name of a microcontroller with embedded flash memory.
See Flash Driver List.
Note: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.
Prints a one-line summary of each device that was
declared using flash bank, numbered from zero.
Note that this is the plural form;
the singular form is a very different command.
Retrieves a list of associative arrays for each device that was
declared using flash bank, numbered from zero.
This returned list can be manipulated easily from within scripts.
Identify the flash, or validate the parameters of the configured flash. Operation
depends on the flash type.
The num parameter is a value shown by flash banks.
Most flash commands will implicitly autoprobe the bank;
flash drivers can distinguish between probing and autoprobing,
but most don’t bother.
The target device should be in well defined state before the flash programming begins.
Always issue reset init before Flash Programming Commands.
Do not issue another reset or reset halt or resume
until the programming session is finished.
If you use Programming using GDB, the target is prepared automatically in the event gdb-flash-erase-start
The jimtcl script program calls reset init explicitly.
One feature distinguishing NOR flash from NAND or serial flash technologies
is that for read access, it acts exactly like any other addressable memory.
This means you can use normal memory read commands like mdw or
dump_image with it, with no special flash subcommands.
See Memory access, and Image access.
Write access works differently. Flash memory normally needs to be erased before it’s written. Erasing a sector turns all of its bits to ones, and writing can turn ones into zeroes. This is why there are special commands for interactive erasing and writing, and why GDB needs to know which parts of the address space hold NOR flash memory.
Note: Most of these erase and write commands leverage the fact that NOR flash chips consume target address space. They implicitly refer to the current JTAG target, and map from an address in that target’s address space back to a flash bank. A few commands use abstract addressing based on bank and sector numbers, and don’t depend on searching the current target and its address space. Avoid confusing the two command models.
Some flash chips implement software protection against accidental writes, since such buggy writes could in some cases “brick” a system. For such systems, erasing and writing may require sector protection to be disabled first. Examples include CFI flash such as “Intel Advanced Bootblock flash”, and AT91SAM7 on-chip flash. See flash protect.
Erase sectors in bank num, starting at sector first
up to and including last.
Sector numbering starts at 0.
Providing a last sector of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
Erase sectors starting at address for length bytes. Unless pad is specified, address must begin a flash sector, and address + length - 1 must end a sector. Specifying pad erases extra data at the beginning and/or end of the specified region, as needed to erase only full sectors. The flash bank to use is inferred from the address, and the specified length must stay within that bank. As a special case, when length is zero and address is the start of the bank, the whole flash is erased. If unlock is specified, then the flash is unprotected before erase starts.
Fills flash memory with the specified double-word (64 bits), word (32 bits), halfword (16 bits), or byte (8-bit) pattern, starting at address and continuing for length units (word/halfword/byte). No erasure is done before writing; when needed, that must be done before issuing this command. Writes are done in blocks of up to 1024 bytes, and each write is verified by reading back the data and comparing it to what was written. The flash bank to use is inferred from the address of each block, and the specified length must stay within that bank.
Display contents of address addr, as
32-bit words (mdw), 16-bit halfwords (mdh),
or 8-bit bytes (mdb).
If count is specified, displays that many units.
Reads from flash using the flash driver, therefore it enables reading
from a bank not mapped in target address space.
The flash bank to use is inferred from the address of
each block, and the specified length must stay within that bank.
Write the binary filename to flash bank num,
starting at offset bytes from the beginning of the bank. If offset
is omitted, start at the beginning of the flash bank.
The num parameter is a value shown by flash banks.
Read length bytes from the flash bank num starting at offset
and write the contents to the binary filename. If offset is
omitted, start at the beginning of the flash bank. If length is omitted,
read the remaining bytes from the flash bank.
The num parameter is a value shown by flash banks.
Compare the contents of the binary file filename with the contents of the
flash bank num starting at offset. If offset is omitted,
start at the beginning of the flash bank. Fail if the contents do not match.
The num parameter is a value shown by flash banks.
Write the image filename to the current target’s flash bank(s). Only loadable sections from the image are written. A relocation offset may be specified, in which case it is added to the base address for each section in the image. The file [type] can be specified explicitly as bin (binary), ihex (Intel hex), elf (ELF file), s19 (Motorola s19). mem, or builder. The relevant flash sectors will be erased prior to programming if the erase parameter is given. If unlock is provided, then the flash banks are unlocked before erase and program. The flash bank to use is inferred from the address of each image section.
Warning: Be careful using the erase flag when the flash is holding data you want to preserve. Portions of the flash outside those described in the image’s sections might be erased with no notice.
- When a section of the image being written does not fill out all the sectors it uses, the unwritten parts of those sectors are necessarily also erased, because sectors can’t be partially erased.
- Data stored in sector "holes" between image sections are also affected. For example, "
flash write_image erase ..." of an image with one byte at the beginning of a flash bank and one byte at the end erases the entire bank – not just the two sectors being written.Also, when flash protection is important, you must re-apply it after it has been removed by the unlock flag.
Verify the image filename to the current target’s flash bank(s). Parameters follow the description of ’flash write_image’. In contrast to the ’verify_image’ command, for banks with specific verify method, that one is used instead of the usual target’s read memory methods. This is necessary for flash banks not readable by ordinary memory reads. This command gives only an overall good/bad result for each bank, not addresses of individual failed bytes as it’s intended only as quick check for successful programming.
Check erase state of sectors in flash bank num,
and display that status.
The num parameter is a value shown by flash banks.
Print info about flash bank num, a list of protection blocks and their status. Use sectors to show a list of sectors instead.
The num parameter is a value shown by flash banks.
This command will first query the hardware, it does not print cached
and possibly stale information.
Enable (on) or disable (off) protection of flash blocks
in flash bank num, starting at protection block first
and continuing up to and including last.
Providing a last block of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
The protection block is usually identical to a flash sector.
Some devices may utilize a protection block distinct from flash sector.
See flash info for a list of protection blocks.
Sets the default value used for padding any image sections, This should normally match the flash bank erased value. If not specified by this command or the flash driver then it defaults to 0xff.
This is a helper script that simplifies using OpenOCD as a standalone programmer. The only required parameter is filename, the others are optional. See Flash Programming.
As noted above, the flash bank command requires a driver name,
and allows driver-specific options and behaviors.
Some drivers also activate driver-specific commands.
This is a special driver that maps a previously defined bank to another address. All bank settings will be copied from the master physical bank.
The virtual driver defines one mandatory parameters,
So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to the flash bank defined at address 0x1fc00000. Any command executed on the virtual banks is actually performed on the physical banks.
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
flash bank vbank0 virtual 0xbfc00000 0 0 0 \
$_TARGETNAME $_FLASHNAME
flash bank vbank1 virtual 0x9fc00000 0 0 0 \
$_TARGETNAME $_FLASHNAME
The “Common Flash Interface” (CFI) is the main standard for
external NOR flash chips, each of which connects to a
specific external chip select on the CPU.
Frequently the first such chip is used to boot the system.
Your board’s reset-init handler might need to
configure additional chip selects using other commands (like: mww to
configure a bus and its timings), or
perhaps configure a GPIO pin that controls the “write protect” pin
on the flash chip.
The CFI driver can use a target-specific working area to significantly
speed up operation.
The CFI driver can accept the following optional parameters, in any order:
To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes) wide on a sixteen bit bus:
flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
To configure one bank of 32 MBytes built from two sixteen bit (two byte) wide parts wired in parallel to create a thirty-two bit (four byte) bus with doubled throughput:
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a SPI flash connected to them. To access this flash from the host, some FPGA device provides dedicated JTAG instructions, while other FPGA devices should be programmed with a special proxy bitstream that exposes the SPI flash on the device’s JTAG interface. The flash can then be accessed through JTAG.
Since signalling between JTAG and SPI is compatible, all that is required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate the flash chip select when the JTAG state machine is in SHIFT-DR.
Such a bitstream for several Xilinx FPGAs can be found in contrib/loaders/flash/fpga/xilinx_bscan_spi.py. It requires migen and a Xilinx toolchain to build.
This mechanism with a proxy bitstream can also be used for FPGAs from Intel and Efinix. FPGAs from Lattice and Cologne Chip have dedicated JTAG instructions and procedure to connect the JTAG to the SPI signals and don’t need a proxy bitstream. Support for these devices with dedicated procedure is provided by the pld drivers. For convenience the PLD drivers will provide the USERx code for FPGAs with a proxy bitstream. Currently the following PLD drivers are able to support jtagspi:
This flash bank driver requires a target on a JTAG tap and will access that
tap directly. Since no support from the target is needed, the target can be a
"testee" dummy. Since the target does not expose the flash memory
mapping, target commands that would otherwise be expected to access the flash
will not work. These include all *_image and
$target_name m* commands as well as program. Equivalent
functionality is available through the flash write_bank,
flash read_bank, and flash verify_bank commands.
According to device size, 1- to 4-byte addresses are sent. However, some flash chips additionally have to be switched to 4-byte addresses by an extra command, see below.
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
set _USER1_INSTR_CODE 0x02
flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
$_TARGETNAME $_USER1_INSTR_CODE
pld devices command.
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld
flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
$_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
Sets flash parameters: name human readable string, total_size size in bytes, page_size is write page size. read_cmd and pprg_cmd are commands for read and page program, respectively. mass_erase_cmd, sector_size and sector_erase_cmd are optional.
jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
Sends command cmd_byte and at most 20 following bytes and reads resp_num bytes afterwards. E.g. for ’Enter 4-byte address mode’
jtagspi cmd 0 0 0xB7
Some devices use 4-byte addresses for all commands except the legacy 0x03 read regardless of device size. This command controls the corresponding hack.
Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash. It is (almost) regular NOR flash with erase sectors, program pages, etc. The only difference is special registers controlling its FPGA specific behavior. They must be properly configured for successful FPGA loading using additional xcf driver command:
command accepts additional parameters:
xcf ccb 0 external parallel slave 40
All of them must be specified even if clock frequency is pointless in slave mode. If only bank id specified than command prints current CCB register value. Note: there is no need to write this register every time you erase/program data sectors because it stores in dedicated sector.
Initiates FPGA loading procedure. Useful if your board has no "configure" button.
xcf configure 0
Additional driver notes:
NXP’s LPC43xx and LPC18xx families include a proprietary SPI Flash Interface (SPIFI) peripheral that can drive and provide memory mapped access to external SPI flash devices.
The lpcspifi driver initializes this interface and provides program and erase functionality for these serial flash devices. Use of this driver requires a working area of at least 1kB to be configured on the target device; more than this will significantly reduce flash programming times.
The setup command only requires the base parameter. All other parameters are ignored, and the flash size and layout are configured by the driver.
flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
Some devices from STMicroelectronics (e.g. STR75x MCU family, SPEAr MPU family) include a proprietary “Serial Memory Interface” (SMI) controller able to drive external SPI flash devices. Depending on specific device and board configuration, up to 4 external flash devices can be connected.
SMI makes the flash content directly accessible in the CPU address
space; each external device is mapped in a memory bank.
CPU can directly read data, execute code and boot from SMI banks.
Normal OpenOCD commands like mdw can be used to display
the flash content.
The setup command only requires the base parameter in order to identify the memory bank. All other parameters are ignored. Additional information, like flash size, are detected automatically.
flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
Some devices from STMicroelectronics include a proprietary “QuadSPI Interface” (e.g. STM32F4, STM32F7, STM32L4) or “OctoSPI Interface” (e.g. STM32L4+) controller able to drive one or even two (dual mode) external SPI flash devices. The OctoSPI is a superset of QuadSPI, its presence is detected automatically. Currently only the regular command mode is supported, whereas the HyperFlash mode is not.
QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address space; in case of dual mode both devices must be of the same type and are mapped in the same memory bank (even and odd addresses interleaved). CPU can directly read data, execute code (but not boot) from QuadSPI bank.
The ’flash bank’ command only requires the base parameter and the extra parameter io_base in order to identify the memory bank. Both are fixed by hardware, see datasheet or RM. All other parameters are ignored.
The controller must be initialized after each reset and properly configured for memory-mapped read operation for the particular flash chip(s), for the full list of available register settings cf. the controller’s RM. This setup is quite board specific (that’s why booting from this memory is not possible). The flash driver infers all parameters from current controller register values when ’flash probe bank_id’ is executed.
Normal OpenOCD commands like mdw can be used to display the flash content,
but only after proper controller initialization as described above. However,
due to a silicon bug in some devices, attempting to access the very last word
should be avoided.
It is possible to use two (even different) flash chips alternatingly, if individual bank chip selects are available. For some package variants, this is not the case due to limited pin count. To switch from one to another, adjust FSEL bit accordingly and re-issue ’flash probe bank_id’. Note that the bank base address will not change, so the address spaces of both devices will overlap. In dual flash mode both chips must be identical regarding size and most other properties.
Block or sector protection internal to the flash chip is not handled by this driver at all, but can be dealt with manually by the ’cmd’ command, see below. The sector protection via ’flash protect’ command etc. is completely internal to openocd, intended only to prevent accidental erase or overwrite and it does not persist across openocd invocations.
OpenOCD contains a hardcoded list of flash devices with their properties, these are auto-detected. If a device is not included in this list, SFDP discovery is attempted. If this fails or gives inappropriate results, manual setting is required (see ’set’ command).
flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
$_TARGETNAME 0xA0001000
flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
$_TARGETNAME 0xA0001400
There are three specific commands
Clears sector protections and performs a mass erase. Works only if there is no chip specific write protection engaged.
Set flash parameters: name human readable string, total_size size in bytes, page_size is write page size. read_cmd, fread_cmd and pprg_cmd are commands for reading and page programming. fread_cmd is used in DPI and QPI modes, read_cmd in normal SPI (single line) mode. mass_erase_cmd, sector_size and sector_erase_cmd are optional.
This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs which don’t support an id command.
In dual mode parameters of both chips are set identically. The parameters refer to a single chip, so the whole bank gets twice the specified capacity etc.
If resp_num is zero, sends command cmd_byte and following data bytes. In dual mode command byte is sent to both chips but data bytes are sent alternatingly to chip 1 and 2, first to flash 1, second to flash 2, etc., i.e. the total number of bytes (including cmd_byte) must be odd.
If resp_num is not zero, cmd and at most four following data bytes are sent, in dual mode simultaneously to both chips. Then resp_num bytes are read interleaved from both chips starting with chip 1. In this case resp_num must be even.
Note the hardware dictated subtle difference of those two cases in dual-flash mode.
To check basic communication settings, issue
stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
for single flash mode or
stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
for dual flash mode. This should return the status register contents.
In 8-line mode, cmd_byte is sent twice - first time as given, second time complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status) need a dummy address, e.g.
stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
should return the status register contents.
This driver supports QSPI flash controller of Marvell’s Wireless Microcontroller platform.
The flash size is autodetected based on the table of known JEDEC IDs hardcoded in the OpenOCD sources.
flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
Members of ATH79 SoC family from Atheros include a SPI interface with 3
chip selects.
On reset a SPI flash connected to the first chip select (CS0) is made
directly read-accessible in the CPU address space (up to 16MBytes)
and is usually used to store the bootloader and operating system.
Normal OpenOCD commands like mdw can be used to display
the flash content while it is in memory-mapped mode (only the first
4MBytes are accessible without additional configuration on reset).
The setup command only requires the base parameter in order to identify the memory bank. The actual value for the base address is not otherwise used by the driver. However the mapping is passed to gdb. Thus for the memory mapped flash (chipselect CS0) the base address should be the actual memory mapped base address. For unmapped chipselects (CS1 and CS2) care should be taken to use a base address that does not overlap with real memory regions. Additional information, like flash size, are detected automatically. An optional additional parameter sets the chipselect for the bank, with the default CS0. CS1 and CS2 require additional GPIO setup before they can be used since the alternate function must be enabled on the GPIO pin CS1/CS2 is routed to on the given SoC.
flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME # When using multiple chipselects the base should be different # for each, otherwise the write_image command is not able to # distinguish the banks. flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
SiFive’s Freedom E SPI controller, used in HiFive and other boards.
flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
The ADUC702x analog microcontrollers from Analog Devices include internal flash and use ARM7TDMI cores. The aduc702x flash driver works with models ADUC7019 through ADUC7028. The setup command only requires the target argument since all devices in this family have the same memory layout.
flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
All members of the Apollo microcontroller family from Ambiq Micro include internal flash and use ARM’s Cortex-M4 core. The host connects over USB to an FTDI interface that communicates with the target using SWD.
The ambiqmicro driver reads the Chip Information Register detect the device class of the MCU. The Flash and SRAM sizes directly follow device class, and are used to set up the flash banks. If this fails, the driver will use default values set to the minimum sizes of an Apollo chip.
All Apollo chips have two flash banks of the same size. In all cases the first flash bank starts at location 0, and the second bank starts after the first.
# Flash bank 0
flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
# Flash bank 1 - same size as bank0, starts after bank 0.
flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
$_TARGETNAME
Flash is programmed using custom entry points into the bootloader. This is the only way to program the flash as no flash control registers are available to the user.
The ambiqmicro driver adds some additional commands:
Erase entire bank.
Erase device pages.
Program OTP is a one time operation to create write protected flash. The user writes sectors to SRAM starting at 0x10000010. Program OTP will write these sectors from SRAM to flash, and write protect the flash.
All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller families from Atmel include internal flash and use ARM’s Cortex-M0+ core.
Do not use for ATSAM D51 and E5x: use See atsame5.
The devices have one flash bank:
flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
Issues a complete Flash erase via the Device Service Unit (DSU). This can be used to erase a chip back to its factory state and does not require the processor to be halted.
Secures the Flash via the Set Security Bit (SSB) command. This prevents access to the Flash and can only be undone by using the chip-erase command which erases the Flash contents and turns off the security bit. Warning: at this time, openocd will not be able to communicate with a secured chip and it is therefore not possible to chip-erase it without using another tool.
at91samd set-security enable
Shows or sets the EEPROM emulation size configuration, stored in the User Row of the Flash. When setting, the EEPROM size must be specified in bytes and it must be one of the permitted sizes according to the datasheet. Settings are written immediately but only take effect on MCU reset. EEPROM emulation requires additional firmware support and the minimum EEPROM size may not be the same as the minimum that the hardware supports. Set the EEPROM size to 0 in order to disable this feature.
at91samd eeprom at91samd eeprom 1024
Shows or sets the bootloader size configuration, stored in the User Row of the Flash. This is called the BOOTPROT region. When setting, the bootloader size must be specified in bytes and it must be one of the permitted sizes according to the datasheet. Settings are written immediately but only take effect on MCU reset. Setting the bootloader size to 0 disables bootloader protection.
at91samd bootloader at91samd bootloader 16384
This command releases internal reset held by DSU and prepares reset vector catch in case of reset halt. Command is used internally in event reset-deassert-post.
Writes or reads the entire 64 bit wide NVM user row register which is located at 0x804000. This register includes various fuses lock-bits and factory calibration data. Reading the register is done by invoking this command without any arguments. Writing is possible by giving 1 or 2 hex values. The first argument is the register value to be written and the second one is an optional changemask. Every bit which value in changemask is 0 will stay unchanged. The lock- and reserved-bits are masked out and cannot be changed.
# Read user row >at91samd nvmuserrow NVMUSERROW: 0xFFFFFC5DD8E0C788 # Write 0xFFFFFC5DD8E0C788 to user row >at91samd nvmuserrow 0xFFFFFC5DD8E0C788 # Write 0x12300 to user row but leave other bits and low # byte unchanged >at91samd nvmuserrow 0x12345 0xFFF00
All members of the AT91SAM3 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M3 core. The driver currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note that the driver was orginaly developed and tested using the AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in the family was cribbed from the data sheet. Note to future readers/updaters: Please remove this worrisome comment after other chips are confirmed.
The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips have one flash bank. In all cases the flash banks are at the following fixed locations:
# Flash bank 0 - all chips flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME # Flash bank 1 - only 256K chips flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
Internally, the AT91SAM3 flash memory is organized as follows.
Unlike the AT91SAM7 chips, these are not used as parameters
to the flash bank command:
The AT91SAM3 driver adds some additional commands:
With no parameters, show or show all,
shows the status of all GPNVM bits.
With show number, displays that bit.
With set number or clear number,
modifies that GPNVM bit.
This command attempts to display information about the AT91SAM3
chip. First it read the CHIPID_CIDR [address 0x400e0740, see
Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
document id: doc6430A] and decodes the values. Second it reads the
various clock configuration registers and attempts to display how it
believes the chip is configured. By default, the SLOWCLK is assumed to
be 32768 Hz, see the command at91sam3 slowclk.
This command shows/sets the slow clock frequency used in the
at91sam3 info command calculations above.
All members of the AT91SAM4 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M4 core. This driver uses the same command names/syntax as See at91sam3.
All members of the AT91SAM4L microcontroller family from Atmel include internal flash and use ARM’s Cortex-M4 core. This driver uses the same command names/syntax as See at91sam3.
The AT91SAM4L driver adds some additional commands:
This command releases internal reset held by SMAP and prepares reset vector catch in case of reset halt. Command is used internally in event reset-deassert-post.
All members of the SAM E54, E53, E51 and D51 microcontroller families from Microchip (former Atmel) include internal flash and use ARM’s Cortex-M4 core.
The devices have two ECC flash banks with a swapping feature. This driver handles both banks together as it were one. Bank swapping is not supported yet.
flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
Shows or sets the bootloader size configuration, stored in the User Page of the Flash. This is called the BOOTPROT region. When setting, the bootloader size must be specified in bytes. The nearest bigger protection size is used. Settings are written immediately but only take effect on MCU reset. Setting the bootloader size to 0 disables bootloader protection.
atsame5 bootloader atsame5 bootloader 16384
Issues a complete Flash erase via the Device Service Unit (DSU). This can be used to erase a chip back to its factory state and does not require the processor to be halted.
This command releases internal reset held by DSU and prepares reset vector catch in case of reset halt. Command is used internally in event reset-deassert-post.
Writes or reads the first 64 bits of NVM User Page which is located at 0x804000. This field includes various fuses. Reading is done by invoking this command without any arguments. Writing is possible by giving 1 or 2 hex values. The first argument is the value to be written and the second one is an optional bit mask (a zero bit in the mask means the bit stays unchanged). The reserved fields are always masked out and cannot be changed.
# Read >atsame5 userpage USER PAGE: 0xAEECFF80FE9A9239 # Write >atsame5 userpage 0xAEECFF80FE9A9239 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other # bits unchanged (setup SmartEEPROM of virtual size 8192 # bytes) >atsame5 userpage 0x4200000000 0x7f00000000
All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from Atmel include internal flash and use ARM’s Cortex-M7 core. This driver uses the same command names/syntax as See at91sam3.
flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
With no parameters, show or show all, shows the status of all GPNVM bits. With show number, displays that bit.
With set number or clear number, modifies that GPNVM bit.
All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
For chips which are not recognized by the controller driver, you must provide additional parameters in the following order:
flash info
It is recommended that you provide zeroes for all of those values except the clock frequency, so that everything except that frequency will be autoconfigured. Knowing the frequency helps ensure correct timings for flash access.
The flash controller handles erases automatically on a page (128/256 byte)
basis, so explicit erase commands are not necessary for flash programming.
However, there is an “EraseAll“ command that can erase an entire flash
plane (of up to 256KB), and it will be used automatically when you issue
flash erase_sector or flash erase_address commands.
Set or clear a “General Purpose Non-Volatile Memory” (GPNVM) bit for the processor. Each processor has a number of such bits, used for controlling features such as brownout detection (so they are not truly general purpose).
Note: This assumes that the first flash bank (number 0) is associated with the appropriate at91sam7 target.
The AVR 8-bit microcontrollers from Atmel integrate flash memory. The current implementation is incomplete.
STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory. The driver automatically recognizes these chips using the chip identification registers, and autoconfigures itself.
flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing each single sector one by one.
flash erase_sector 0 0 last # It will perform a mass erase
Triggering a mass erase is also useful when users want to disable readout protection.
All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas Instruments include internal flash. The cc26xx flash driver supports both the CC13xx and CC26xx family of devices. The driver automatically recognizes the specific version’s flash parameters and autoconfigures itself. The flash bank starts at address 0.
flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas Instruments includes 1MB of internal flash. The cc3220sf flash driver only supports the internal flash. The serial flash on SimpleLink boards is programmed via the bootloader over a UART connection. Security features of the CC3220SF may erase the internal flash during power on reset. Refer to documentation at www.ti.com/cc3220sf for details on security features and programming the serial flash.
flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs) include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
It supports writing to the user data page, as well as the portion of the lockbits page past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs bootloader/AppLoader system for encryption keys. Setting protection on these pages is currently not supported.
flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
A special feature of efm32 controllers is that it is possible to completely disable the debug interface by writing the correct values to the ’Debug Lock Word’. OpenOCD supports this via the following command:
efm32 debuglock num
The num parameter is a value shown by flash banks.
Note that in order for this command to take effect, the target needs to be reset.
The current implementation is incomplete. Unprotecting flash pages is not
supported.
All versions of the KB1200 microcontrollers from ENE include internal flash. The eneispif flash driver supports the KB1200 family of devices. The driver automatically recognizes the specific version’s flash parameters and autoconfigures itself. The flash bank starts at address 0x60000000. An optional additional parameter sets the address of eneispif controller, with the default address is 0x50101000.
flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME \
0x50101000
# Address defaults to 0x50101000
flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME
Members of the eSi-RISC family may optionally include internal flash programmed via the eSi-TSMC Flash interface. Additional parameters are required to configure the driver: cfg_address is the base address of the configuration register interface, clock_hz is the expected clock frequency, and wait_states is the number of configured read wait states.
flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
$_TARGETNAME cfg_address clock_hz wait_states
Erase all pages in data memory for the bank identified by bank_id.
Erase the reference cell for the bank identified by bank_id. This is an uncommon operation.
All members of the FM3 microcontroller family from Fujitsu
include internal flash and use ARM Cortex-M3 cores.
The fm3 driver uses the target parameter to select the
correct bank config, it can currently be one of the following:
mb9bfxx1.cpu, mb9bfxx2.cpu, mb9bfxx3.cpu,
mb9bfxx4.cpu, mb9bfxx5.cpu or mb9bfxx6.cpu.
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
include internal flash and use ARM Cortex-M4 cores.
The fm4 driver uses a family parameter to select the
correct bank config, it can currently be one of the following:
MB9BFx64, MB9BFx65, MB9BFx66, MB9BFx67, MB9BFx68,
S6E2Cx8, S6E2Cx9, S6E2CxA or S6E2Dx,
with x treated as wildcard and otherwise case (and any trailing
characters) ignored.
flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 \
$_TARGETNAME S6E2CCAJ0A
flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 \
$_TARGETNAME S6E2CCAJ0A
The current implementation is incomplete. Protection is not supported, nor is Chip Erase (only Sector Erase is implemented).
Several microcontrollers from NXP (former Freescale), including Kx, KLx, KVx and KE1x members of the Kinetis family, and S32K11x/S32K14x microcontrollers, include internal flash and use ARM Cortex-M0+ or M4 cores. Kinetis and S32K1 families use incompatible identification registers, so the driver assumes Kinetis and requires a driver option to indicate S32K1 is to be used. Within the familiy, the driver automatically recognizes flash size and a number of flash banks (1-4) using the chip identification register, and autoconfigures itself. Use kinetis_ke driver for KE0x and KEAx devices.
The kinetis driver defines option:
flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
Configuration command enables automatic creation of additional flash banks based on real flash layout of device. Banks are created during device probe. Use ’flash probe 0’ to force probe.
Select what source is used when writing to a Flash Configuration Field. protection mode builds FCF content from protection bits previously set by ’flash protect’ command. This mode is default. MCU is protected from unwanted locking by immediate writing FCF after erase of relevant sector. write mode enables direct write to FCF. Protection cannot be set by ’flash protect’ command. FCF is written along with the rest of a flash image. BEWARE: Incorrect flash configuration may permanently lock the device!
Set value to write to FOPT byte of Flash Configuration Field. Used in kinetis ’fcf_source protection’ mode only.
Checks status of device security lock. Used internally in examine-end and examine-fail event.
Issues a halt via the MDM-AP. This command can be used to break a watchdog reset loop when connecting to an unsecured target.
Issues a complete flash erase via the MDM-AP. This can be used to erase a chip back to its factory state, removing security. It does not require the processor to be halted, however the target will remain in a halted state after this command completes.
For FlexNVM devices only (KxxDX and KxxFX). Not supported (yet) on S32K1 devices. Command shows or sets data flash or EEPROM backup size in kilobytes, sets two EEPROM blocks sizes in bytes and enables/disables loading of EEPROM contents to FlexRAM during reset.
For details see device reference manual, Flash Memory Module, Program Partition command.
Setting is possible only once after mass_erase. Reset the device after partition setting.
Show partition size:
kinetis nvm_partition info
Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
kinetis nvm_partition dataflash 32 512 1536 on
Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks of 1024 bytes and its contents is not loaded to FlexRAM during reset:
kinetis nvm_partition eebkp 16 1024 1024 off
Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the RESET pin, which can be used to reset other hardware on board.
For Kx devices only (KLx has different COP watchdog, it is not supported). Command disables watchdog timer.
KE0x and KEAx members of the Kinetis microcontroller family from NXP include internal flash and use ARM Cortex-M0+. The driver automatically recognizes the KE0x sub-family using the chip identification register, and autoconfigures itself. Use kinetis (not kinetis_ke) driver for KE1x devices.
flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
Checks status of device security lock. Used internally in examine-end event.
Issues a complete Flash erase via the MDM-AP. This can be used to erase a chip back to its factory state. Command removes security lock from a device (use of SRST highly recommended). It does not require the processor to be halted.
Command disables watchdog timer.
This is the driver to support internal flash of all members of the LPC11(x)00 and LPC1300 microcontroller families and most members of the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100, LPC8Nxx and NHS31xx microcontroller families from NXP.
Note: There are LPC2000 devices which are not supported by the lpc2000 driver: The LPC2888 is supported by the lpc288x driver. The LPC29xx family is supported by the lpc2900 driver.
The lpc2000 driver defines two mandatory and two optional parameters, which must appear in the following order:
Note: If you don’t provide calc_checksum when you’re writing the vector table, the boot ROM will almost certainly ignore your flash image. However, if you do provide it, with most tool chains
verify_imagewill fail.
LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
lpc2000_v2 14765 calc_checksum
Displays the four byte part identifier associated with the specified flash bank.
The LPC2888 microcontroller from NXP needs slightly different flash support from its lpc2000 siblings. The lpc288x driver defines one mandatory parameter, the programming clock rate in Hz. LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
This driver supports the LPC29xx ARM968E based microcontroller family from NXP.
The predefined parameters base, size, chip_width and
bus_width of the flash bank command are ignored. Flash size and
sector layout are auto-configured by the driver.
The driver has one additional mandatory parameter: The CPU clock rate
(in kHz) at the time the flash operations will take place. Most of the time this
will not be the crystal frequency, but a higher PLL frequency. The
reset-init event handler in the board script is usually the place where
you start the PLL.
The driver rejects flashless devices (currently the LPC2930).
The EEPROM in LPC2900 devices is not mapped directly into the address space.
It must be handled much more like NAND flash memory, and will therefore be
handled by a separate lpc2900_eeprom driver (not yet available).
Sector protection in terms of the LPC2900 is handled transparently. Every time a
sector needs to be erased or programmed, it is automatically unprotected.
What is shown as protection status in the flash info command, is
actually the LPC2900 sector security. This is a mechanism to prevent a
sector from ever being erased or programmed again. As this is an irreversible
mechanism, it is handled by a special command (lpc2900 secure_sector),
and not by the standard flash protect command.
Example for a 125 MHz clock frequency:
flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
Some lpc2900-specific commands are defined. In the following command list,
the bank parameter is the bank number as obtained by the
flash banks command.
Calculates a 128-bit hash value, the signature, from the whole flash content. This is a hardware feature of the flash block, hence the calculation is very fast. You may use this to verify the content of a programmed device against a known signature. Example:
lpc2900 signature 0 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
Reads the 912 bytes of customer information from the flash index sector, and saves it to a file in binary format. Example:
lpc2900 read_custom 0 /path_to/customer_info.bin
The index sector of the flash is a write-only sector. It cannot be
erased! In order to guard against unintentional write access, all following
commands need to be preceded by a successful call to the password
command:
You need to use this command right before each of the following commands:
lpc2900 write_custom, lpc2900 secure_sector,
lpc2900 secure_jtag.
The password string is fixed to "I_know_what_I_am_doing". Example:
lpc2900 password 0 I_know_what_I_am_doing Potentially dangerous operation allowed in next command!
Writes the content of the file into the customer info space of the flash index sector. The filetype can be specified with the type field. Possible values for type are: bin (binary), ihex (Intel hex format), elf (ELF binary) or s19 (Motorola S-records). The file must contain a single section, and the contained data length must be exactly 912 bytes.
Attention: This cannot be reverted! Be careful!
Example:
lpc2900 write_custom 0 /path_to/customer_info.bin bin
Secures the sector range from first to last (including) against further program and erase operations. The sector security will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Secured sectors appear as protected in the flash info command.
Example:
lpc2900 secure_sector 0 1 1
flash info 0
#0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
# 0: 0x00000000 (0x2000 8kB) not protected
# 1: 0x00002000 (0x2000 8kB) protected
# 2: 0x00004000 (0x2000 8kB) not protected
Irreversibly disable the JTAG port. The new JTAG security setting will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Examples:
lpc2900 secure_jtag 0
This drivers handles the integrated NOR flash on Milandr Cortex-M based controllers. A known limitation is that the Info memory can’t be read or verified as it’s not memory mapped.
flash bank <name> mdr <base> <size> \
0 0 <target#> type page_count sec_count
Example usage:
if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 \
0 0 $_TARGETNAME 1 1 4
} else {
flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
0 0 $_TARGETNAME 0 32 4
}
All versions of the SimpleLink MSP432 microcontrollers from Texas Instruments include internal flash. The msp432 flash driver automatically recognizes the specific version’s flash parameters and autoconfigures itself. Main program flash starts at address 0. The information flash region on MSP432P4 versions starts at address 0x200000.
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
Performs a complete erase of flash. By default, mass_erase will erase
only the main program flash.
On MSP432P4 versions, using mass_erase all will erase both the
main program and information flash regions. To also erase the BSL in information
flash, the user must first use the bsl command.
On MSP432P4 versions, bsl unlocks and locks the bootstrap loader (BSL)
region in information flash so that flash commands can erase or write the BSL.
Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
To erase and program the BSL:
msp432 bsl unlock flash erase_address 0x202000 0x2000 flash write_image bsl.bin 0x202000 msp432 bsl lock
This drivers handles the integrated NOR flash on NIIET Cortex-M4 based controllers. Flash size and sector layout are auto-configured by the driver. Main flash memory is called "Bootflash" and has main region and info region. Info region is NOT memory mapped by default, but it can replace first part of main region if needed. Full erase, single and block writes are supported for both main and info regions. There is additional not memory mapped flash called "Userflash", which also have division into regions: main and info. Purpose of userflash - to store system and user settings. Driver has special commands to perform operations with this memory.
flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
Some niietcm4-specific commands are defined:
Read byte from main or info userflash region.
Write byte to main or info userflash region.
Erase all userflash including info region.
Erase sectors of main or info userflash region, starting at sector first up to and including last.
Check sectors protect.
Protect sectors of main or info userflash region, starting at sector first up to and including last.
Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
Configure external memory interface for boot.
Perform emergency erase of all flash (bootflash and userflash).
Show information about flash driver.
All versions of the NPCX microcontroller families from Nuvoton include internal flash. The NPCX flash driver supports the NPCX family of devices. The driver automatically recognizes the specific version’s flash parameters and autoconfigures itself. The flash bank starts at address 0x64000000. An optional additional parameter sets the FIU version for the bank, with the default FIU is npcx.fiu.
flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu # FIU defaults to npcx.fiu flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
Supports all members of the nRF51, nRF52 and nRF53 microcontroller families from Nordic Semiconductor. nRF91 family is supported too. One driver handles both the main flash and the UICR area.
Flash protection is handled on nRF51 family and nRF52805, nRF52810, nRF52811, nRF52832 devices. Flash access control list (ACL) protection scheme of the newer devices is not supported.
flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
Some nrf5-specific commands are defined:
Erases the contents of the code memory and user information configuration registers as well. It must be noted that this command works only for chips that do not have factory pre-programmed region 0 code.
This driver is an implementation of the “on chip flash loader” protocol proposed by Pavel Chromy.
It is a minimalistic command-response protocol intended to be used over a DCC when communicating with an internal or external flash loader running from RAM. An example implementation for AT91SAM7x is available in contrib/loaders/flash/at91sam7x/.
flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
The PIC32MX microcontrollers are based on the MIPS 4K cores, and integrate flash memory.
flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
Some pic32mx-specific commands are defined:
Programs the specified 32-bit value at the given address in the specified chip bank.
Unlock and erase specified chip bank. This will remove any Code Protection.
All members of the PSoC 41xx/42xx microcontroller family from Cypress include internal flash and use ARM Cortex-M0 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note: Erased internal flash reads as 00. System ROM of PSoC 4 does not implement erase of a flash sector.
flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
psoc4-specific commands
Enables or disables autoerase mode for a flash bank.
If flash_autoerase is off, use mass_erase before flash programming. Flash erase command fails if region to erase is not whole flash memory.
If flash_autoerase is on, a sector is both erased and programmed in one system ROM call. Flash erase command is ignored. This mode is suitable for gdb load.
The num parameter is a value shown by flash banks.
Erases the contents of the flash memory, protection and security lock.
The num parameter is a value shown by flash banks.
All members of the PSoC 5LP microcontroller family from Cypress include internal program flash and use ARM Cortex-M3 cores. The driver probes for a number of these chips and autoconfigures itself, apart from the base address.
flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
Note: PSoC 5LP chips can be configured to have ECC enabled or disabled.
Attention: If flash operations are performed in ECC-disabled mode, they will also affect the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will then also erase the corresponding 2k data bytes in the 0x48000000 area. Writing to the ECC data bytes in ECC-disabled mode is not implemented.
Commands defined in the psoc5lp driver:
Erases all flash data and ECC/configuration bytes, all flash protection rows, and all row latches in all flash arrays on the device.
All members of the PSoC 5LP microcontroller family from Cypress include internal EEPROM and use ARM Cortex-M3 cores. The driver probes for a number of these chips and autoconfigures itself, apart from the base address.
flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
$_TARGETNAME
All members of the PSoC 5LP microcontroller family from Cypress include internal Nonvolatile Latches and use ARM Cortex-M3 cores. The driver probes for a number of these chips and autoconfigures itself.
flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
PSoC 5LP chips have multiple NV Latches:
Note: This driver only implements the Device Configuration NVL.
The psoc5lp driver reads the ECC mode from Device Configuration NVL.
Attention: Switching ECC mode via write to Device Configuration NVL will require a reset after successful write.
Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers. PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share the same Flash/RAM/MMIO address space.
Flash in PSoC6 is split into three regions:
All three flash regions are supported by the driver. Flash geometry is detected automatically by parsing data in SPCIF_GEOMETRY register.
PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
${TARGET}.cm0
flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
${TARGET}.cm0
flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
${TARGET}.cm0
flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
${TARGET}.cm0
flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
${TARGET}.cm0
flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
${TARGET}.cm0
flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
${TARGET}.cm4
flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
${TARGET}.cm4
flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
${TARGET}.cm4
flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
${TARGET}.cm4
flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
${TARGET}.cm4
flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
${TARGET}.cm4
psoc6-specific commands
Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts. When invoked for CM0+ target, it will set break point at application entry point and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used instead of SYSRESETREQ to avoid unwanted reset of CM0+;
Erases the contents given flash bank. The num parameter is a value shown
by flash banks.
Note: only Main and Work flash regions support Erase operation.
The NXP QN908x microcontrollers feature a Cortex-M4F with integrated Bluetooth LE 5 support and an internal flash of up to 512 KiB. These chips only support the SWD interface.
The qn908x driver uses the internal "Flash Memory Controller" block via SWD to erase, program and read the internal flash. This driver does not support the ISP (In-System Programming) mode which is an alternate way to program the flash via UART, SPI or USB.
The internal flash is 512 KiB in size in all released chips and it starts at the address 0x01000000, although it can be mapped to address 0 and it is aliased to other addresses. This driver only recognizes the bank starting at address 0x01000000.
The internal bootloader stored in ROM is in charge of loading and verifying
the image from flash, or enter ISP mode. The programmed image must start at
the beginning of the flash and contain a valid header and a matching CRC32
checksum. Additionally, the image header contains a "Code Read Protection"
(CRP) word which indicates whether SWD access is enabled, as well as whether
ISP mode is enabled. Therefore, it is possible to program an image that
disables SWD and ISP making it impossible to program another image in the
future through these interfaces, or even debug the current image. While this is
a valid use case for production deployments where the chips are locked down, by
default this driver doesn’t allow such images that disable the SWD interface.
To program such images see the qn908x allow_brick command.
Apart from the CRP field which is located in the image header, the last page
of the flash memory contains a "Flash lock and protect" descriptor which allows
to individually protect each 2 KiB page, as well as disabling SWD access to the
flash and RAM. If this access is disabled it is not possible to read, erase or
program individual pages from the SWD interface or even access the read-only
"Flash information page" with information about the bootloader version and
flash size. However when this protection is in place, it is still possible to
mass erase the whole chip and then program a new image, for which you can use
the qn908x mass_erase.
Example:
flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
Parameters:
Note: If the checksum in the header of your image is invalid and you don’t provide the calc_checksum option the boot ROM will not boot your image and it may render the flash inaccessible. On the other hand, if you use this option to compute the checksum keep in mind that
verify_imagewill fail on those four bytes of the checksum since those bytes in the flash will have the updated checksum.
Allow the qn908x driver to program images with a "Code Read Protection" byte
that disables the SWD access. Programming such image will cause OpenOCD to
not be able to reach the target over SWD anymore after the new image is
programmed and its configuration takes effect, e.g. after a reboot. After
executing qn908x allow_brick these images will be allowed to be
programmed when writing to the flash.
Disable the watchdog timer (WDT) by resetting its CTRL field. The WDT starts
enabled after a reset halt and it doesn’t run while the target is
halted. However, the verification process in this driver uses the generic
Cortex-M verification process which executes a payload in RAM and thus
requires the watchdog to be disabled before running verify_image
after a reset halt or any other condition where the watchdog is running.
Note that this is not done automatically and you must run this command in
those scenarios.
Erases the complete flash using the mass_erase method. Mass erase is only allowed if enabled in the Lock Status Register 8 (LOCK_STAT_8) which is read from the last sector of the flash on boot. However, this mass_erase lock protection can be bypassed and this command does so automatically.
In the same LOCK_STAT_8 the flash and RAM access from SWD can be disabled by setting two bits in this register. After a mass_erase, all the bits of the flash would be set, making it the default to restrict SWD access to the flash and RAM regions. This new after erase LOCK_STAT_8 value only takes effect after being read from flash on the next reboot for example. After a mass_erase the LOCK_STAT_8 register is changed by the hardware to allow access to flash and RAM regardless of the value on flash, but only right after a mass_erase and until the next boot. Therefore it is possible to perform a mass_erase, program a new image, verify it and then reboot to a valid image that’s locked from the SWD access.
The qn908x mass_erase command clears the bits that would be loaded
from the flash into LOCK_STAT_8 after erasing the whole chip to allow SWD
access for debugging or re-flashing an image without a mass_erase by default.
If the image being programmed also programs the last page of the flash with its
own settings, this mass_erase behavior will interfere with that write since a
new erase of at least the last page would need to be performed before writing
to it again. For this reason the optional keep_lock argument can be
used to leave the flash and RAM lock set. For development environments, the
default behavior is desired.
The mass erase locking mechanism is independent from the individual page locking bits, so it is possible that you can’t erase a given page that is locked and you can’t unprotect that page because the locking bits are also locked, but can still mass erase the whole flash.
Supports RP2040 "Raspberry Pi Pico" microcontroller. RP2040 is a dual-core device with two CM0+ cores. Both cores share the same Flash/RAM/MMIO address space. Non-volatile storage is achieved with an external QSPI flash; a Boot ROM provides helper functions.
flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
Supports Onsemi RSL10 microcontroller flash memory. Uses functions stored in ROM to control flash memory interface.
flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME
Writes key1 key2 key3 key4 words to 0x81044 0x81048 0x8104c 0x8050. Locks debug port by writing 0x4C6F634B to 0x81040.
To unlock use the rsl10 unlock key1 key2 key3 key4 command.
Unlocks debug port, by writing key1 key2 key3 key4 words to registers through DAP, and clears 0x81040 address in flash to 0x1.
Erases all unprotected flash sectors.
All members of the SiM3 microcontroller family from Silicon Laboratories include internal flash and use ARM Cortex-M3 cores. It supports both JTAG and SWD interface. The sim3x driver tries to probe the device to auto detect the MCU. If this fails, it will use the size parameter as the size of flash bank.
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
There are 2 commands defined in the sim3x driver:
Erases the complete flash. This is used to unlock the flash. And this command is only possible when using the SWD interface.
Lock the flash. To unlock use the sim3x mass_erase command.
All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller families from Texas Instruments include internal flash. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
Performs the Recovering a "Locked" Device procedure to restore the flash and its associated nonvolatile registers to their factory default values (erased). This is the only way to remove flash protection or re-enable debugging if that capability has been disabled.
Note that the final "power cycle the chip" step in this procedure must be performed by hand, since OpenOCD can’t do it.
Warning: if more than one Stellaris chip is connected, the procedure is applied to all of them.
This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics. The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice. The driver also supports the APM32F0 and APM32F1 series from Geehy Semiconductor. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
If you have a target with dual flash banks then define the second bank as per the following example.
flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
Some stm32f1x-specific commands are defined:
Locks the entire stm32 device against reading.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device for reading. This command will cause
a mass erase of the entire stm32 device if previously locked.
The num parameter is a value shown by flash banks.
Mass erases the entire stm32 device.
The num parameter is a value shown by flash banks.
Reads and displays active stm32 option bytes loaded during POR
or upon executing the stm32f1x options_load command.
The num parameter is a value shown by flash banks.
Writes the stm32 option byte with the specified values.
The num parameter is a value shown by flash banks.
The user_data parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
Generates a special kind of reset to re-load the stm32 option bytes written
by the stm32f1x options_write or flash protect commands
without having to power cycle the target. Not applicable to stm32f1x devices.
The num parameter is a value shown by flash banks.
All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M3/M4/M7 cores. The driver also works for the APM32F4 series from Geehy Semiconductor. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
If you use OTP (One-Time Programmable) memory define it as a second bank as per the following example.
flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
Enables or disables OTP write commands for bank num.
The num parameter is a value shown by flash banks.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
Some stm32f2x-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Mass erases the entire stm32f2x device.
The num parameter is a value shown by flash banks.
Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
The num parameter is a value shown by flash banks.
Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
Warning: The meaning of the various bits depends on the device, always check datasheet!
The num parameter is a value shown by flash banks, user_options a
12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, boot_addr0 and
boot_addr1 two halfwords (of FLASH_OPTCR1).
Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
The num parameter is a value shown by flash banks, optcr2 a 32-bit word.
All members of the STM32H7 microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M7 core. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
Some stm32h7x-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Mass erases the entire stm32h7x device.
The num parameter is a value shown by flash banks.
Reads an option byte register from the stm32h7x device.
The num parameter is a value shown by flash banks, reg_offset
is the register offset of the option byte to read from the used bank registers’ base.
For example: in STM32H74x/H75x the bank 1 registers’ base is 0x52002000 and 0x52002100 for bank 2.
Example usage:
# read OPTSR_CUR stm32h7x option_read 0 0x1c # read WPSN_CUR1R stm32h7x option_read 0 0x38 # read WPSN_CUR2R stm32h7x option_read 1 0x38
Writes an option byte register of the stm32h7x device.
The num parameter is a value shown by flash banks, reg_offset
is the register offset of the option byte to write from the used bank register base,
and reg_mask is the mask to apply when writing the register (only bits with a ’1’
will be touched).
Example usage:
# swap bank 1 and bank 2 in dual bank devices # by setting SWAP_BANK_OPT bit in OPTSR_PRG stm32h7x option_write 0 0x20 0x8000000 0x8000000
All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver. If you use 0 as the bank base address, it tells the driver to autodetect the bank location assuming you’re configuring the second bank.
flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
Some stm32lx-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Mass erases the entire stm32lx device (all flash banks and EEPROM
data). This is the only way to unlock a protected flash (unless RDP
Level is 2 which can’t be unlocked at all).
The num parameter is a value shown by flash banks.
All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M0+, M4 and M33 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
If you use OTP (One-Time Programmable) memory define it as a second bank as per the following example.
flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
Enables or disables OTP write commands for bank num.
The num parameter is a value shown by flash banks.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver. However, specifying a wrong value might lead to a completely wrong flash layout, so this feature must be used carefully.
flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
Some stm32l4x-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Note: To apply the protection change immediately, use stm32l4x option_load.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Note: To apply the protection change immediately, use stm32l4x option_load.
Mass erases the entire stm32l4x device.
The num parameter is a value shown by flash banks.
Reads an option byte register from the stm32l4x device.
The num parameter is a value shown by flash banks, reg_offset
is the register offset of the Option byte to read.
For example to read the FLASH_OPTR register:
stm32l4x option_read 0 0x20 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa # Option Register (for STM32WBx): <0x58004020> = ... # The correct flash base address will be used automatically
The above example will read out the FLASH_OPTR register which contains the RDP option byte, Watchdog configuration, BOR level etc.
Write an option byte register of the stm32l4x device.
The num parameter is a value shown by flash banks, reg_offset
is the register offset of the Option byte to write, and reg_mask is the mask
to apply when writing the register (only bits with a ’1’ will be touched).
Note: To apply the option bytes change immediately, use stm32l4x option_load.
For example to write the WRP1AR option bytes:
stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
The above example will write the WRP1AR option register configuring the Write protection Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0. This will effectively write protect all sectors in flash bank 1.
List the protected areas using WRP.
The num parameter is a value shown by flash banks.
device_bank parameter is optional, possible values ’bank1’ or ’bank2’,
if not specified, the command will display the whole flash protected areas.
Note: device_bank is different from banks created using flash bank.
Devices supported in this flash driver, can have main flash memory organized
in single or dual-banks mode.
Thus the usage of device_bank is meaningful only in dual-bank mode, to get
write protected areas in a specific device_bank
Forces a re-load of the option byte registers. Will cause a system reset of the device.
The num parameter is a value shown by flash banks.
Enables or disables Global TrustZone Security, using the TZEN option bit. If neither enabled nor disable are specified, the command will display the TrustZone status. Note: This command works only with devices with TrustZone, eg. STM32L5. Note: This command will perform an OBL_Launch after modifying the TZEN.
All members of the STR7 microcontroller family from STMicroelectronics
include internal flash and use ARM7TDMI cores.
The str7x driver defines one mandatory parameter, variant,
which is either STR71x, STR73x or STR75x.
flash bank $_FLASHNAME str7x \
0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
Activate the Debug/Readout protection mechanism for the specified flash bank.
Most members of the STR9 microcontroller family from STMicroelectronics
include internal flash and use ARM966E cores.
The str9 needs the flash controller to be configured using
the str9x flash_config command prior to Flash programming.
flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME str9x flash_config 0 4 2 0 0x80000
Configures the str9 flash controller.
The num parameter is a value shown by flash banks.
Only use this driver for locking/unlocking the device or configuring the option bytes.
Use the standard str9 driver for programming.
Before using the flash commands the turbo mode must be enabled using the
str9xpec enable_turbo command.
Here is some background info to help you better understand how this driver works. OpenOCD has two flash drivers for the str9:
Before we run any commands using the str9xpec driver we must first disable the str9 core. This example assumes the str9xpec driver has been configured for flash bank 0.
# assert srst, we do not want core running # while accessing str9xpec flash driver adapter assert srst # turn off target polling poll off # disable str9 core str9xpec enable_turbo 0 # read option bytes str9xpec options_read 0 # re-enable str9 core str9xpec disable_turbo 0 poll on reset halt
The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the str9xpec driver as mentioned above, just issue the commands above manually or from a telnet prompt.
Several str9xpec-specific commands are defined:
Restore the str9 into JTAG chain.
Enable turbo mode, will simply remove the str9 from the chain and talk directly to the embedded flash controller.
Lock str9 device. The str9 will only respond to an unlock command that will erase the device.
Prints the part identifier for bank num.
Configure str9 boot bank.
Configure str9 lvd source.
Configure str9 lvd threshold.
Configure str9 lvd reset warning source.
Read str9 option bytes.
Write str9 option bytes.
unlock str9 device.
All members of the swm050 microcontroller family from Foshan Synwit Tech.
flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
One swm050-specific command is defined:
Erases the entire flash bank.
Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. This driver doesn’t require the chip and bus width to be specified.
Some tms470-specific commands are defined:
Saves programming keys in a register, to enable flash erase and write commands.
Reports the clock speed, which is used to calculate timings.
Disables (1) or enables (0) use of the PLL to speed up the flash clock.
W60x series Wi-Fi SoC from WinnerMicro are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside. The w600 driver uses the target parameter to select the correct bank config.
flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
All members of the XMC1xxx microcontroller family from Infineon. This driver does not require the chip and bus width to be specified.
All members of the XMC4xxx microcontroller family from Infineon. This driver does not require the chip and bus width to be specified.
Some xmc4xxx-specific commands are defined:
Saves flash protection passwords which are used to lock the user flash
Removes Flash write protection from the selected user bank
Compared to NOR or SPI flash, NAND devices are inexpensive and high density. Today’s NAND chips, and multi-chip modules, commonly hold multiple GigaBytes of data.
NAND chips consist of a number of “erase blocks” of a given size (such as 128 KBytes), each of which is divided into a number of pages (of perhaps 512 or 2048 bytes each). Each page of a NAND flash has an “out of band” (OOB) area to hold Error Correcting Code (ECC) and other metadata, usually 16 bytes of OOB for every 512 bytes of page data.
One key characteristic of NAND flash is that its error rate is higher than that of NOR flash. In normal operation, that ECC is used to correct and detect errors. However, NAND blocks can also wear out and become unusable; those blocks are then marked "bad". NAND chips are even shipped from the manufacturer with a few bad blocks. The highest density chips use a technology (MLC) that wears out more quickly, so ECC support is increasingly important as a way to detect blocks that have begun to fail, and help to preserve data integrity with techniques such as wear leveling.
Software is used to manage the ECC. Some controllers don’t support ECC directly; in those cases, software ECC is used. Other controllers speed up the ECC calculations with hardware. Single-bit error correction hardware is routine. Controllers geared for newer MLC chips may correct 4 or more errors for every 512 bytes of data.
You will need to make sure that any data you write using
OpenOCD includes the appropriate kind of ECC. For example,
that may mean passing the oob_softecc flag when
writing NAND data, or ensuring that the correct hardware
ECC mode is used.
The basic steps for using NAND devices include:
nand device
nand probe.
nand subcommand
NOTE: At the time this text was written, the largest NAND flash fully supported by OpenOCD is 2 GiBytes (16 GiBits). This is because the variables used to hold offsets and lengths are only 32 bits wide. (Larger chips may work in some cases, unless an offset or length is larger than 0xffffffff, the largest 32-bit unsigned integer.) Some larger devices will work, since they are actually multi-chip modules with two smaller chips and individual chipselect lines.
NAND chips must be declared in configuration scripts, plus some additional configuration that’s done after OpenOCD has initialized.
Declares a NAND device, which can be read and written to
after it has been configured through nand probe.
In OpenOCD, devices are single chips; this is unlike some
operating systems, which may manage multiple chips as if
they were a single (larger) device.
In some cases, configuring a device will activate extra
commands; see the controller-specific documentation.
NOTE: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.
Prints a summary of each device declared
using nand device, numbered from zero.
Note that un-probed devices show no details.
> nand list
#0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
blocksize: 131072, blocks: 8192
#1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
blocksize: 131072, blocks: 8192
>
Probes the specified device to determine key characteristics
like its page and block sizes, and how many blocks it has.
The num parameter is the value shown by nand list.
You must (successfully) probe a device before you can use
it with most other NAND commands.
Reads binary data from the NAND device and writes it to the file,
starting at the specified offset.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset and length must be exact multiples of the device’s page size. They describe a data region; the OOB data associated with each such page may also be accessed.
NOTE: At the time this text was written, no error correction
was done on the data that’s read, unless raw access was disabled
and the underlying NAND controller driver had a read_page
method which handled that error correction.
By default, only page data is saved to the specified file. Use an oob_option parameter to save OOB data:
oob_raw
nand raw_access, which just
controls whether a hardware-aware access method is used.
oob_only
Erases blocks on the specified NAND device, starting at the
specified offset and continuing for length bytes.
Both of those values must be exact multiples of the device’s
block size, and the region they specify must fit entirely in the chip.
If those parameters are not specified,
the whole NAND chip will be erased.
The num parameter is the value shown by nand list.
NOTE: This command will try to erase bad blocks, when told
to do so, which will probably invalidate the manufacturer’s bad
block marker.
For the remainder of the current server session, nand info
will still report that the block “is” bad.
Writes binary data from the file into the specified NAND device,
starting at the specified offset. Those pages should already
have been erased; you can’t change zero bits to one bits.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset must be an exact multiple of the device’s page size. All data in the file will be written, assuming it doesn’t run past the end of the device. Only full pages are written, and any extra space in the last page will be filled with 0xff bytes. (That includes OOB data, if that’s being written.)
NOTE: At the time this text was written, bad blocks are ignored. That is, this routine will not skip bad blocks, but will instead try to write them. This can cause problems.
Provide at most one option parameter. With some
NAND drivers, the meanings of these parameters may change
if nand raw_access was used to disable hardware ECC.
write_page routine, that routine may write the OOB
with hardware-computed ECC data.
oob_only
oob_raw
write_page routine, that routine may modify the OOB
before it’s written, to include hardware-computed ECC data.
oob_softecc
oob_softecc_kw
Verify the binary data in the file has been programmed to the
specified NAND device, starting at the specified offset.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset must be an exact multiple of the device’s page size.
All data in the file will be read and compared to the contents of the
flash, assuming it doesn’t run past the end of the device.
As with nand write, only full pages are verified, so any extra
space in the last page will be filled with 0xff bytes.
The same options accepted by nand write,
and the file will be processed similarly to produce the buffers that
can be compared against the contents produced from nand dump.
NOTE: This will not work when the underlying NAND controller
driver’s write_page routine must update the OOB with a
hardware-computed ECC before the data is written. This limitation may
be removed in a future release.
Checks for manufacturer bad block markers on the specified NAND
device. If no parameters are provided, checks the whole
device; otherwise, starts at the specified offset and
continues for length bytes.
Both of those values must be exact multiples of the device’s
block size, and the region they specify must fit entirely in the chip.
The num parameter is the value shown by nand list.
NOTE: Before using this command you should force raw access
with nand raw_access enable to ensure that the underlying
driver will not try to apply hardware ECC.
The num parameter is the value shown by nand list.
This prints the one-line summary from "nand list", plus for
devices which have been probed this also prints any known
status for each block.
Sets or clears an flag affecting how page I/O is done.
The num parameter is the value shown by nand list.
This flag is cleared (disabled) by default, but changing that
value won’t affect all NAND devices. The key factor is whether
the underlying driver provides read_page or write_page
methods. If it doesn’t provide those methods, the setting of
this flag is irrelevant; all access is effectively “raw”.
When those methods exist, they are normally used when reading
data (nand dump or reading bad block markers) or
writing it (nand write). However, enabling
raw access (setting the flag) prevents use of those methods,
bypassing hardware ECC logic.
This can be a dangerous option, since writing blocks
with the wrong ECC data can cause them to be marked as bad.
As noted above, the nand device command allows
driver-specific options and behaviors.
Some controllers also activate controller-specific commands.
This driver handles the NAND controllers found on AT91SAM9 family chips from Atmel. It takes two extra parameters: address of the NAND chip; address of the ECC controller.
nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
AT91SAM9 chips support single-bit ECC hardware. The write_page and
read_page methods are used to utilize the ECC hardware unless they are
disabled by using the nand raw_access command. There are four
additional commands that are needed to fully configure the AT91SAM9 NAND
controller. Two are optional; most boards use the same wiring for ALE/CLE:
Configure the address line used for latching commands. The num
parameter is the value shown by nand list.
Configure the address line used for latching addresses. The num
parameter is the value shown by nand list.
For the next two commands, it is assumed that the pins have already been properly configured for input or output.
Configure the RDY/nBUSY input from the NAND device. The num
parameter is the value shown by nand list. pio_base_addr
is the base address of the PIO controller and pin is the pin number.
Configure the chip enable input to the NAND device. The num
parameter is the value shown by nand list. pio_base_addr
is the base address of the PIO controller and pin is the pin number.
This driver handles the NAND controllers found on DaVinci family chips from Texas Instruments. It takes three extra parameters: address of the NAND chip; hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix); address of the AEMIF controller on this processor.
nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
All DaVinci processors support the single-bit ECC hardware,
and newer ones also support the four-bit ECC hardware.
The write_page and read_page methods are used
to implement those ECC modes, unless they are disabled using
the nand raw_access command.
These controllers require an extra nand device
parameter: the clock rate used by the controller.
Configures use of the MLC or SLC controller mode.
MLC implies use of hardware ECC.
The num parameter is the value shown by nand list.
At this writing, this driver includes write_page
and read_page methods. Using nand raw_access
to disable those methods will prevent use of hardware ECC
in the MLC controller mode, but won’t change SLC behavior.
This driver handles the NAND controller in i.MX31. The mxc driver should work for this chip as well.
This driver handles the NAND controller found in Freescale i.MX chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35). The driver takes 3 extra arguments, chip (mx27, mx31, mx35), ecc (noecc, hwecc) and optionally if bad block information should be swapped between main area and spare area (biswap), defaults to off.
nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
Turns on/off bad block information swapping from main area, without parameter query status.
These controllers require an extra nand device
parameter: the address of the controller.
nand device orion 0xd8000000
These controllers don’t define any specialized commands.
At this writing, their drivers don’t include write_page
or read_page methods, so nand raw_access won’t
change any behavior.
These S3C family controllers don’t have any special
nand device options, and don’t define any
specialized commands.
At this writing, their drivers don’t include write_page
or read_page methods, so nand raw_access won’t
change any behavior.
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