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8 #ifndef OPENOCD_FLASH_NOR_STMQSPI_H
9 #define OPENOCD_FLASH_NOR_STMQSPI_H
14 #define QSPI_CR (0x00)
15 #define QSPI_DCR (0x04)
16 #define QSPI_SR (0x08)
17 #define QSPI_FCR (0x0C)
18 #define QSPI_DLR (0x10)
19 #define QSPI_CCR (0x14)
20 #define QSPI_AR (0x18)
21 #define QSPI_ABR (0x1C)
22 #define QSPI_DR (0x20)
25 #define SPI_FSEL_FLASH 7
26 #define SPI_DUAL_FLASH 6
30 #define SPI_FSIZE_POS 16
31 #define SPI_FSIZE_LEN 5
40 #define SPI_DMODE_POS 24
41 #define QSPI_DCYC_POS 18
42 #define QSPI_DCYC_LEN 5
43 #define QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)
44 #define SPI_ADSIZE_POS 12
46 #define QSPI_WRITE_MODE 0x00000000U
47 #define QSPI_READ_MODE 0x04000000U
48 #define QSPI_MM_MODE 0x0C000000U
49 #define QSPI_ALTB_MODE 0x0003C000U
50 #define QSPI_4LINE_MODE 0x03000F00U
51 #define QSPI_NO_DATA (~0x03000000U)
52 #define QSPI_NO_ALTB (~QSPI_ALTB_MODE)
53 #define QSPI_NO_ADDR (~0x00000C00U)
54 #define QSPI_ADDR3 (0x2U << SPI_ADSIZE_POS)
55 #define QSPI_ADDR4 (0x3U << SPI_ADSIZE_POS)
58 #define OCTOSPI_CR (0x000)
59 #define OCTOSPI_DCR1 (0x008)
60 #define OCTOSPI_DCR2 (0x00C)
61 #define OCTOSPI_DCR3 (0x010)
62 #define OCTOSPI_SR (0x020)
63 #define OCTOSPI_FCR (0x024)
64 #define OCTOSPI_DLR (0x040)
65 #define OCTOSPI_AR (0x048)
66 #define OCTOSPI_DR (0x050)
67 #define OCTOSPI_CCR (0x100)
68 #define OCTOSPI_TCR (0x108)
69 #define OCTOSPI_IR (0x110)
70 #define OCTOSPI_WCCR (0x180)
71 #define OCTOSPI_WIR (0x190)
72 #define OCTOSPI_MAGIC (0x3FC)
74 #define OCTO_MAGIC_ID 0xA3C5DD01
77 #define OCTOSPI_WRITE_MODE 0x00000000U
78 #define OCTOSPI_READ_MODE 0x10000000U
79 #define OCTOSPI_MM_MODE 0x30000000U
82 #define OCTOSPI_MTYP_POS (24)
83 #define OCTOSPI_MTYP_LEN (3)
84 #define OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)
87 #define OCTOSPI_ALTB_MODE 0x001F0000U
88 #define OCTOSPI_8LINE_MODE 0x0F003F3FU
89 #define OCTOSPI_NO_DATA (~0x0F000000U)
90 #define OCTOSPI_NO_ALTB (~OCTOSPI_ALTB_MODE)
91 #define OCTOSPI_NO_ADDR (~0x00000F00U)
92 #define OCTOSPI_ADDR3 (0x2U << SPI_ADSIZE_POS)
93 #define OCTOSPI_ADDR4 (0x3U << SPI_ADSIZE_POS)
94 #define OCTOSPI_DQSEN 29
95 #define OCTOSPI_DDTR 27
96 #define OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR))
97 #define OCTOSPI_ISIZE_MASK (0x30)
100 #define OCTOSPI_DCYC_POS 0
101 #define OCTOSPI_DCYC_LEN 5
102 #define OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)
104 #define IS_OCTOSPI (stmqspi_info->octo)
105 #define SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)
106 #define SPI_DCR (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)
107 #define SPI_SR (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)
108 #define SPI_FCR (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)
109 #define SPI_DLR (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)
110 #define SPI_AR (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)
111 #define SPI_DR (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)
112 #define SPI_CCR (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)