This represents an ARM Debug Interface (v5) Access Port (AP). More...

Collaboration diagram for adiv5_ap:

Data Fields
uint64_t	ap_num
	ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coherent, it should be renamed apsel. More...

uint32_t	cfg_reg

bool	config_ap_never_release

uint32_t	csw_default
	Default value for (MEM-AP) AP_REG_CSW register. More...

uint32_t	csw_size_probed_mask
	Probed CSW.Size data types for the MEM-AP. More...

uint32_t	csw_size_supported_mask
	Save the supported CSW.Size data types for the MEM-AP. More...

uint32_t	csw_value
	Cache for (MEM-AP) AP_REG_CSW register value. More...

struct adiv5_dap *	dap
	DAP this AP belongs to. More...

uint32_t	memaccess_tck
	Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read its status (and/or result). More...

bool	packed_transfers_probed

bool	packed_transfers_supported

unsigned int	refcount

uint32_t	tar_autoincr_block

bool	tar_valid

target_addr_t	tar_value
	Cache for (MEM-AP) AP_REG_TAR register value This is written to configure the address being read or written "-1" indicates no cached value. More...

bool	unaligned_access_bad

Detailed Description

This represents an ARM Debug Interface (v5) Access Port (AP).

Most common is a MEM-AP, for memory access.

Definition at line 250 of file arm_adi_v5.h.

Field Documentation

◆ ap_num

uint64_t adiv5_ap::ap_num

ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coherent, it should be renamed apsel.

Definition at line 261 of file arm_adi_v5.h.

Referenced by _dap_get_ap(), COMMAND_HANDLER(), cortex_a_examine_first(), dap_find_get_ap(), dap_get_ap(), dap_get_config_ap(), dap_info_ap_header(), dap_info_mem_ap_header(), dap_instance_init(), dap_lookup_cs_component(), dap_lookup_cs_component_cs_component(), dap_put_ap(), dap_queue_ap_read(), dap_queue_ap_write(), dmem_get_ap_reg_offset(), dmem_is_emulated_ap(), jtag_ap_q_bankselect(), mem_ap_setup_transfer_verify_size_packing(), rshim_ap_q_read(), rtp_rom_loop(), stlink_dap_ap_read(), stlink_dap_ap_write(), stlink_dap_op_queue_ap_write(), stlink_usb_count_misc_rw_queue(), stlink_usb_misc_rw_segment(), stm32l4_probe(), stm32l4_read_idcode(), swd_queue_ap_bankselect(), vdebug_dap_bankselect(), and xtensa_dm_examine().

◆ cfg_reg

uint32_t adiv5_ap::cfg_reg

Definition at line 322 of file arm_adi_v5.h.

Referenced by COMMAND_HANDLER(), dap_get_debugbase(), dap_instance_init(), dap_put_ap(), is_64bit_ap(), and mem_ap_init().

◆ config_ap_never_release

bool adiv5_ap::config_ap_never_release

Definition at line 328 of file arm_adi_v5.h.

Referenced by dap_get_config_ap(), dap_instance_init(), and is_ap_in_use().

◆ csw_default

uint32_t adiv5_ap::csw_default

Default value for (MEM-AP) AP_REG_CSW register.

Definition at line 266 of file arm_adi_v5.h.

Referenced by COMMAND_HANDLER(), dap_instance_init(), dap_put_ap(), mem_ap_setup_csw(), stlink_dap_op_queue_ap_read(), and stlink_dap_op_queue_ap_write().

◆ csw_size_probed_mask

uint32_t adiv5_ap::csw_size_probed_mask

Probed CSW.Size data types for the MEM-AP.

Each bit corresponds to a data type. 0b1 = Data size has been probed. 0b0 = Not yet probed. Bits assigned to sizes same way as above.

Definition at line 293 of file arm_adi_v5.h.

Referenced by mem_ap_init(), and mem_ap_setup_transfer_verify_size_packing().

◆ csw_size_supported_mask

uint32_t adiv5_ap::csw_size_supported_mask

Save the supported CSW.Size data types for the MEM-AP.

Each bit corresponds to a data type. 0b1 = Supported data size. 0b0 = Not supported. Bit 0 = Byte (8-bits) Bit 1 = Halfword (16-bits) Bit 2 = Word (32-bits) - always supported by spec. Bit 3 = Doubleword (64-bits) Bit 4 = 128-bits Bit 5 = 256-bits

Definition at line 286 of file arm_adi_v5.h.

Referenced by mem_ap_init(), and mem_ap_setup_transfer_verify_size_packing().