OpenOCD
stm32f1x.c
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1 /***************************************************************************
2  * Copyright (C) 2005 by Dominic Rath *
3  * Dominic.Rath@gmx.de *
4  * *
5  * Copyright (C) 2008 by Spencer Oliver *
6  * spen@spen-soft.co.uk *
7  * *
8  * Copyright (C) 2011 by Andreas Fritiofson *
9  * andreas.fritiofson@gmail.com *
10  *
11  * This program is free software; you can redistribute it and/or modify *
12  * it under the terms of the GNU General Public License as published by *
13  * the Free Software Foundation; either version 2 of the License, or *
14  * (at your option) any later version. *
15  * *
16  * This program is distributed in the hope that it will be useful, *
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19  * GNU General Public License for more details. *
20  * *
21  * You should have received a copy of the GNU General Public License *
22  * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23  ***************************************************************************/
24 
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28 
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 
34 /* stm32x register locations */
35 
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38 
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47 
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49  * There are valid cases, on dual flash devices the protection of the
50  * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59 
60 /* option byte location */
61 
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70 
71 /* FLASH_CR register bits */
72 
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 
82 /* FLASH_SR register bits */
83 
84 #define FLASH_BSY (1 << 0)
85 #define FLASH_PGERR (1 << 2)
86 #define FLASH_WRPRTERR (1 << 4)
87 #define FLASH_EOP (1 << 5)
88 
89 /* STM32_FLASH_OBR bit definitions (reading) */
90 
91 #define OPT_ERROR 0
92 #define OPT_READOUT 1
93 #define OPT_RDWDGSW 2
94 #define OPT_RDRSTSTOP 3
95 #define OPT_RDRSTSTDBY 4
96 #define OPT_BFB2 5 /* dual flash bank only */
97 
98 /* register unlock keys */
99 
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
102 
103 /* timeout values */
104 
105 #define FLASH_WRITE_TIMEOUT 10
106 #define FLASH_ERASE_TIMEOUT 100
107 
109  uint16_t RDP;
110  uint16_t user_options;
111  uint16_t user_data;
112  uint16_t protection[4];
113 };
114 
118  int probed;
119 
121  /* used to access dual flash bank stm32xl */
122  uint32_t register_base;
123  uint16_t default_rdp;
126  uint32_t user_bank_size;
127 };
128 
129 static int stm32x_mass_erase(struct flash_bank *bank);
130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
131 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
132  uint32_t offset, uint32_t count);
133 
134 /* flash bank stm32x <base> <size> 0 0 <target#>
135  */
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
137 {
138  struct stm32x_flash_bank *stm32x_info;
139 
140  if (CMD_ARGC < 6)
142 
143  stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
144 
145  bank->driver_priv = stm32x_info;
146  stm32x_info->probed = 0;
147  stm32x_info->has_dual_banks = false;
148  stm32x_info->register_base = FLASH_REG_BASE_B0;
149  stm32x_info->user_bank_size = bank->size;
150 
151  return ERROR_OK;
152 }
153 
154 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
155 {
156  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
157  return reg + stm32x_info->register_base;
158 }
159 
160 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
161 {
162  struct target *target = bank->target;
163  return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
164 }
165 
166 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
167 {
168  struct target *target = bank->target;
169  uint32_t status;
170  int retval = ERROR_OK;
171 
172  /* wait for busy to clear */
173  for (;;) {
174  retval = stm32x_get_flash_status(bank, &status);
175  if (retval != ERROR_OK)
176  return retval;
177  LOG_DEBUG("status: 0x%" PRIx32 "", status);
178  if ((status & FLASH_BSY) == 0)
179  break;
180  if (timeout-- <= 0) {
181  LOG_ERROR("timed out waiting for flash");
182  return ERROR_FAIL;
183  }
184  alive_sleep(1);
185  }
186 
187  if (status & FLASH_WRPRTERR) {
188  LOG_ERROR("stm32x device protected");
189  retval = ERROR_FAIL;
190  }
191 
192  if (status & FLASH_PGERR) {
193  LOG_ERROR("stm32x device programming failed");
194  retval = ERROR_FAIL;
195  }
196 
197  /* Clear but report errors */
198  if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
199  /* If this operation fails, we ignore it and report the original
200  * retval
201  */
203  FLASH_WRPRTERR | FLASH_PGERR);
204  }
205  return retval;
206 }
207 
209 {
210  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
211 
212  /* if we have a dual flash bank device then
213  * we need to perform option byte stuff on bank0 only */
214  if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
215  LOG_ERROR("Option Byte Operation's must use bank0");
217  }
218 
219  return ERROR_OK;
220 }
221 
222 static int stm32x_read_options(struct flash_bank *bank)
223 {
224  uint32_t optiondata;
225  struct stm32x_flash_bank *stm32x_info = NULL;
226  struct target *target = bank->target;
227 
228  stm32x_info = bank->driver_priv;
229 
230  /* read current option bytes */
231  int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232  if (retval != ERROR_OK)
233  return retval;
234 
235  stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
236  stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
237  stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
238 
239  if (optiondata & (1 << OPT_READOUT))
240  LOG_INFO("Device Security Bit Set");
241 
242  /* each bit refers to a 4bank protection */
243  retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
244  if (retval != ERROR_OK)
245  return retval;
246 
247  stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
248  stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
249  stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
250  stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
251 
252  return ERROR_OK;
253 }
254 
255 static int stm32x_erase_options(struct flash_bank *bank)
256 {
257  struct stm32x_flash_bank *stm32x_info = NULL;
258  struct target *target = bank->target;
259 
260  stm32x_info = bank->driver_priv;
261 
262  /* read current options */
263  stm32x_read_options(bank);
264 
265  /* unlock flash registers */
266  int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
267  if (retval != ERROR_OK)
268  return retval;
269 
270  retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
271  if (retval != ERROR_OK)
272  return retval;
273 
274  /* unlock option flash registers */
275  retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
276  if (retval != ERROR_OK)
277  return retval;
278  retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
279  if (retval != ERROR_OK)
280  return retval;
281 
282  /* erase option bytes */
284  if (retval != ERROR_OK)
285  return retval;
287  if (retval != ERROR_OK)
288  return retval;
289 
291  if (retval != ERROR_OK)
292  return retval;
293 
294  /* clear readout protection and complementary option bytes
295  * this will also force a device unlock if set */
296  stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
297 
298  return ERROR_OK;
299 }
300 
301 static int stm32x_write_options(struct flash_bank *bank)
302 {
303  struct stm32x_flash_bank *stm32x_info = NULL;
304  struct target *target = bank->target;
305 
306  stm32x_info = bank->driver_priv;
307 
308  /* unlock flash registers */
309  int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
310  if (retval != ERROR_OK)
311  return retval;
312  retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
313  if (retval != ERROR_OK)
314  return retval;
315 
316  /* unlock option flash registers */
317  retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
318  if (retval != ERROR_OK)
319  return retval;
320  retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
321  if (retval != ERROR_OK)
322  return retval;
323 
324  /* program option bytes */
326  if (retval != ERROR_OK)
327  return retval;
328 
329  uint8_t opt_bytes[16];
330 
331  target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
332  target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
333  target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
334  target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
335  target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
336  target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
337  target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
338  target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
339 
340  uint32_t offset = STM32_OB_RDP - bank->base;
341  retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
342  if (retval != ERROR_OK) {
344  LOG_ERROR("working area required to erase options bytes");
345  return retval;
346  }
347 
348  retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349  if (retval != ERROR_OK)
350  return retval;
351 
352  return ERROR_OK;
353 }
354 
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357  struct target *target = bank->target;
358  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
359 
360  uint32_t protection;
361  int i, s;
362  int num_bits;
363  int set;
364 
365  int retval = stm32x_check_operation_supported(bank);
366  if (ERROR_OK != retval)
367  return retval;
368 
369  /* medium density - each bit refers to a 4bank protection
370  * high density - each bit refers to a 2bank protection */
371  retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
372  if (retval != ERROR_OK)
373  return retval;
374 
375  /* medium density - each protection bit is for 4 * 1K pages
376  * high density - each protection bit is for 2 * 2K pages */
377  num_bits = (bank->num_sectors / stm32x_info->ppage_size);
378 
379  if (stm32x_info->ppage_size == 2) {
380  /* high density flash/connectivity line protection */
381 
382  set = 1;
383 
384  if (protection & (1 << 31))
385  set = 0;
386 
387  /* bit 31 controls sector 62 - 255 protection for high density
388  * bit 31 controls sector 62 - 127 protection for connectivity line */
389  for (s = 62; s < bank->num_sectors; s++)
390  bank->sectors[s].is_protected = set;
391 
392  if (bank->num_sectors > 61)
393  num_bits = 31;
394 
395  for (i = 0; i < num_bits; i++) {
396  set = 1;
397 
398  if (protection & (1 << i))
399  set = 0;
400 
401  for (s = 0; s < stm32x_info->ppage_size; s++)
402  bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403  }
404  } else {
405  /* low/medium density flash protection */
406  for (i = 0; i < num_bits; i++) {
407  set = 1;
408 
409  if (protection & (1 << i))
410  set = 0;
411 
412  for (s = 0; s < stm32x_info->ppage_size; s++)
413  bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
414  }
415  }
416 
417  return ERROR_OK;
418 }
419 
420 static int stm32x_erase(struct flash_bank *bank, int first, int last)
421 {
422  struct target *target = bank->target;
423  int i;
424 
425  if (bank->target->state != TARGET_HALTED) {
426  LOG_ERROR("Target not halted");
428  }
429 
430  if ((first == 0) && (last == (bank->num_sectors - 1)))
431  return stm32x_mass_erase(bank);
432 
433  /* unlock flash registers */
434  int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
435  if (retval != ERROR_OK)
436  return retval;
438  if (retval != ERROR_OK)
439  return retval;
440 
441  for (i = first; i <= last; i++) {
443  if (retval != ERROR_OK)
444  return retval;
445  retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
446  bank->base + bank->sectors[i].offset);
447  if (retval != ERROR_OK)
448  return retval;
449  retval = target_write_u32(target,
451  if (retval != ERROR_OK)
452  return retval;
453 
455  if (retval != ERROR_OK)
456  return retval;
457 
458  bank->sectors[i].is_erased = 1;
459  }
460 
462  if (retval != ERROR_OK)
463  return retval;
464 
465  return ERROR_OK;
466 }
467 
468 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
469 {
470  struct stm32x_flash_bank *stm32x_info = NULL;
471  struct target *target = bank->target;
472  uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
473  int i, reg, bit;
474  int status;
475  uint32_t protection;
476 
477  stm32x_info = bank->driver_priv;
478 
479  if (target->state != TARGET_HALTED) {
480  LOG_ERROR("Target not halted");
482  }
483 
484  int retval = stm32x_check_operation_supported(bank);
485  if (ERROR_OK != retval)
486  return retval;
487 
488  if ((first % stm32x_info->ppage_size) != 0) {
489  LOG_WARNING("aligned start protect sector to a %d sector boundary",
490  stm32x_info->ppage_size);
491  first = first - (first % stm32x_info->ppage_size);
492  }
493  if (((last + 1) % stm32x_info->ppage_size) != 0) {
494  LOG_WARNING("aligned end protect sector to a %d sector boundary",
495  stm32x_info->ppage_size);
496  last++;
497  last = last - (last % stm32x_info->ppage_size);
498  last--;
499  }
500 
501  /* medium density - each bit refers to a 4bank protection
502  * high density - each bit refers to a 2bank protection */
503  retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
504  if (retval != ERROR_OK)
505  return retval;
506 
507  prot_reg[0] = (uint16_t)protection;
508  prot_reg[1] = (uint16_t)(protection >> 8);
509  prot_reg[2] = (uint16_t)(protection >> 16);
510  prot_reg[3] = (uint16_t)(protection >> 24);
511 
512  if (stm32x_info->ppage_size == 2) {
513  /* high density flash */
514 
515  /* bit 7 controls sector 62 - 255 protection */
516  if (last > 61) {
517  if (set)
518  prot_reg[3] &= ~(1 << 7);
519  else
520  prot_reg[3] |= (1 << 7);
521  }
522 
523  if (first > 61)
524  first = 62;
525  if (last > 61)
526  last = 61;
527 
528  for (i = first; i <= last; i++) {
529  reg = (i / stm32x_info->ppage_size) / 8;
530  bit = (i / stm32x_info->ppage_size) - (reg * 8);
531 
532  if (set)
533  prot_reg[reg] &= ~(1 << bit);
534  else
535  prot_reg[reg] |= (1 << bit);
536  }
537  } else {
538  /* medium density flash */
539  for (i = first; i <= last; i++) {
540  reg = (i / stm32x_info->ppage_size) / 8;
541  bit = (i / stm32x_info->ppage_size) - (reg * 8);
542 
543  if (set)
544  prot_reg[reg] &= ~(1 << bit);
545  else
546  prot_reg[reg] |= (1 << bit);
547  }
548  }
549 
550  status = stm32x_erase_options(bank);
551  if (status != ERROR_OK)
552  return status;
553 
554  stm32x_info->option_bytes.protection[0] = prot_reg[0];
555  stm32x_info->option_bytes.protection[1] = prot_reg[1];
556  stm32x_info->option_bytes.protection[2] = prot_reg[2];
557  stm32x_info->option_bytes.protection[3] = prot_reg[3];
558 
559  return stm32x_write_options(bank);
560 }
561 
562 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
563  uint32_t offset, uint32_t count)
564 {
565  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
566  struct target *target = bank->target;
567  uint32_t buffer_size = 16384;
568  struct working_area *write_algorithm;
569  struct working_area *source;
570  uint32_t address = bank->base + offset;
571  struct reg_param reg_params[5];
572  struct armv7m_algorithm armv7m_info;
573  int retval = ERROR_OK;
574 
575  static const uint8_t stm32x_flash_write_code[] = {
576 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
577  };
578 
579  /* flash write code */
580  if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
581  &write_algorithm) != ERROR_OK) {
582  LOG_WARNING("no working area available, can't do block memory writes");
584  }
585 
586  retval = target_write_buffer(target, write_algorithm->address,
587  sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
588  if (retval != ERROR_OK)
589  return retval;
590 
591  /* memory buffer */
592  while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
593  buffer_size /= 2;
594  buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
595  if (buffer_size <= 256) {
596  /* we already allocated the writing code, but failed to get a
597  * buffer, free the algorithm */
598  target_free_working_area(target, write_algorithm);
599 
600  LOG_WARNING("no large enough working area available, can't do block memory writes");
602  }
603  }
604 
605  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
606  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
607  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
608  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
609  init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
610 
611  buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
612  buf_set_u32(reg_params[1].value, 0, 32, count);
613  buf_set_u32(reg_params[2].value, 0, 32, source->address);
614  buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
615  buf_set_u32(reg_params[4].value, 0, 32, address);
616 
617  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
618  armv7m_info.core_mode = ARM_MODE_THREAD;
619 
620  retval = target_run_flash_async_algorithm(target, buffer, count, 2,
621  0, NULL,
622  5, reg_params,
623  source->address, source->size,
624  write_algorithm->address, 0,
625  &armv7m_info);
626 
627  if (retval == ERROR_FLASH_OPERATION_FAILED) {
628  LOG_ERROR("flash write failed at address 0x%"PRIx32,
629  buf_get_u32(reg_params[4].value, 0, 32));
630 
631  if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
632  LOG_ERROR("flash memory not erased before writing");
633  /* Clear but report errors */
635  }
636 
637  if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
638  LOG_ERROR("flash memory write protected");
639  /* Clear but report errors */
641  }
642  }
643 
644  target_free_working_area(target, source);
645  target_free_working_area(target, write_algorithm);
646 
647  destroy_reg_param(&reg_params[0]);
648  destroy_reg_param(&reg_params[1]);
649  destroy_reg_param(&reg_params[2]);
650  destroy_reg_param(&reg_params[3]);
651  destroy_reg_param(&reg_params[4]);
652 
653  return retval;
654 }
655 
656 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
657  uint32_t offset, uint32_t count)
658 {
659  struct target *target = bank->target;
660  uint8_t *new_buffer = NULL;
661 
662  if (bank->target->state != TARGET_HALTED) {
663  LOG_ERROR("Target not halted");
665  }
666 
667  if (offset & 0x1) {
668  LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
670  }
671 
672  /* If there's an odd number of bytes, the data has to be padded. Duplicate
673  * the buffer and use the normal code path with a single block write since
674  * it's probably cheaper than to special case the last odd write using
675  * discrete accesses. */
676  if (count & 1) {
677  new_buffer = malloc(count + 1);
678  if (new_buffer == NULL) {
679  LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
680  return ERROR_FAIL;
681  }
682  LOG_INFO("odd number of bytes to write, padding with 0xff");
683  buffer = memcpy(new_buffer, buffer, count);
684  new_buffer[count++] = 0xff;
685  }
686 
687  uint32_t words_remaining = count / 2;
688  int retval, retval2;
689 
690  /* unlock flash registers */
692  if (retval != ERROR_OK)
693  goto cleanup;
695  if (retval != ERROR_OK)
696  goto cleanup;
697 
699  if (retval != ERROR_OK)
700  goto cleanup;
701 
702  /* try using a block write */
703  retval = stm32x_write_block(bank, buffer, offset, words_remaining);
704 
705  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
706  /* if block write failed (no sufficient working area),
707  * we use normal (slow) single halfword accesses */
708  LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
709 
710  while (words_remaining > 0) {
711  uint16_t value;
712  memcpy(&value, buffer, sizeof(uint16_t));
713 
714  retval = target_write_u16(target, bank->base + offset, value);
715  if (retval != ERROR_OK)
716  goto reset_pg_and_lock;
717 
718  retval = stm32x_wait_status_busy(bank, 5);
719  if (retval != ERROR_OK)
720  goto reset_pg_and_lock;
721 
722  words_remaining--;
723  buffer += 2;
724  offset += 2;
725  }
726  }
727 
728 reset_pg_and_lock:
730  if (retval == ERROR_OK)
731  retval = retval2;
732 
733 cleanup:
734  if (new_buffer)
735  free(new_buffer);
736 
737  return retval;
738 }
739 
740 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
741 {
742  /* This check the device CPUID core register to detect
743  * the M0 from the M3 devices. */
744 
745  struct target *target = bank->target;
746  uint32_t cpuid, device_id_register = 0;
747 
748  /* Get the CPUID from the ARM Core
749  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
750  int retval = target_read_u32(target, 0xE000ED00, &cpuid);
751  if (retval != ERROR_OK)
752  return retval;
753 
754  if (((cpuid >> 4) & 0xFFF) == 0xC20) {
755  /* 0xC20 is M0 devices */
756  device_id_register = 0x40015800;
757  } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
758  /* 0xC23 is M3 devices */
759  device_id_register = 0xE0042000;
760  } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
761  /* 0xC24 is M4 devices */
762  device_id_register = 0xE0042000;
763  } else {
764  LOG_ERROR("Cannot identify target as a stm32x");
765  return ERROR_FAIL;
766  }
767 
768  /* read stm32 device id register */
769  retval = target_read_u32(target, device_id_register, device_id);
770  if (retval != ERROR_OK)
771  return retval;
772 
773  return retval;
774 }
775 
776 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
777 {
778  struct target *target = bank->target;
779  uint32_t cpuid, flash_size_reg;
780 
781  int retval = target_read_u32(target, 0xE000ED00, &cpuid);
782  if (retval != ERROR_OK)
783  return retval;
784 
785  if (((cpuid >> 4) & 0xFFF) == 0xC20) {
786  /* 0xC20 is M0 devices */
787  flash_size_reg = 0x1FFFF7CC;
788  } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
789  /* 0xC23 is M3 devices */
790  flash_size_reg = 0x1FFFF7E0;
791  } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
792  /* 0xC24 is M4 devices */
793  flash_size_reg = 0x1FFFF7CC;
794  } else {
795  LOG_ERROR("Cannot identify target as a stm32x");
796  return ERROR_FAIL;
797  }
798 
799  retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
800  if (retval != ERROR_OK)
801  return retval;
802 
803  return retval;
804 }
805 
806 static int stm32x_probe(struct flash_bank *bank)
807 {
808  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
809  int i;
810  uint16_t flash_size_in_kb;
811  uint16_t max_flash_size_in_kb;
812  uint32_t device_id;
813  int page_size;
814  uint32_t base_address = 0x08000000;
815 
816  stm32x_info->probed = 0;
817  stm32x_info->register_base = FLASH_REG_BASE_B0;
818  stm32x_info->user_data_offset = 10;
819  stm32x_info->option_offset = 0;
820 
821  /* default factory protection level */
822  stm32x_info->default_rdp = 0x5AA5;
823 
824  /* read stm32 device id register */
825  int retval = stm32x_get_device_id(bank, &device_id);
826  if (retval != ERROR_OK)
827  return retval;
828 
829  LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
830 
831  /* set page size, protection granularity and max flash size depending on family */
832  switch (device_id & 0xfff) {
833  case 0x410: /* medium density */
834  page_size = 1024;
835  stm32x_info->ppage_size = 4;
836  max_flash_size_in_kb = 128;
837  break;
838  case 0x412: /* low density */
839  page_size = 1024;
840  stm32x_info->ppage_size = 4;
841  max_flash_size_in_kb = 32;
842  break;
843  case 0x414: /* high density */
844  page_size = 2048;
845  stm32x_info->ppage_size = 2;
846  max_flash_size_in_kb = 512;
847  break;
848  case 0x418: /* connectivity line density */
849  page_size = 2048;
850  stm32x_info->ppage_size = 2;
851  max_flash_size_in_kb = 256;
852  break;
853  case 0x420: /* value line density */
854  page_size = 1024;
855  stm32x_info->ppage_size = 4;
856  max_flash_size_in_kb = 128;
857  break;
858  case 0x422: /* stm32f302/3xb/c */
859  page_size = 2048;
860  stm32x_info->ppage_size = 2;
861  max_flash_size_in_kb = 256;
862  stm32x_info->user_data_offset = 16;
863  stm32x_info->option_offset = 6;
864  stm32x_info->default_rdp = 0x55AA;
865  break;
866  case 0x446: /* stm32f303xD/E */
867  page_size = 2048;
868  stm32x_info->ppage_size = 2;
869  max_flash_size_in_kb = 512;
870  stm32x_info->user_data_offset = 16;
871  stm32x_info->option_offset = 6;
872  stm32x_info->default_rdp = 0x55AA;
873  break;
874  case 0x428: /* value line High density */
875  page_size = 2048;
876  stm32x_info->ppage_size = 4;
877  max_flash_size_in_kb = 128;
878  break;
879  case 0x430: /* xl line density (dual flash banks) */
880  page_size = 2048;
881  stm32x_info->ppage_size = 2;
882  max_flash_size_in_kb = 1024;
883  stm32x_info->has_dual_banks = true;
884  break;
885  case 0x432: /* stm32f37x */
886  page_size = 2048;
887  stm32x_info->ppage_size = 2;
888  max_flash_size_in_kb = 256;
889  stm32x_info->user_data_offset = 16;
890  stm32x_info->option_offset = 6;
891  stm32x_info->default_rdp = 0x55AA;
892  break;
893  case 0x438: /* stm32f33x */
894  case 0x439: /* stm32f302x6/8 */
895  page_size = 2048;
896  stm32x_info->ppage_size = 2;
897  max_flash_size_in_kb = 64;
898  stm32x_info->user_data_offset = 16;
899  stm32x_info->option_offset = 6;
900  stm32x_info->default_rdp = 0x55AA;
901  break;
902  case 0x440: /* stm32f05x */
903  case 0x444: /* stm32f03x */
904  case 0x445: /* stm32f04x */
905  page_size = 1024;
906  stm32x_info->ppage_size = 4;
907  max_flash_size_in_kb = 64;
908  stm32x_info->user_data_offset = 16;
909  stm32x_info->option_offset = 6;
910  stm32x_info->default_rdp = 0x55AA;
911  break;
912  case 0x448: /* stm32f07x */
913  case 0x442: /* stm32f09x */
914  page_size = 2048;
915  stm32x_info->ppage_size = 4;
916  max_flash_size_in_kb = 256;
917  stm32x_info->user_data_offset = 16;
918  stm32x_info->option_offset = 6;
919  stm32x_info->default_rdp = 0x55AA;
920  break;
921  default:
922  LOG_WARNING("Cannot identify target as a STM32 family.");
923  return ERROR_FAIL;
924  }
925 
926  /* get flash size from target. */
927  retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
928 
929  /* failed reading flash size or flash size invalid (early silicon),
930  * default to max target family */
931  if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
932  LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
933  max_flash_size_in_kb);
934  flash_size_in_kb = max_flash_size_in_kb;
935  }
936 
937  if (stm32x_info->has_dual_banks) {
938  /* split reported size into matching bank */
939  if (bank->base != 0x08080000) {
940  /* bank 0 will be fixed 512k */
941  flash_size_in_kb = 512;
942  } else {
943  flash_size_in_kb -= 512;
944  /* bank1 also uses a register offset */
945  stm32x_info->register_base = FLASH_REG_BASE_B1;
946  base_address = 0x08080000;
947  }
948  }
949 
950  /* if the user sets the size manually then ignore the probed value
951  * this allows us to work around devices that have a invalid flash size register value */
952  if (stm32x_info->user_bank_size) {
953  LOG_INFO("ignoring flash probed value, using configured bank size");
954  flash_size_in_kb = stm32x_info->user_bank_size / 1024;
955  }
956 
957  LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
958 
959  /* did we assign flash size? */
960  assert(flash_size_in_kb != 0xffff);
961 
962  /* calculate numbers of pages */
963  int num_pages = flash_size_in_kb * 1024 / page_size;
964 
965  /* check that calculation result makes sense */
966  assert(num_pages > 0);
967 
968  if (bank->sectors) {
969  free(bank->sectors);
970  bank->sectors = NULL;
971  }
972 
973  bank->base = base_address;
974  bank->size = (num_pages * page_size);
975  bank->num_sectors = num_pages;
976  bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
977 
978  for (i = 0; i < num_pages; i++) {
979  bank->sectors[i].offset = i * page_size;
980  bank->sectors[i].size = page_size;
981  bank->sectors[i].is_erased = -1;
982  bank->sectors[i].is_protected = 1;
983  }
984 
985  stm32x_info->probed = 1;
986 
987  return ERROR_OK;
988 }
989 
990 static int stm32x_auto_probe(struct flash_bank *bank)
991 {
992  struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
993  if (stm32x_info->probed)
994  return ERROR_OK;
995  return stm32x_probe(bank);
996 }
997 
998 #if 0
999 COMMAND_HANDLER(stm32x_handle_part_id_command)
1000 {
1001  return ERROR_OK;
1002 }
1003 #endif
1004 
1005 static const char *get_stm32f0_revision(uint16_t rev_id)
1006 {
1007  const char *rev_str = NULL;
1008 
1009  switch (rev_id) {
1010  case 0x1000:
1011  rev_str = "1.0";
1012  break;
1013  case 0x2000:
1014  rev_str = "2.0";
1015  break;
1016  }
1017  return rev_str;
1018 }
1019 
1020 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1021 {
1022  uint32_t dbgmcu_idcode;
1023 
1024  /* read stm32 device id register */
1025  int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1026  if (retval != ERROR_OK)
1027  return retval;
1028 
1029  uint16_t device_id = dbgmcu_idcode & 0xfff;
1030  uint16_t rev_id = dbgmcu_idcode >> 16;
1031  const char *device_str;
1032  const char *rev_str = NULL;
1033 
1034  switch (device_id) {
1035  case 0x410:
1036  device_str = "STM32F10x (Medium Density)";
1037 
1038  switch (rev_id) {
1039  case 0x0000:
1040  rev_str = "A";
1041  break;
1042 
1043  case 0x2000:
1044  rev_str = "B";
1045  break;
1046 
1047  case 0x2001:
1048  rev_str = "Z";
1049  break;
1050 
1051  case 0x2003:
1052  rev_str = "Y";
1053  break;
1054  }
1055  break;
1056 
1057  case 0x412:
1058  device_str = "STM32F10x (Low Density)";
1059 
1060  switch (rev_id) {
1061  case 0x1000:
1062  rev_str = "A";
1063  break;
1064  }
1065  break;
1066 
1067  case 0x414:
1068  device_str = "STM32F10x (High Density)";
1069 
1070  switch (rev_id) {
1071  case 0x1000:
1072  rev_str = "A";
1073  break;
1074 
1075  case 0x1001:
1076  rev_str = "Z";
1077  break;
1078 
1079  case 0x1003:
1080  rev_str = "Y";
1081  break;
1082  }
1083  break;
1084 
1085  case 0x418:
1086  device_str = "STM32F10x (Connectivity)";
1087 
1088  switch (rev_id) {
1089  case 0x1000:
1090  rev_str = "A";
1091  break;
1092 
1093  case 0x1001:
1094  rev_str = "Z";
1095  break;
1096  }
1097  break;
1098 
1099  case 0x420:
1100  device_str = "STM32F100 (Low/Medium Density)";
1101 
1102  switch (rev_id) {
1103  case 0x1000:
1104  rev_str = "A";
1105  break;
1106 
1107  case 0x1001:
1108  rev_str = "Z";
1109  break;
1110  }
1111  break;
1112 
1113  case 0x422:
1114  device_str = "STM32F302xB/C";
1115 
1116  switch (rev_id) {
1117  case 0x1000:
1118  rev_str = "A";
1119  break;
1120 
1121  case 0x1001:
1122  rev_str = "Z";
1123  break;
1124 
1125  case 0x1003:
1126  rev_str = "Y";
1127  break;
1128 
1129  case 0x2000:
1130  rev_str = "B";
1131  break;
1132  }
1133  break;
1134 
1135  case 0x428:
1136  device_str = "STM32F100 (High Density)";
1137 
1138  switch (rev_id) {
1139  case 0x1000:
1140  rev_str = "A";
1141  break;
1142 
1143  case 0x1001:
1144  rev_str = "Z";
1145  break;
1146  }
1147  break;
1148 
1149  case 0x430:
1150  device_str = "STM32F10x (XL Density)";
1151 
1152  switch (rev_id) {
1153  case 0x1000:
1154  rev_str = "A";
1155  break;
1156  }
1157  break;
1158 
1159  case 0x432:
1160  device_str = "STM32F37x";
1161 
1162  switch (rev_id) {
1163  case 0x1000:
1164  rev_str = "A";
1165  break;
1166 
1167  case 0x2000:
1168  rev_str = "B";
1169  break;
1170  }
1171  break;
1172 
1173  case 0x438:
1174  device_str = "STM32F33x";
1175 
1176  switch (rev_id) {
1177  case 0x1000:
1178  rev_str = "A";
1179  break;
1180  }
1181  break;
1182 
1183  case 0x439:
1184  device_str = "STM32F302x6/8";
1185 
1186  switch (rev_id) {
1187  case 0x1000:
1188  rev_str = "A";
1189  break;
1190 
1191  case 0x1001:
1192  rev_str = "Z";
1193  break;
1194  }
1195  break;
1196 
1197  case 0x444:
1198  device_str = "STM32F03x";
1199  rev_str = get_stm32f0_revision(rev_id);
1200  break;
1201 
1202  case 0x440:
1203  device_str = "STM32F05x";
1204  rev_str = get_stm32f0_revision(rev_id);
1205  break;
1206 
1207  case 0x445:
1208  device_str = "STM32F04x";
1209  rev_str = get_stm32f0_revision(rev_id);
1210  break;
1211 
1212  case 0x446:
1213  device_str = "STM32F303xD/E";
1214  switch (rev_id) {
1215  case 0x1000:
1216  rev_str = "A";
1217  break;
1218  }
1219  break;
1220 
1221  case 0x448:
1222  device_str = "STM32F07x";
1223  rev_str = get_stm32f0_revision(rev_id);
1224  break;
1225 
1226  case 0x442:
1227  device_str = "STM32F09x";
1228  rev_str = get_stm32f0_revision(rev_id);
1229  break;
1230 
1231  default:
1232  snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1233  return ERROR_FAIL;
1234  }
1235 
1236  if (rev_str != NULL)
1237  snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1238  else
1239  snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1240 
1241  return ERROR_OK;
1242 }
1243 
1244 COMMAND_HANDLER(stm32x_handle_lock_command)
1245 {
1246  struct target *target = NULL;
1247  struct stm32x_flash_bank *stm32x_info = NULL;
1248 
1249  if (CMD_ARGC < 1)
1251 
1252  struct flash_bank *bank;
1253  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1254  if (ERROR_OK != retval)
1255  return retval;
1256 
1257  stm32x_info = bank->driver_priv;
1258 
1259  target = bank->target;
1260 
1261  if (target->state != TARGET_HALTED) {
1262  LOG_ERROR("Target not halted");
1263  return ERROR_TARGET_NOT_HALTED;
1264  }
1265 
1266  retval = stm32x_check_operation_supported(bank);
1267  if (ERROR_OK != retval)
1268  return retval;
1269 
1270  if (stm32x_erase_options(bank) != ERROR_OK) {
1271  command_print(CMD_CTX, "stm32x failed to erase options");
1272  return ERROR_OK;
1273  }
1274 
1275  /* set readout protection */
1276  stm32x_info->option_bytes.RDP = 0;
1277 
1278  if (stm32x_write_options(bank) != ERROR_OK) {
1279  command_print(CMD_CTX, "stm32x failed to lock device");
1280  return ERROR_OK;
1281  }
1282 
1283  command_print(CMD_CTX, "stm32x locked");
1284 
1285  return ERROR_OK;
1286 }
1287 
1288 COMMAND_HANDLER(stm32x_handle_unlock_command)
1289 {
1290  struct target *target = NULL;
1291 
1292  if (CMD_ARGC < 1)
1294 
1295  struct flash_bank *bank;
1296  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1297  if (ERROR_OK != retval)
1298  return retval;
1299 
1300  target = bank->target;
1301 
1302  if (target->state != TARGET_HALTED) {
1303  LOG_ERROR("Target not halted");
1304  return ERROR_TARGET_NOT_HALTED;
1305  }
1306 
1307  retval = stm32x_check_operation_supported(bank);
1308  if (ERROR_OK != retval)
1309  return retval;
1310 
1311  if (stm32x_erase_options(bank) != ERROR_OK) {
1312  command_print(CMD_CTX, "stm32x failed to unlock device");
1313  return ERROR_OK;
1314  }
1315 
1316  if (stm32x_write_options(bank) != ERROR_OK) {
1317  command_print(CMD_CTX, "stm32x failed to lock device");
1318  return ERROR_OK;
1319  }
1320 
1321  command_print(CMD_CTX, "stm32x unlocked.\n"
1322  "INFO: a reset or power cycle is required "
1323  "for the new settings to take effect.");
1324 
1325  return ERROR_OK;
1326 }
1327 
1328 COMMAND_HANDLER(stm32x_handle_options_read_command)
1329 {
1330  uint32_t optionbyte;
1331  struct target *target = NULL;
1332  struct stm32x_flash_bank *stm32x_info = NULL;
1333 
1334  if (CMD_ARGC < 1)
1336 
1337  struct flash_bank *bank;
1338  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1339  if (ERROR_OK != retval)
1340  return retval;
1341 
1342  stm32x_info = bank->driver_priv;
1343 
1344  target = bank->target;
1345 
1346  if (target->state != TARGET_HALTED) {
1347  LOG_ERROR("Target not halted");
1348  return ERROR_TARGET_NOT_HALTED;
1349  }
1350 
1351  retval = stm32x_check_operation_supported(bank);
1352  if (ERROR_OK != retval)
1353  return retval;
1354 
1355  retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1356  if (retval != ERROR_OK)
1357  return retval;
1358  command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1359 
1360  int user_data = optionbyte;
1361 
1362  if (optionbyte >> OPT_ERROR & 1)
1363  command_print(CMD_CTX, "Option Byte Complement Error");
1364 
1365  if (optionbyte >> OPT_READOUT & 1)
1366  command_print(CMD_CTX, "Readout Protection On");
1367  else
1368  command_print(CMD_CTX, "Readout Protection Off");
1369 
1370  /* user option bytes are offset depending on variant */
1371  optionbyte >>= stm32x_info->option_offset;
1372 
1373  if (optionbyte >> OPT_RDWDGSW & 1)
1374  command_print(CMD_CTX, "Software Watchdog");
1375  else
1376  command_print(CMD_CTX, "Hardware Watchdog");
1377 
1378  if (optionbyte >> OPT_RDRSTSTOP & 1)
1379  command_print(CMD_CTX, "Stop: No reset generated");
1380  else
1381  command_print(CMD_CTX, "Stop: Reset generated");
1382 
1383  if (optionbyte >> OPT_RDRSTSTDBY & 1)
1384  command_print(CMD_CTX, "Standby: No reset generated");
1385  else
1386  command_print(CMD_CTX, "Standby: Reset generated");
1387 
1388  if (stm32x_info->has_dual_banks) {
1389  if (optionbyte >> OPT_BFB2 & 1)
1390  command_print(CMD_CTX, "Boot: Bank 0");
1391  else
1392  command_print(CMD_CTX, "Boot: Bank 1");
1393  }
1394 
1395  command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1396  (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
1397  command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1398  (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
1399 
1400  return ERROR_OK;
1401 }
1402 
1403 COMMAND_HANDLER(stm32x_handle_options_write_command)
1404 {
1405  struct target *target = NULL;
1406  struct stm32x_flash_bank *stm32x_info = NULL;
1407  uint16_t optionbyte;
1408 
1409  if (CMD_ARGC < 2)
1411 
1412  struct flash_bank *bank;
1413  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1414  if (ERROR_OK != retval)
1415  return retval;
1416 
1417  stm32x_info = bank->driver_priv;
1418 
1419  target = bank->target;
1420 
1421  if (target->state != TARGET_HALTED) {
1422  LOG_ERROR("Target not halted");
1423  return ERROR_TARGET_NOT_HALTED;
1424  }
1425 
1426  retval = stm32x_check_operation_supported(bank);
1427  if (ERROR_OK != retval)
1428  return retval;
1429 
1430  retval = stm32x_read_options(bank);
1431  if (ERROR_OK != retval)
1432  return retval;
1433 
1434  /* start with current options */
1435  optionbyte = stm32x_info->option_bytes.user_options;
1436 
1437  /* skip over flash bank */
1438  CMD_ARGC--;
1439  CMD_ARGV++;
1440 
1441  while (CMD_ARGC) {
1442  if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1443  optionbyte |= (1 << 0);
1444  else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1445  optionbyte &= ~(1 << 0);
1446  else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1447  optionbyte |= (1 << 1);
1448  else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1449  optionbyte &= ~(1 << 1);
1450  else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1451  optionbyte |= (1 << 2);
1452  else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1453  optionbyte &= ~(1 << 2);
1454  else if (stm32x_info->has_dual_banks) {
1455  if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1456  optionbyte |= (1 << 3);
1457  else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1458  optionbyte &= ~(1 << 3);
1459  else
1461  } else
1463  CMD_ARGC--;
1464  CMD_ARGV++;
1465  }
1466 
1467  if (stm32x_erase_options(bank) != ERROR_OK) {
1468  command_print(CMD_CTX, "stm32x failed to erase options");
1469  return ERROR_OK;
1470  }
1471 
1472  stm32x_info->option_bytes.user_options = optionbyte;
1473 
1474  if (stm32x_write_options(bank) != ERROR_OK) {
1475  command_print(CMD_CTX, "stm32x failed to write options");
1476  return ERROR_OK;
1477  }
1478 
1479  command_print(CMD_CTX, "stm32x write options complete.\n"
1480  "INFO: a reset or power cycle is required "
1481  "for the new settings to take effect.");
1482 
1483  return ERROR_OK;
1484 }
1485 
1486 static int stm32x_mass_erase(struct flash_bank *bank)
1487 {
1488  struct target *target = bank->target;
1489 
1490  if (target->state != TARGET_HALTED) {
1491  LOG_ERROR("Target not halted");
1492  return ERROR_TARGET_NOT_HALTED;
1493  }
1494 
1495  /* unlock option flash registers */
1496  int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1497  if (retval != ERROR_OK)
1498  return retval;
1499  retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1500  if (retval != ERROR_OK)
1501  return retval;
1502 
1503  /* mass erase flash memory */
1505  if (retval != ERROR_OK)
1506  return retval;
1507  retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1508  FLASH_MER | FLASH_STRT);
1509  if (retval != ERROR_OK)
1510  return retval;
1511 
1513  if (retval != ERROR_OK)
1514  return retval;
1515 
1517  if (retval != ERROR_OK)
1518  return retval;
1519 
1520  return ERROR_OK;
1521 }
1522 
1523 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1524 {
1525  int i;
1526 
1527  if (CMD_ARGC < 1)
1529 
1530  struct flash_bank *bank;
1531  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1532  if (ERROR_OK != retval)
1533  return retval;
1534 
1535  retval = stm32x_mass_erase(bank);
1536  if (retval == ERROR_OK) {
1537  /* set all sectors as erased */
1538  for (i = 0; i < bank->num_sectors; i++)
1539  bank->sectors[i].is_erased = 1;
1540 
1541  command_print(CMD_CTX, "stm32x mass erase complete");
1542  } else
1543  command_print(CMD_CTX, "stm32x mass erase failed");
1544 
1545  return retval;
1546 }
1547 
1549  {
1550  .name = "lock",
1551  .handler = stm32x_handle_lock_command,
1552  .mode = COMMAND_EXEC,
1553  .usage = "bank_id",
1554  .help = "Lock entire flash device.",
1555  },
1556  {
1557  .name = "unlock",
1558  .handler = stm32x_handle_unlock_command,
1559  .mode = COMMAND_EXEC,
1560  .usage = "bank_id",
1561  .help = "Unlock entire protected flash device.",
1562  },
1563  {
1564  .name = "mass_erase",
1565  .handler = stm32x_handle_mass_erase_command,
1566  .mode = COMMAND_EXEC,
1567  .usage = "bank_id",
1568  .help = "Erase entire flash device.",
1569  },
1570  {
1571  .name = "options_read",
1572  .handler = stm32x_handle_options_read_command,
1573  .mode = COMMAND_EXEC,
1574  .usage = "bank_id",
1575  .help = "Read and display device option byte.",
1576  },
1577  {
1578  .name = "options_write",
1579  .handler = stm32x_handle_options_write_command,
1580  .mode = COMMAND_EXEC,
1581  .usage = "bank_id ('SWWDG'|'HWWDG') "
1582  "('RSTSTNDBY'|'NORSTSTNDBY') "
1583  "('RSTSTOP'|'NORSTSTOP')",
1584  .help = "Replace bits in device option byte.",
1585  },
1587 };
1588 
1590  {
1591  .name = "stm32f1x",
1592  .mode = COMMAND_ANY,
1593  .help = "stm32f1x flash command group",
1594  .usage = "",
1596  },
1598 };
1599 
1601  .name = "stm32f1x",
1602  .commands = stm32x_command_handlers,
1603  .flash_bank_command = stm32x_flash_bank_command,
1604  .erase = stm32x_erase,
1605  .protect = stm32x_protect,
1606  .write = stm32x_write,
1607  .read = default_flash_read,
1608  .probe = stm32x_probe,
1609  .auto_probe = stm32x_auto_probe,
1610  .erase_check = default_flash_blank_check,
1611  .protect_check = stm32x_protect_check,
1612  .info = get_stm32x_info,
1613  .free_driver_priv = default_flash_free_driver_priv,
1614 };
struct stm32x_options option_bytes
Definition: stm32f1x.c:116
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:40
uint16_t default_rdp
Definition: stm32f1x.c:123
static int stm32x_probe(struct flash_bank *bank)
Definition: stm32f1x.c:806
#define LOG_DEBUG(expr...)
Definition: log.h:115
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
static int stm32x_write_options(struct flash_bank *bank)
Definition: stm32f1x.c:301
#define STM32_FLASH_OPTKEYR_B0
Definition: stm32f1x.c:53
#define STM32_OB_RDP
Definition: stm32f1x.c:62
#define FLASH_STRT
Definition: stm32f1x.c:78
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
#define FLASH_OPTWRE
Definition: stm32f1x.c:80
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:43
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
Definition: flash/common.h:42
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
Definition: stm32f1x.c:740
#define FLASH_ERASE_TIMEOUT
Definition: stm32f1x.c:106
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
uint32_t size
The size of this chip bank, in bytes.
Definition: nor/core.h:95
#define STM32_FLASH_CR
Definition: stm32f1x.c:43
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
#define LOG_INFO(expr...)
Definition: log.h:123
COMMAND_HANDLER(stm32x_handle_lock_command)
Definition: stm32f1x.c:1244
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:693
int target_write_u16(struct target *target, target_addr_t address, uint16_t value)
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:45
#define OPT_RDRSTSTDBY
Definition: stm32f1x.c:95
#define CALL_COMMAND_HANDLER(name, extra...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:105
void * driver_priv
Private driver storage pointer.
Definition: nor/core.h:91
Definition: psoc6.c:94
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
Definition: stm32f1x.c:1020
static int stm32x_check_operation_supported(struct flash_bank *bank)
Definition: stm32f1x.c:208
static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
Definition: stm32f1x.c:160
struct flash_sector * sectors
Array of sectors, allocated and initialized by the flash driver.
Definition: nor/core.h:126
#define ERROR_FAIL
Definition: log.h:150
Support functions to access arbitrary bits in a byte array.
static int stm32x_read_options(struct flash_bank *bank)
Definition: stm32f1x.c:222
#define FLASH_REG_BASE_B0
Definition: stm32f1x.c:36
#define OPT_RDWDGSW
Definition: stm32f1x.c:93
static const struct command_registration stm32x_exec_command_handlers[]
Definition: stm32f1x.c:1548
static int stm32x_erase_options(struct flash_bank *bank)
Definition: stm32f1x.c:255
#define FLASH_PG
Definition: stm32f1x.c:73
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:138
static int stm32x_auto_probe(struct flash_bank *bank)
Definition: stm32f1x.c:990
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:133
uint32_t offset
Definition: arm_cti.c:179
#define OPT_RDRSTSTOP
Definition: stm32f1x.c:94
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:40
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
uint16_t RDP
Definition: stm32f1x.c:109
#define FLASH_PER
Definition: stm32f1x.c:74
#define KEY2
Definition: stm32f1x.c:101
int target_free_working_area(struct target *target, struct working_area *area)
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:40
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
static int stm32x_mass_erase(struct flash_bank *bank)
Definition: stm32f1x.c:1486
#define FLASH_MER
Definition: stm32f1x.c:75
uint32_t register_base
Definition: stm32f1x.c:122
enum arm_mode core_mode
Definition: armv7m.h:185
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
Definition: stm32f1x.c:166
int is_erased
Indication of erasure status: 0 = not erased, 1 = erased, other = unknown.
Definition: nor/core.h:52
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:142
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:239
#define OPT_ERROR
Definition: stm32f1x.c:91
#define LOG_ERROR(expr...)
Definition: log.h:129
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:363
enum target_state state
Definition: target.h:168
#define STM32_FLASH_SR
Definition: stm32f1x.c:42
static int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
Definition: stm32f1x.c:154
const char * name
Definition: command.h:220
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:128
Definition: register.h:119
#define STM32_FLASH_CR_B0
Definition: stm32f1x.c:55
#define FLASH_OPTPG
Definition: stm32f1x.c:76
static int stm32x_erase(struct flash_bank *bank, int first, int last)
Definition: stm32f1x.c:420
#define OPT_READOUT
Definition: stm32f1x.c:92
static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
Definition: stm32f1x.c:776
struct target * target
Target to which this bank belongs.
Definition: nor/core.h:88
uint16_t user_options
Definition: stm32f1x.c:110
#define FLASH_WRPRTERR
Definition: stm32f1x.c:86
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
#define FLASH_REG_BASE_B1
Definition: stm32f1x.c:37
void command_print(struct command_context *context, const char *format,...)
Definition: command.c:528
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:697
uint16_t protection[4]
Definition: stm32f1x.c:112
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word...
Definition: binarybuffer.h:107
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
#define FLASH_BSY
Definition: stm32f1x.c:84
#define FLASH_LOCK
Definition: stm32f1x.c:79
#define OPT_BFB2
Definition: stm32f1x.c:96
int num_sectors
The number of sectors on this chip.
Definition: nor/core.h:124
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:85
#define KEY1
Definition: stm32f1x.c:100
#define STM32_FLASH_KEYR_B0
Definition: stm32f1x.c:52
uint32_t user_bank_size
Definition: stm32f1x.c:126
static const char * get_stm32f0_revision(uint16_t rev_id)
Definition: stm32f1x.c:1005
uint16_t user_data
Definition: stm32f1x.c:111
static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32f1x.c:656
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:48
#define ERROR_OK
Definition: log.h:144
struct flash_driver stm32f1x_flash
Definition: stm32f1x.c:1600
void alive_sleep(uint64_t ms)
Definition: helper/log.c:465
#define STM32_FLASH_WRPR_B0
Definition: stm32f1x.c:58
#define STM32_FLASH_OBR_B0
Definition: stm32f1x.c:57
#define FLASH_OPTER
Definition: stm32f1x.c:77
static int count
Definition: helper/log.c:62
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
uint32_t size
Definition: target.h:97
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
Definition: stm32f1x.c:136
static const struct command_registration stm32x_command_handlers[]
Definition: stm32f1x.c:1589
static int stm32x_protect_check(struct flash_bank *bank)
Definition: stm32f1x.c:355
int common_magic
Definition: armv7m.h:183
#define NULL
Definition: usb.h:27
#define FLASH_PGERR
Definition: stm32f1x.c:85
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown...
Definition: nor/core.h:65
static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
Definition: stm32f1x.c:468
static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32f1x.c:562
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:41
#define LOG_WARNING(expr...)
Definition: log.h:126
Definition: target.h:126
#define STM32_FLASH_KEYR
Definition: stm32f1x.c:40
uint32_t base
The base address of this bank.
Definition: nor/core.h:94
#define STM32_FLASH_AR
Definition: stm32f1x.c:44
target_addr_t address
Definition: target.h:96