OpenOCD
nuc910.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2010 by Spencer Oliver *
5  * spen@spen-soft.co.uk *
6  ***************************************************************************/
7 
8 /*
9  * NAND controller interface for Nuvoton NUC910
10  */
11 
12 #ifndef OPENOCD_FLASH_NAND_NUC910_H
13 #define OPENOCD_FLASH_NAND_NUC910_H
14 
15 #define NUC910_FMICSR 0xB000D000
16 #define NUC910_SMCSR 0xB000D0A0
17 #define NUC910_SMTCR 0xB000D0A4
18 #define NUC910_SMIER 0xB000D0A8
19 #define NUC910_SMISR 0xB000D0AC
20 #define NUC910_SMCMD 0xB000D0B0
21 #define NUC910_SMADDR 0xB000D0B4
22 #define NUC910_SMDATA 0xB000D0B8
23 
24 #define NUC910_SMECC0 0xB000D0BC
25 #define NUC910_SMECC1 0xB000D0C0
26 #define NUC910_SMECC2 0xB000D0C4
27 #define NUC910_SMECC3 0xB000D0C8
28 #define NUC910_ECC4ST 0xB000D114
29 
30 /* Global Control and Status Register (FMICSR) */
31 #define NUC910_FMICSR_SM_EN (1<<3)
32 
33 /* NAND Flash Address Port Register (SMADDR) */
34 #define NUC910_SMADDR_EOA (1<<31)
35 
36 /* NAND Flash Control and Status Register (SMCSR) */
37 #define NUC910_SMCSR_PSIZE (1<<3)
38 #define NUC910_SMCSR_DBW (1<<4)
39 
40 /* NAND Flash Interrupt Status Register (SMISR) */
41 #define NUC910_SMISR_ECC_IF (1<<2)
42 #define NUC910_SMISR_RB_ (1<<18)
43 
44 /* ECC4 Correction Status (ECC4ST) */
45 
46 #endif /* OPENOCD_FLASH_NAND_NUC910_H */