OpenOCD
mips_ejtag.c
Go to the documentation of this file.
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2008 by Spencer Oliver *
5  * spen@spen-soft.co.uk *
6  * *
7  * Copyright (C) 2008 by David T.L. Wong *
8  * *
9  * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
10  ***************************************************************************/
11 
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15 
16 #include "mips32.h"
17 #include "mips_ejtag.h"
18 #include "mips32_dmaacc.h"
19 #include "mips64.h"
20 #include "mips64_pracc.h"
21 
22 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
23 {
24  assert(ejtag_info->tap);
25  struct jtag_tap *tap = ejtag_info->tap;
26 
27  if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
28 
29  struct scan_field field;
30  field.num_bits = tap->ir_length;
31 
32  uint8_t t[4] = { 0 };
33  field.out_value = t;
34  buf_set_u32(t, 0, field.num_bits, new_instr);
35 
36  field.in_value = NULL;
37 
38  jtag_add_ir_scan(tap, &field, TAP_IDLE);
39  }
40 }
41 
42 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info)
43 {
45 
46  ejtag_info->idcode = 0;
47  return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->idcode);
48 }
49 
50 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info)
51 {
53 
54  ejtag_info->impcode = 0;
55  return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->impcode);
56 }
57 
58 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
59 {
60  assert(ejtag_info->tap);
61  struct jtag_tap *tap = ejtag_info->tap;
62 
63  struct scan_field field;
64  uint8_t out_scan[12];
65 
66  /* processor access "all" register 96 bit */
67  field.num_bits = 96;
68 
69  field.out_value = out_scan;
70  buf_set_u32(out_scan, 0, 32, ctrl);
71  buf_set_u32(out_scan + 4, 0, 32, data);
72  buf_set_u32(out_scan + 8, 0, 32, 0);
73 
74  field.in_value = in_scan_buf;
75 
76  jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
77 
78  keep_alive();
79 }
80 
81 int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data)
82 {
83  struct jtag_tap *tap;
84  tap = ejtag_info->tap;
85 
86  if (!tap)
87  return ERROR_FAIL;
88  struct scan_field field;
89  uint8_t t[8] = { 0 }, r[8];
90  int retval;
91 
92  field.num_bits = 64;
93  field.out_value = t;
94  buf_set_u64(t, 0, field.num_bits, *data);
95  field.in_value = r;
96 
97  jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
98  retval = jtag_execute_queue();
99  if (retval != ERROR_OK) {
100  LOG_ERROR("register read failed");
101  return retval;
102  }
103 
104  *data = buf_get_u64(field.in_value, 0, 64);
105 
106  keep_alive();
107 
108  return ERROR_OK;
109 }
110 
111 static void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info,
112  uint32_t data_out, uint8_t *data_in)
113 {
114  assert(ejtag_info->tap);
115  struct jtag_tap *tap = ejtag_info->tap;
116 
117  struct scan_field field;
118  field.num_bits = 32;
119 
120  uint8_t scan_out[4] = { 0 };
121  field.out_value = scan_out;
122  buf_set_u32(scan_out, 0, field.num_bits, data_out);
123 
124  field.in_value = data_in;
125  jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
126 
127  keep_alive();
128 }
129 
130 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
131 {
132  uint8_t scan_in[4];
133  mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
134 
135  int retval = jtag_execute_queue();
136  if (retval != ERROR_OK) {
137  LOG_ERROR("register read failed");
138  return retval;
139  }
140 
141  *data = buf_get_u32(scan_in, 0, 32);
142  return ERROR_OK;
143 }
144 
145 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
146 {
147  mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
148 }
149 
150 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
151 {
152  assert(ejtag_info->tap);
153  struct jtag_tap *tap = ejtag_info->tap;
154 
155  struct scan_field field;
156  field.num_bits = 8;
157 
158  field.out_value = data;
159  field.in_value = data;
160 
161  jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
162 
163  int retval = jtag_execute_queue();
164  if (retval != ERROR_OK) {
165  LOG_ERROR("register read failed");
166  return retval;
167  }
168  return ERROR_OK;
169 }
170 
171 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
172 {
173  assert(ejtag_info->tap);
174  struct jtag_tap *tap = ejtag_info->tap;
175 
176  struct scan_field field;
177  field.num_bits = 8;
178 
179  field.out_value = &data;
180  field.in_value = NULL;
181 
182  jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
183 }
184 
185 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
186 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
187 {
188  struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
189  pracc_queue_init(&ctx);
190 
191  pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 23, 0)); /* move COP0 Debug to $8 */
192  pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, 0x0100)); /* set SSt bit in debug reg */
193  if (!enable_step)
194  pracc_add(&ctx, 0, MIPS32_XORI(ctx.isa, 8, 8, 0x0100)); /* clear SSt bit in debug reg */
195 
196  pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 8, 23, 0)); /* move $8 to COP0 Debug */
197  pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
198  pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
199  pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
200 
202  pracc_queue_free(&ctx);
203  return ctx.retval;
204 }
205 
206 /*
207  * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
208  * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
209  * For example bcm7401 and others. At leas on some
210  * CPUs, DebugMode wont start if this bit is not removed.
211  */
213 {
214  uint32_t dcr;
215  int retval;
216 
218  if (retval != ERROR_OK)
219  goto error;
220 
221  dcr &= ~EJTAG_DCR_MP;
223  if (retval != ERROR_OK)
224  goto error;
225  return ERROR_OK;
226 error:
227  LOG_ERROR("Failed to remove DCR MPbit!");
228  return retval;
229 }
230 
232 {
233  uint32_t ejtag_ctrl;
235 
238  goto error;
239  }
240 
241  /* set debug break bit */
242  ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
243  mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
244 
245  /* break bit will be cleared by hardware */
246  ejtag_ctrl = ejtag_info->ejtag_ctrl;
247  mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
248  LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
249  if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
250  goto error;
251 
252  return ERROR_OK;
253 error:
254  LOG_ERROR("Failed to enter Debug Mode!");
255  return ERROR_FAIL;
256 }
257 
259 {
260  struct pa_list pracc_list = {.instr = MIPS32_DRET(ejtag_info->isa), .addr = 0};
261  struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0};
262  struct mips32_common *mips32 = container_of(ejtag_info,
263  struct mips32_common, ejtag_info);
264 
265  /* execute our dret instruction */
267  mips32->cpu_quirks & EJTAG_QUIRK_PAD_DRET);
268 
269  /* pic32mx workaround, false pending at low core clock */
270  jtag_add_sleep(1000);
271  return ctx.retval;
272 }
273 
274 /* mips_ejtag_init_mmr - assign Memory-Mapped Registers depending
275  * on EJTAG version.
276  */
278 {
284 
290 
293  } else {
299 
306 
309  }
310 }
311 
313 {
314  LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
315  EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
316  EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
317  EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
318  EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
319  EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
320  EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
321  EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
322  EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
323  LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
326 }
327 
329 {
330  LOG_DEBUG("EJTAG v2.6: features:%s%s",
331  EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
332  EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
333 }
334 
336 {
337  LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
338  EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
339  EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
340  EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
341  EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
342  EJTAG_IMP_HAS(EJTAG_IMP_MIPS64) ? " MIPS64" : " MIPS32");
343 
344  switch (ejtag_info->ejtag_version) {
345  case EJTAG_VERSION_20:
347  break;
348  case EJTAG_VERSION_25:
349  case EJTAG_VERSION_26:
350  case EJTAG_VERSION_31:
351  case EJTAG_VERSION_41:
352  case EJTAG_VERSION_51:
354  break;
355  default:
356  break;
357  }
358 }
359 
361 {
362  int retval = mips_ejtag_get_impcode(ejtag_info);
363  if (retval != ERROR_OK) {
364  LOG_ERROR("impcode read failed");
365  return retval;
366  }
367 
368  /* get ejtag version */
369  ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
370 
371  switch (ejtag_info->ejtag_version) {
372  case EJTAG_VERSION_20:
373  LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
374  break;
375  case EJTAG_VERSION_25:
376  LOG_DEBUG("EJTAG: Version 2.5 Detected");
377  break;
378  case EJTAG_VERSION_26:
379  LOG_DEBUG("EJTAG: Version 2.6 Detected");
380  break;
381  case EJTAG_VERSION_31:
382  LOG_DEBUG("EJTAG: Version 3.1 Detected");
383  break;
384  case EJTAG_VERSION_41:
385  LOG_DEBUG("EJTAG: Version 4.1 Detected");
386  break;
387  case EJTAG_VERSION_51:
388  LOG_DEBUG("EJTAG: Version 5.1 Detected");
389  break;
390  default:
391  LOG_DEBUG("EJTAG: Unknown Version Detected");
392  break;
393  }
395 
396  if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
397  LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
398  "workaround current broken code.");
400  }
401 
403 
406 
408 
410 
411  return ERROR_OK;
412 }
413 
414 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
415 {
416  assert(ejtag_info->tap);
417  struct jtag_tap *tap = ejtag_info->tap;
418 
419  struct scan_field fields[2];
420 
421  /* fastdata 1-bit register */
422  fields[0].num_bits = 1;
423 
424  uint8_t spracc = 0;
425  fields[0].out_value = &spracc;
426  fields[0].in_value = NULL;
427 
428  /* processor access data register 32 bit */
429  fields[1].num_bits = 32;
430 
431  uint8_t t[4] = {0, 0, 0, 0};
432  fields[1].out_value = t;
433 
434  if (write_t) {
435  fields[1].in_value = NULL;
436  buf_set_u32(t, 0, 32, *data);
437  } else
438  fields[1].in_value = (uint8_t *) data;
439 
440  jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
441 
442  if (!write_t && data)
444  (jtag_callback_data_t) data);
445 
446  keep_alive();
447 
448  return ERROR_OK;
449 }
450 
451 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
452 {
453  const uint32_t code_enable[] = {
454  MIPS64_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */
455  MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
456  MIPS64_ORI(1, 1, 0x0100), /* set SSt bit in debug reg */
457  MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
458  MIPS64_B(NEG16(5)),
459  MIPS64_MFC0(1, 31, 0), /* move COP0 DeSave to $1 */
460  MIPS64_NOP,
461  MIPS64_NOP,
462  MIPS64_NOP,
463  MIPS64_NOP,
464  MIPS64_NOP,
465  MIPS64_NOP,
466  MIPS64_NOP,
467  MIPS64_NOP,
468  };
469 
470  const uint32_t code_disable[] = {
471  MIPS64_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
472  MIPS64_LUI(15, UPPER16(MIPS64_PRACC_STACK)), /* $15 = MIPS64_PRACC_STACK */
474  MIPS64_SD(1, 0, 15), /* sw $1,($15) */
475  MIPS64_SD(2, 0, 15), /* sw $2,($15) */
476  MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
477  MIPS64_LUI(2, 0xFFFF), /* $2 = 0xfffffeff */
478  MIPS64_ORI(2, 2, 0xFEFF),
479  MIPS64_AND(1, 1, 2),
480  MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
481  MIPS64_LD(2, 0, 15),
482  MIPS64_LD(1, 0, 15),
483  MIPS64_SYNC,
484  MIPS64_B(NEG16(14)),
485  MIPS64_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
486  MIPS64_NOP,
487  MIPS64_NOP,
488  MIPS64_NOP,
489  MIPS64_NOP,
490  MIPS64_NOP,
491  MIPS64_NOP,
492  MIPS64_NOP,
493  MIPS64_NOP,
494  };
495  const uint32_t *code = enable_step ? code_enable : code_disable;
496  unsigned code_len = enable_step ? ARRAY_SIZE(code_enable) :
497  ARRAY_SIZE(code_disable);
498 
499  return mips64_pracc_exec(ejtag_info,
500  code_len, code, 0, NULL, 0, NULL);
501 }
502 
503 int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
504 {
505  const uint32_t code[] = {
506  MIPS64_DRET,
507  MIPS64_NOP,
508  MIPS64_NOP,
509  MIPS64_NOP,
510  MIPS64_NOP,
511  MIPS64_NOP,
512  MIPS64_NOP,
513  MIPS64_NOP,
514  };
515  LOG_DEBUG("enter mips64_pracc_exec");
516  return mips64_pracc_exec(ejtag_info,
517  ARRAY_SIZE(code), code, 0, NULL, 0, NULL);
518 }
519 
520 int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data)
521 {
522  struct jtag_tap *tap;
523 
524  tap = ejtag_info->tap;
525  assert(tap);
526 
527  struct scan_field fields[2];
528  uint8_t spracc = 0;
529  uint8_t t[8] = {0, 0, 0, 0, 0, 0, 0, 0};
530 
531  /* fastdata 1-bit register */
532  fields[0].num_bits = 1;
533  fields[0].out_value = &spracc;
534  fields[0].in_value = NULL;
535 
536  /* processor access data register 64 bit */
537  fields[1].num_bits = 64;
538  fields[1].out_value = t;
539 
540  if (write_t) {
541  fields[1].in_value = NULL;
542  buf_set_u64(t, 0, 64, *data);
543  } else
544  fields[1].in_value = (uint8_t *) data;
545 
546  jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
547 
548  if (!write_t && data)
550  (jtag_callback_data_t) data);
551  keep_alive();
552 
553  return ERROR_OK;
554 }
static void buf_set_u64(uint8_t *_buffer, unsigned first, unsigned num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:61
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:99
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:31
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:128
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
void jtag_add_sleep(uint32_t us)
Definition: jtag/core.c:870
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
Definition: jtag/core.c:374
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
@ TAP_IDLE
Definition: jtag.h:53
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
Definition: jtag.h:337
void keep_alive(void)
Definition: log.c:415
#define ERROR_FAIL
Definition: log.h:170
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define EJTAG_QUIRK_PAD_DRET
Definition: mips32.h:208
#define MIPS32_DRET(isa)
Definition: mips32.h:770
#define MIPS32_XORI(isa, tar, src, val)
Definition: mips32.h:765
#define MIPS32_MTC0(isa, gpr, cpr, sel)
Definition: mips32.h:735
#define MIPS32_LUI(isa, reg, val)
Definition: mips32.h:732
#define MIPS32_ORI(isa, tar, src, val)
Definition: mips32.h:747
#define MIPS32_MFC0(isa, gpr, cpr, sel)
Definition: mips32.h:734
#define MIPS32_B(isa, off)
Definition: mips32.h:717
int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
void pracc_queue_free(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:339
int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf, bool check_last)
Definition: mips32_pracc.c:344
void pracc_queue_init(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:297
void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
Definition: mips32_pracc.c:307
#define LOWER16(addr)
Definition: mips32_pracc.h:32
#define UPPER16(addr)
Definition: mips32_pracc.h:31
#define NEG16(v)
Definition: mips32_pracc.h:33
#define MIPS64_MFC0(gpr, cpr, sel)
Definition: mips64.h:167
#define MIPS64_SD(reg, off, base)
Definition: mips64.h:194
#define MIPS64_LUI(reg, val)
Definition: mips64.h:183
#define MIPS64_NOP
Definition: mips64.h:157
#define MIPS64_SYNC
Definition: mips64.h:206
#define MIPS64_ORI(src, tar, val)
Definition: mips64.h:190
#define MIPS64_LD(reg, off, base)
Definition: mips64.h:185
#define MIPS64_B(off)
Definition: mips64.h:164
#define MIPS64_AND(reg, off, val)
Definition: mips64.h:161
#define MIPS64_DRET
Definition: mips64.h:200
#define MIPS64_MTC0(gpr, cpr, sel)
Definition: mips64.h:169
int mips64_pracc_exec(struct mips_ejtag *ejtag_info, unsigned code_len, const uint32_t *code, unsigned num_param_in, uint64_t *param_in, unsigned num_param_out, uint64_t *param_out)
Definition: mips64_pracc.c:211
#define MIPS64_PRACC_STACK
Definition: mips64_pracc.h:22
int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
Definition: mips_ejtag.c:150
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
Definition: mips_ejtag.c:414
int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data)
Definition: mips_ejtag.c:81
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:42
static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:212
void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
Definition: mips_ejtag.c:145
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
Definition: mips_ejtag.c:22
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:50
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
Definition: mips_ejtag.c:130
int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
Definition: mips_ejtag.c:451
void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
Definition: mips_ejtag.c:171
void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:335
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:258
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:231
static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:277
static void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
Definition: mips_ejtag.c:111
static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:312
int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data)
Definition: mips_ejtag.c:520
int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:503
void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
Definition: mips_ejtag.c:58
static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:328
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
Definition: mips_ejtag.c:186
int mips_ejtag_init(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:360
#define EJTAG_VERSION_41
Definition: mips_ejtag.h:172
#define EJTAG_V25_DBA0
Definition: mips_ejtag.h:155
#define EJTAG_V20_IMP_NODB
Definition: mips_ejtag.h:117
#define EJTAG_CTRL_PROBEN
Definition: mips_ejtag.h:57
#define EJTAG_V20_DBV_OFFS
Definition: mips_ejtag.h:145
#define EJTAG_IMP_MIPS64
Definition: mips_ejtag.h:122
#define EJTAG_INST_IDCODE
Definition: mips_ejtag.h:16
#define EJTAG_IMP_ASID6
Definition: mips_ejtag.h:107
#define EJTAG_V20_DBM_OFFS
Definition: mips_ejtag.h:144
#define EJTAG_V20_IMP_BCHANNELS_SHIFT
Definition: mips_ejtag.h:121
#define EJTAG_VERSION_20
Definition: mips_ejtag.h:168
#define EJTAG_V20_IMP_COMPLEX_BREAK
Definition: mips_ejtag.h:108
#define EJTAG_V25_IBA0
Definition: mips_ejtag.h:149
#define EJTAG_V25_DBAN_STEP
Definition: mips_ejtag.h:160
#define EJTAG_IMP_HAS(x)
Definition: mips_ejtag.h:99
#define EJTAG_V20_IBM_OFFS
Definition: mips_ejtag.h:139
#define EJTAG_INST_CONTROL
Definition: mips_ejtag.h:20
#define EJTAG_V20_DBA0
Definition: mips_ejtag.h:142
#define EJTAG_V26_IMP_R3K
Definition: mips_ejtag.h:102
#define EJTAG_V20_IMP_NOIB
Definition: mips_ejtag.h:118
#define EJTAG_DCR_MP
Definition: mips_ejtag.h:131
#define EJTAG_V20_DBC_OFFS
Definition: mips_ejtag.h:143
#define EJTAG_VERSION_31
Definition: mips_ejtag.h:171
#define EJTAG_V25_IBS
Definition: mips_ejtag.h:148
#define EJTAG_V25_DBASID_OFFS
Definition: mips_ejtag.h:157
#define EJTAG_V20_IBA0
Definition: mips_ejtag.h:137
#define EJTAG_V25_DBC_OFFS
Definition: mips_ejtag.h:158
#define EJTAG_V20_IBC_OFFS
Definition: mips_ejtag.h:138
#define EJTAG_V20_DBS
Definition: mips_ejtag.h:141
#define EJTAG_V20_IBAN_STEP
Definition: mips_ejtag.h:140
#define EJTAG_V20_IBS
Definition: mips_ejtag.h:136
#define EJTAG_V20_IMP_EADDR_NO32BIT
Definition: mips_ejtag.h:109
#define EJTAG_V25_IBASID_OFFS
Definition: mips_ejtag.h:151
#define EJTAG_V25_DBS
Definition: mips_ejtag.h:154
#define EJTAG_V20_IMP_BCHANNELS_MASK
Definition: mips_ejtag.h:120
#define EJTAG_V20_IMP_SDBBP
Definition: mips_ejtag.h:105
static void mips_le_to_h_u64(jtag_callback_data_t arg)
Definition: mips_ejtag.h:273
#define EJTAG_IMP_ASID8
Definition: mips_ejtag.h:106
#define EJTAG_CTRL_BRKST
Definition: mips_ejtag.h:49
static void mips_le_to_h_u32(jtag_callback_data_t arg)
Definition: mips_ejtag.h:267
#define EJTAG_CTRL_ROCC
Definition: mips_ejtag.h:65
#define EJTAG_V25_DBV_OFFS
Definition: mips_ejtag.h:159
#define EJTAG_VERSION_26
Definition: mips_ejtag.h:170
#define EJTAG_VERSION_25
Definition: mips_ejtag.h:169
#define EJTAG_CTRL_JTAGBRK
Definition: mips_ejtag.h:54
#define EJTAG_V25_IBM_OFFS
Definition: mips_ejtag.h:150
#define EJTAG_IMP_MIPS16
Definition: mips_ejtag.h:112
#define EJTAG_V25_IBAN_STEP
Definition: mips_ejtag.h:153
#define EJTAG_V26_IMP_DINT
Definition: mips_ejtag.h:104
#define EJTAG_V20_IMP_ICACHE_COH
Definition: mips_ejtag.h:111
#define EJTAG_V25_DBM_OFFS
Definition: mips_ejtag.h:156
#define EJTAG_VERSION_51
Definition: mips_ejtag.h:173
#define EJTAG_V25_IBC_OFFS
Definition: mips_ejtag.h:152
#define EJTAG_V20_IMP_DCACHE_COH
Definition: mips_ejtag.h:110
#define EJTAG_CTRL_PRACC
Definition: mips_ejtag.h:60
#define EJTAG_V20_IMP_NOPB
Definition: mips_ejtag.h:116
#define EJTAG_DCR
Definition: mips_ejtag.h:125
#define EJTAG_IMP_NODMA
Definition: mips_ejtag.h:113
#define EJTAG_CTRL_SETDEV
Definition: mips_ejtag.h:56
#define EJTAG_V20_DBAN_STEP
Definition: mips_ejtag.h:146
#define EJTAG_INST_IMPCODE
Definition: mips_ejtag.h:17
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
Definition: jtag.h:101
uint8_t * cur_instr
current instruction
Definition: jtag.h:132
int ir_length
size of instruction register
Definition: jtag.h:110
uint32_t cpu_quirks
Definition: mips32.h:416
struct mips_ejtag ejtag_info
Definition: mips32.h:387
uint32_t ejtag_dbm_offs
Definition: mips_ejtag.h:237
uint32_t ejtag_ctrl
Definition: mips_ejtag.h:210
uint32_t ejtag_ibm_offs
Definition: mips_ejtag.h:231
uint32_t ejtag_ibasid_offs
Definition: mips_ejtag.h:232
uint32_t idcode
Definition: mips_ejtag.h:208
uint32_t ejtag_dbasid_offs
Definition: mips_ejtag.h:239
unsigned int ejtag_version
Definition: mips_ejtag.h:221
uint32_t impcode
Definition: mips_ejtag.h:207
uint32_t ejtag_iba0_addr
Definition: mips_ejtag.h:229
uint32_t ejtag_ibc_offs
Definition: mips_ejtag.h:230
uint32_t ejtag_iba_step_size
Definition: mips_ejtag.h:241
struct jtag_tap * tap
Definition: mips_ejtag.h:206
uint32_t ejtag_dba_step_size
Definition: mips_ejtag.h:242
uint32_t reg8
Definition: mips_ejtag.h:215
uint32_t ejtag_dbv_offs
Definition: mips_ejtag.h:238
uint32_t ejtag_ibs_addr
Definition: mips_ejtag.h:228
int fast_access_save
Definition: mips_ejtag.h:211
uint32_t ejtag_dbc_offs
Definition: mips_ejtag.h:236
uint32_t ejtag_dbs_addr
Definition: mips_ejtag.h:234
uint32_t ejtag_dba0_addr
Definition: mips_ejtag.h:235
uint32_t isa
Definition: mips_ejtag.h:222
uint32_t instr
Definition: mips32_pracc.h:42
struct pa_list * pracc_list
Definition: mips32_pracc.h:53
struct mips_ejtag * ejtag_info
Definition: mips32_pracc.h:47
This structure defines a single scan field in the scan.
Definition: jtag.h:87
int num_bits
The number of bits this field specifies.
Definition: jtag.h:89
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:93
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:91
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
#define NULL
Definition: usb.h:16