Include dependency graph for mips32_pracc.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	pa_list

struct	pracc_queue_info

Macros
#define	LOWER16(addr) ((addr) & 0xFFFF)

#define	MIPS32_FASTDATA_HANDLER_SIZE 0x80

#define	MIPS32_PRACC_BASE_ADDR 0xFF200000

#define	MIPS32_PRACC_FASTDATA_AREA 0xFF200000

#define	MIPS32_PRACC_FASTDATA_SIZE 16

#define	MIPS32_PRACC_PARAM_OUT 0xFF202000

#define	MIPS32_PRACC_TEXT 0xFF200200

#define	NEG16(v) (((~(v)) + 1) & 0xFFFF)

#define	PRACC_BLOCK 128 /* 1 Kbyte */

#define	PRACC_MAX_CODE (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT)

#define	PRACC_MAX_INSTRUCTIONS (PRACC_MAX_CODE / 4)

#define	PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)

#define	PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)

#define	SWAP16(v) ((LOWER16(v) << 16) \| (UPPER16(v)))

#define	UPPER16(addr) ((addr) >> 16)

Functions
int	mips32_cp0_read (struct mips_ejtag ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
	mips32_cp0_read More...

int	mips32_cp0_write (struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
	mips32_cp0_write More...

int	mips32_cp1_control_read (struct mips_ejtag ejtag_info, uint32_t val, uint32_t cp1_c_reg)
	mips32_cp1_control_read More...

int	mips32_pracc_fastdata_xfer (struct mips_ejtag ejtag_info, struct working_area source, int write_t, uint32_t addr, int count, uint32_t *buf)

int	mips32_pracc_queue_exec (struct mips_ejtag ejtag_info, struct pracc_queue_info ctx, uint32_t *buf, bool check_last)

int	mips32_pracc_read_mem (struct mips_ejtag ejtag_info, uint32_t addr, int size, int count, void buf)

int	mips32_pracc_read_regs (struct mips32_common *mips32)

int	mips32_pracc_write_mem (struct mips_ejtag ejtag_info, uint32_t addr, int size, int count, const void buf)

int	mips32_pracc_write_regs (struct mips32_common *mips32)

void	pracc_add (struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)

void	pracc_queue_free (struct pracc_queue_info *ctx)

void	pracc_queue_init (struct pracc_queue_info *ctx)

static void	pracc_swap16_array (struct mips_ejtag ejtag_info, uint32_t buf, int count)

Macro Definition Documentation

◆ LOWER16

#define LOWER16 ( addr ) ((addr) & 0xFFFF)

Definition at line 32 of file mips32_pracc.h.

◆ MIPS32_FASTDATA_HANDLER_SIZE

#define MIPS32_FASTDATA_HANDLER_SIZE 0x80

Definition at line 30 of file mips32_pracc.h.

◆ MIPS32_PRACC_BASE_ADDR

#define MIPS32_PRACC_BASE_ADDR 0xFF200000

Definition at line 21 of file mips32_pracc.h.

◆ MIPS32_PRACC_FASTDATA_AREA

#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000

Definition at line 19 of file mips32_pracc.h.

◆ MIPS32_PRACC_FASTDATA_SIZE

#define MIPS32_PRACC_FASTDATA_SIZE 16

Definition at line 20 of file mips32_pracc.h.

◆ MIPS32_PRACC_PARAM_OUT

#define MIPS32_PRACC_PARAM_OUT 0xFF202000

Definition at line 23 of file mips32_pracc.h.

◆ MIPS32_PRACC_TEXT

#define MIPS32_PRACC_TEXT 0xFF200200

Definition at line 22 of file mips32_pracc.h.

◆ NEG16

#define NEG16 ( v ) (((~(v)) + 1) & 0xFFFF)

Definition at line 33 of file mips32_pracc.h.

◆ PRACC_BLOCK

#define PRACC_BLOCK 128 /* 1 Kbyte */

Definition at line 37 of file mips32_pracc.h.

◆ PRACC_MAX_CODE

#define PRACC_MAX_CODE (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT)

Definition at line 26 of file mips32_pracc.h.

◆ PRACC_MAX_INSTRUCTIONS

#define PRACC_MAX_INSTRUCTIONS (PRACC_MAX_CODE / 4)

Definition at line 27 of file mips32_pracc.h.

◆ PRACC_OUT_OFFSET

#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)

Definition at line 28 of file mips32_pracc.h.

◆ PRACC_UPPER_BASE_ADDR

#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)

Definition at line 25 of file mips32_pracc.h.

◆ SWAP16

#define SWAP16 ( v ) ((LOWER16(v) << 16) | (UPPER16(v)))

Definition at line 34 of file mips32_pracc.h.

◆ UPPER16

#define UPPER16 ( addr ) ((addr) >> 16)

Definition at line 31 of file mips32_pracc.h.

Function Documentation

◆ mips32_cp0_read()

int mips32_cp0_read	(	struct mips_ejtag *	ejtag_info,
		uint32_t *	val,
		uint32_t	cp0_reg,
		uint32_t	cp0_sel
	)

mips32_cp0_read

Simulates mfc0 ASM instruction (Move From C0), i.e. implements copro C0 Register read.

Parameters

[in]	ejtag_info
[in]	val	Storage to hold read value
[in]	cp0_reg	Number of copro C0 register we want to read
[in]	cp0_sel	Select for the given C0 register

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 552 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, mips32_cpu_support_hazard_barrier(), MIPS32_EHB, MIPS32_LUI, MIPS32_MFC0, MIPS32_ORI, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, NEG16, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by COMMAND_HANDLER(), mips32_cp0_get_all_regs(), mips32_cp0_get_reg_by_name(), mips32_cp0_get_reg_by_number(), mips32_pracc_fastdata_xfer_synchronize_cache(), mips32_pracc_synchronize_cache(), mips32_pracc_write_mem(), mips32_read_c0_prid(), mips32_read_config_fpu(), mips32_read_config_mmu(), and mips32_read_config_regs().

◆ mips32_cp0_write()

int mips32_cp0_write	(	struct mips_ejtag *	ejtag_info,
		uint32_t	val,
		uint32_t	cp0_reg,
		uint32_t	cp0_sel
	)

mips32_cp0_write

Simulates mtc0 ASM instruction (Move To C0), i.e. implements copro C0 Register read.

Parameters

[in]	ejtag_info
[in]	val	Value to be written
[in]	cp0_reg	Number of copro C0 register we want to write to
[in]	cp0_sel	Select for the given C0 register

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 573 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, MIPS32_B, mips32_cpu_support_hazard_barrier(), MIPS32_EHB, MIPS32_MFC0, MIPS32_MTC0, mips32_pracc_queue_exec(), NEG16, NULL, pracc_add(), pracc_add_li32(), pracc_queue_free(), pracc_queue_init(), and pracc_queue_info::retval.

Referenced by COMMAND_HANDLER(), mips32_cp0_set_reg_by_name(), and mips32_cp0_set_reg_by_number().

◆ mips32_cp1_control_read()

int mips32_cp1_control_read	(	struct mips_ejtag *	ejtag_info,
		uint32_t *	val,
		uint32_t	cp1_c_reg
	)

mips32_cp1_control_read

Simulates cfc1 ASM instruction (Move Control Word From Floating Point), i.e. implements copro C1 Control Register read.

Parameters

[in]	ejtag_info
[in]	val	Storage to hold read value
[in]	cp1_c_reg	Number of copro C1 control register we want to read

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 591 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, MIPS32_CFC1, MIPS32_EHB, MIPS32_LUI, MIPS32_MFC0, MIPS32_ORI, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, NEG16, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by mips32_read_config_fpu().

◆ mips32_pracc_fastdata_xfer()

int mips32_pracc_fastdata_xfer	(	struct mips_ejtag *	ejtag_info,
		struct working_area *	source,
		int	write_t,
		uint32_t	addr,
		int	count,
		uint32_t *	buf
	)

Definition at line 1226 of file mips32_pracc.c.

References adapter_get_speed_khz(), addr, ARRAY_SIZE, count, EJTAG_INST_DATA, EJTAG_INST_FASTDATA, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, mips_ejtag::fast_access_save, mips_ejtag::isa, jtag_add_clocks(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, LOWER16, MIPS32_ADDI, MIPS32_BNE, mips32_cpu_support_hazard_barrier(), mips32_cpu_support_sync(), MIPS32_FASTDATA_HANDLER_SIZE, MIPS32_JR, MIPS32_JRHB, MIPS32_LUI, MIPS32_LW, MIPS32_MFC0, MIPS32_NOP, MIPS32_ORI, MIPS32_PRACC_FASTDATA_AREA, mips32_pracc_fastdata_xfer_synchronize_cache(), mips32_pracc_finish(), mips32_pracc_read_ctrl_addr(), MIPS32_PRACC_TEXT, mips32_pracc_write_mem(), MIPS32_SW, MIPS32_SYNC, MIPS32_XORI, mips_ejtag_drscan_32_out(), mips_ejtag_fastdata_scan(), mips_ejtag_set_instr(), mips_ejtag::mode, NEG16, mips_ejtag::pa_addr, pracc_swap16_array(), mips_ejtag::scan_delay, source, TARGET_PRIxADDR, UPPER16, and wait_for_pracc_rw().

Referenced by mips_m4k_bulk_read_memory(), and mips_m4k_bulk_write_memory().

◆ mips32_pracc_queue_exec()

int mips32_pracc_queue_exec	(	struct mips_ejtag *	ejtag_info,
		struct pracc_queue_info *	ctx,
		uint32_t *	buf,
		bool	check_last
	)

Definition at line 344 of file mips32_pracc.c.

References adapter_get_speed_khz(), addr, pa_list::addr, buf_get_u32(), pracc_queue_info::code_count, ctrl, mips_ejtag::ejtag_ctrl, EJTAG_CTRL_PRACC, EJTAG_CTRL_PRNW, EJTAG_INST_ALL, mips_ejtag::endianness, ERROR_FAIL, ERROR_OK, pa_list::instr, mips_ejtag::isa, jtag_add_clocks(), jtag_execute_queue(), LOG_ERROR, mips32_pracc_exec(), MIPS32_PRACC_PARAM_OUT, MIPS32_PRACC_TEXT, mips_ejtag_add_scan_96(), mips_ejtag_set_instr(), mips_ejtag::mode, pracc_queue_info::pracc_list, pracc_queue_info::retval, mips_ejtag::scan_delay, pracc_queue_info::store_count, and SWAP16.

Referenced by ath79_spi_bitbang_chunk(), mips32_cp0_read(), mips32_cp0_write(), mips32_cp1_control_read(), mips32_pracc_read_dsp_reg(), mips32_pracc_read_mem(), mips32_pracc_read_regs(), mips32_pracc_read_u32(), mips32_pracc_synchronize_cache(), mips32_pracc_write_dsp_reg(), mips32_pracc_write_mem(), mips32_pracc_write_mem_generic(), mips32_pracc_write_regs(), mips_ejtag_config_step(), and mips_ejtag_exit_debug().

◆ mips32_pracc_read_mem()

int mips32_pracc_read_mem	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		int	size,
		int	count,
		void *	buf
	)

◆ mips32_pracc_read_regs()

int mips32_pracc_read_regs ( struct mips32_common * mips32 )

◆ mips32_pracc_write_mem()

int mips32_pracc_write_mem	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		int	size,
		int	count,
		const void *	buf
	)

If we are in the cacheable region and cache is activated, we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write, so that changes do not continue to live only in D$ (if CCA = 3), but to be replicated in I$ also (maybe we wrote the instructions)

Check cacheability bits coherency algorithm is the region cacheable or uncached. If cacheable we have to synchronize the cache

Definition at line 800 of file mips32_pracc.c.

References addr, pracc_queue_info::code_count, count, pracc_queue_info::ejtag_info, ERROR_FAIL, ERROR_OK, pracc_queue_info::isa, KSEG0, KSEG1, KSEG2, KSEG3, KSEGX, KUSEG, LOG_DEBUG, LOG_ERROR, MIPS32_B, MIPS32_CONFIG0_AR_MASK, MIPS32_CONFIG0_AR_SHIFT, MIPS32_CONFIG0_K0_MASK, MIPS32_CONFIG0_K0_SHIFT, MIPS32_CONFIG0_K23_MASK, MIPS32_CONFIG0_K23_SHIFT, MIPS32_CONFIG0_KU_MASK, MIPS32_CONFIG0_KU_SHIFT, mips32_cp0_read(), mips32_cpu_support_hazard_barrier(), mips32_cpu_support_sync(), MIPS32_EHB, MIPS32_NOP, mips32_pracc_queue_exec(), mips32_pracc_synchronize_cache(), mips32_pracc_write_mem_generic(), MIPS32_RELEASE_2, MIPS32_SYNC, NEG16, NULL, pracc_add(), pracc_queue_free(), pracc_queue_init(), pracc_queue_info::retval, and size.