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mips32_pracc.c File Reference
Include dependency graph for mips32_pracc.c:

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Functions

int mips32_cp0_read (struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
 mips32_cp0_read More...
 
int mips32_cp0_write (struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
 mips32_cp0_write More...
 
int mips32_cp1_control_read (struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp1_c_reg)
 mips32_cp1_control_read More...
 
static int mips32_pracc_clean_text_jump (struct mips_ejtag *ejtag_info)
 
static int mips32_pracc_exec (struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out, bool check_last)
 
int mips32_pracc_fastdata_xfer (struct mips_ejtag *ejtag_info, struct working_area *source, int write_t, uint32_t addr, int count, uint32_t *buf)
 
static int mips32_pracc_fastdata_xfer_synchronize_cache (struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count)
 mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer More...
 
static void mips32_pracc_finish (struct mips_ejtag *ejtag_info)
 
int mips32_pracc_queue_exec (struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf, bool check_last)
 
static int mips32_pracc_read_ctrl_addr (struct mips_ejtag *ejtag_info)
 
int mips32_pracc_read_mem (struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
 
int mips32_pracc_read_regs (struct mips32_common *mips32)
 
static int mips32_pracc_read_u32 (struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
 
static void mips32_pracc_store_regs (struct pracc_queue_info *ctx, unsigned int offset_gpr, unsigned int offset_cp0)
 
static void mips32_pracc_store_regs_cp0_context (struct pracc_queue_info *ctx, unsigned int offset_cp0)
 
static void mips32_pracc_store_regs_gpr (struct pracc_queue_info *ctx, unsigned int offset_gpr)
 
static void mips32_pracc_store_regs_lohi (struct pracc_queue_info *ctx)
 
static void mips32_pracc_store_regs_restore (struct pracc_queue_info *ctx)
 
static void mips32_pracc_store_regs_set_base_addr (struct pracc_queue_info *ctx)
 
static int mips32_pracc_synchronize_cache (struct mips_ejtag *ejtag_info, uint32_t start_addr, uint32_t end_addr, int cached, int rel)
 mips32_pracc_sync_cache More...
 
int mips32_pracc_write_mem (struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
 
static int mips32_pracc_write_mem_generic (struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
 
int mips32_pracc_write_regs (struct mips32_common *mips32)
 
void pracc_add (struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
 
static void pracc_add_li32 (struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize)
 
void pracc_queue_free (struct pracc_queue_info *ctx)
 
void pracc_queue_init (struct pracc_queue_info *ctx)
 
static int wait_for_pracc_rw (struct mips_ejtag *ejtag_info)
 

Function Documentation

◆ mips32_cp0_read()

int mips32_cp0_read ( struct mips_ejtag ejtag_info,
uint32_t *  val,
uint32_t  cp0_reg,
uint32_t  cp0_sel 
)

◆ mips32_cp0_write()

int mips32_cp0_write ( struct mips_ejtag ejtag_info,
uint32_t  val,
uint32_t  cp0_reg,
uint32_t  cp0_sel 
)

mips32_cp0_write

Simulates mtc0 ASM instruction (Move To C0), i.e. implements copro C0 Register read.

Parameters
[in]ejtag_info
[in]valValue to be written
[in]cp0_regNumber of copro C0 register we want to write to
[in]cp0_selSelect for the given C0 register
Returns
ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 573 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, MIPS32_B, mips32_cpu_support_hazard_barrier(), MIPS32_EHB, MIPS32_MFC0, MIPS32_MTC0, mips32_pracc_queue_exec(), NEG16, NULL, pracc_add(), pracc_add_li32(), pracc_queue_free(), pracc_queue_init(), and pracc_queue_info::retval.

Referenced by COMMAND_HANDLER(), mips32_cp0_set_reg_by_name(), and mips32_cp0_set_reg_by_number().

◆ mips32_cp1_control_read()

int mips32_cp1_control_read ( struct mips_ejtag ejtag_info,
uint32_t *  val,
uint32_t  cp1_c_reg 
)

mips32_cp1_control_read

Simulates cfc1 ASM instruction (Move Control Word From Floating Point), i.e. implements copro C1 Control Register read.

Parameters
[in]ejtag_info
[in]valStorage to hold read value
[in]cp1_c_regNumber of copro C1 control register we want to read
Returns
ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 591 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, MIPS32_CFC1, MIPS32_EHB, MIPS32_LUI, MIPS32_MFC0, MIPS32_ORI, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, NEG16, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by mips32_read_config_fpu().

◆ mips32_pracc_clean_text_jump()

◆ mips32_pracc_exec()

◆ mips32_pracc_fastdata_xfer()

◆ mips32_pracc_fastdata_xfer_synchronize_cache()

static int mips32_pracc_fastdata_xfer_synchronize_cache ( struct mips_ejtag ejtag_info,
uint32_t  addr,
int  size,
int  count 
)
static

mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer

Parameters
[in]ejtag_infoEJTAG information structure
[in]addrStarting address for cache synchronization
[in]sizeSize of each data element
[in]countNumber of data elements

Synchronizes the cache for fast data transfer based on the specified address and cache configuration. If the region is cacheable (write-back cache or write-through cache), it synchronizes the cache for the specified range. The synchronization is performed using the MIPS32 cache synchronization function.

Returns
ERROR_OK on success; error code on failure.

Check cacheability bits coherency algorithm is the region cacheable or uncached. If cacheable we have to synchronize the cache

Definition at line 1170 of file mips32_pracc.c.

References addr, count, ERROR_FAIL, ERROR_OK, KSEG0, KSEG1, KSEG2, KSEG3, KSEGX, KUSEG, LOG_DEBUG, MIPS32_CONFIG0_AR_MASK, MIPS32_CONFIG0_AR_SHIFT, MIPS32_CONFIG0_K0_MASK, MIPS32_CONFIG0_K0_SHIFT, MIPS32_CONFIG0_K23_MASK, MIPS32_CONFIG0_K23_SHIFT, MIPS32_CONFIG0_KU_MASK, MIPS32_CONFIG0_KU_SHIFT, mips32_cp0_read(), mips32_pracc_synchronize_cache(), MIPS32_RELEASE_2, and size.

Referenced by mips32_pracc_fastdata_xfer().

◆ mips32_pracc_finish()

static void mips32_pracc_finish ( struct mips_ejtag ejtag_info)
static

◆ mips32_pracc_queue_exec()

◆ mips32_pracc_read_ctrl_addr()

static int mips32_pracc_read_ctrl_addr ( struct mips_ejtag ejtag_info)
static

◆ mips32_pracc_read_mem()

◆ mips32_pracc_read_regs()

◆ mips32_pracc_read_u32()

◆ mips32_pracc_store_regs()

static void mips32_pracc_store_regs ( struct pracc_queue_info ctx,
unsigned int  offset_gpr,
unsigned int  offset_cp0 
)
static

◆ mips32_pracc_store_regs_cp0_context()

static void mips32_pracc_store_regs_cp0_context ( struct pracc_queue_info ctx,
unsigned int  offset_cp0 
)
static

◆ mips32_pracc_store_regs_gpr()

static void mips32_pracc_store_regs_gpr ( struct pracc_queue_info ctx,
unsigned int  offset_gpr 
)
static

◆ mips32_pracc_store_regs_lohi()

static void mips32_pracc_store_regs_lohi ( struct pracc_queue_info ctx)
static

◆ mips32_pracc_store_regs_restore()

static void mips32_pracc_store_regs_restore ( struct pracc_queue_info ctx)
static

◆ mips32_pracc_store_regs_set_base_addr()

static void mips32_pracc_store_regs_set_base_addr ( struct pracc_queue_info ctx)
static

◆ mips32_pracc_synchronize_cache()

static int mips32_pracc_synchronize_cache ( struct mips_ejtag ejtag_info,
uint32_t  start_addr,
uint32_t  end_addr,
int  cached,
int  rel 
)
static

mips32_pracc_sync_cache

Synchronize Caches to Make Instruction Writes Effective (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, Document Number: MD00086, Revision 2.00, June 9, 2003)

When the instruction stream is written, the SYNCI instruction should be used in conjunction with other instructions to make the newly-written instructions effective.

Explanation : A program that loads another program into memory is actually writing the D- side cache. The instructions it has loaded can't be executed until they reach the I-cache.

After the instructions have been written, the loader should arrange to write back any containing D-cache line and invalidate any locations already in the I-cache.

If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need to write back.

In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, which does the whole job for a cache-line-sized chunk of the memory you just loaded: That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate.

The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.

Find cache line size in bytes

Definition at line 638 of file mips32_pracc.c.

References pracc_queue_info::code_count, count, pracc_queue_info::ejtag_info, ERROR_FAIL, ERROR_OK, IS_PWR_OF_2, pracc_queue_info::isa, LOG_DEBUG, LOWER16, MIPS32_B, MIPS32_CACHE, MIPS32_CACHE_D_HIT_WRITEBACK, MIPS32_CACHE_I_HIT_INVALIDATE, MIPS32_CONFIG1_DL_MASK, MIPS32_CONFIG1_DL_SHIFT, mips32_cp0_read(), MIPS32_LUI, MIPS32_MFC0, MIPS32_NOP, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_RDHWR, MIPS32_SW, MIPS32_SYNC, MIPS32_SYNCI, MIPS32_SYNCI_STEP, NEG16, NULL, pracc_add(), pracc_add_li32(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, pracc_queue_info::store_count, and UPPER16.

Referenced by mips32_pracc_fastdata_xfer_synchronize_cache(), and mips32_pracc_write_mem().

◆ mips32_pracc_write_mem()

int mips32_pracc_write_mem ( struct mips_ejtag ejtag_info,
uint32_t  addr,
int  size,
int  count,
const void *  buf 
)

If we are in the cacheable region and cache is activated, we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write, so that changes do not continue to live only in D$ (if CCA = 3), but to be replicated in I$ also (maybe we wrote the instructions)

Check cacheability bits coherency algorithm is the region cacheable or uncached. If cacheable we have to synchronize the cache

Definition at line 800 of file mips32_pracc.c.

References addr, pracc_queue_info::code_count, count, pracc_queue_info::ejtag_info, ERROR_FAIL, ERROR_OK, pracc_queue_info::isa, KSEG0, KSEG1, KSEG2, KSEG3, KSEGX, KUSEG, LOG_DEBUG, LOG_ERROR, MIPS32_B, MIPS32_CONFIG0_AR_MASK, MIPS32_CONFIG0_AR_SHIFT, MIPS32_CONFIG0_K0_MASK, MIPS32_CONFIG0_K0_SHIFT, MIPS32_CONFIG0_K23_MASK, MIPS32_CONFIG0_K23_SHIFT, MIPS32_CONFIG0_KU_MASK, MIPS32_CONFIG0_KU_SHIFT, mips32_cp0_read(), mips32_cpu_support_hazard_barrier(), mips32_cpu_support_sync(), MIPS32_EHB, MIPS32_NOP, mips32_pracc_queue_exec(), mips32_pracc_synchronize_cache(), mips32_pracc_write_mem_generic(), MIPS32_RELEASE_2, MIPS32_SYNC, NEG16, NULL, pracc_add(), pracc_queue_free(), pracc_queue_init(), pracc_queue_info::retval, and size.

Referenced by mips32_pracc_fastdata_xfer(), and mips_m4k_write_memory().

◆ mips32_pracc_write_mem_generic()

◆ mips32_pracc_write_regs()

◆ pracc_add()

◆ pracc_add_li32()

static void pracc_add_li32 ( struct pracc_queue_info ctx,
uint32_t  reg_num,
uint32_t  data,
bool  optimize 
)
static

◆ pracc_queue_free()

◆ pracc_queue_init()

◆ wait_for_pracc_rw()