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lpc32xx.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2007 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com> *
8  * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
9  * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
10  * *
11  * Based on a combination of the lpc3180 driver and code from *
12  * uboot-2009.03-lpc32xx by Kevin Wells. *
13  * Any bugs are mine. --BSt *
14  ***************************************************************************/
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "imp.h"
21 #include "lpc32xx.h"
22 #include <target/target.h>
23 
24 static int lpc32xx_reset(struct nand_device *nand);
25 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
26 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
27 
28 /* These are offset with the working area in IRAM when using DMA to
29  * read/write data to the SLC controller.
30  * - DMA descriptors will be put at start of working area,
31  * - Hardware generated ECC will be stored at ECC_OFFS
32  * - OOB will be read/written from/to SPARE_OFFS
33  * - Actual page data will be read from/to DATA_OFFS
34  * There are unused holes between the used areas.
35  */
36 #define ECC_OFFS 0x120
37 #define SPARE_OFFS 0x140
38 #define DATA_OFFS 0x200
39 
40 static const int sp_ooblayout[] = {
41  10, 11, 12, 13, 14, 15
42 };
43 static const int lp_ooblayout[] = {
44  40, 41, 42, 43, 44, 45,
45  46, 47, 48, 49, 50, 51,
46  52, 53, 54, 55, 56, 57,
47  58, 59, 60, 61, 62, 63
48 };
49 
50 struct dmac_ll {
51  volatile uint32_t dma_src;
52  volatile uint32_t dma_dest;
53  volatile uint32_t next_lli;
54  volatile uint32_t next_ctrl;
55 };
56 
57 static struct dmac_ll dmalist[(2048/256) * 2 + 1];
58 
59 /* nand device lpc32xx <target#> <oscillator_frequency>
60  */
61 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
62 {
63  if (CMD_ARGC < 3)
65 
66  uint32_t osc_freq;
67  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
68 
69  struct lpc32xx_nand_controller *lpc32xx_info;
70  lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
71  nand->controller_priv = lpc32xx_info;
72 
73  lpc32xx_info->osc_freq = osc_freq;
74 
75  if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
76  LOG_WARNING("LPC32xx oscillator frequency should be between "
77  "1000 and 20000 kHz, was %i",
78  lpc32xx_info->osc_freq);
79 
81  lpc32xx_info->sw_write_protection = 0;
82  lpc32xx_info->sw_wp_lower_bound = 0x0;
83  lpc32xx_info->sw_wp_upper_bound = 0x0;
84 
85  return ERROR_OK;
86 }
87 
88 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
89 {
90  int bypass = (pll_ctrl & 0x8000) >> 15;
91  int direct = (pll_ctrl & 0x4000) >> 14;
92  int feedback = (pll_ctrl & 0x2000) >> 13;
93  int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
94  int n = ((pll_ctrl & 0x0600) >> 9) + 1;
95  int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
96  int lock = (pll_ctrl & 0x1);
97 
98  if (!lock)
99  LOG_WARNING("PLL is not locked");
100 
101  if (!bypass && direct) /* direct mode */
102  return (m * fclkin) / n;
103 
104  if (bypass && !direct) /* bypass mode */
105  return fclkin / (2 * p);
106 
107  if (bypass & direct) /* direct bypass mode */
108  return fclkin;
109 
110  if (feedback) /* integer mode */
111  return m * (fclkin / n);
112  else /* non-integer mode */
113  return (m / (2 * p)) * (fclkin / n);
114 }
115 
116 static float lpc32xx_cycle_time(struct nand_device *nand)
117 {
118  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
119  struct target *target = nand->target;
120  uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
121  int sysclk;
122  int hclk;
123  int hclk_pll;
124  float cycle;
125  int retval;
126 
127  /* calculate timings */
128 
129  /* determine current SYSCLK (13'MHz or main oscillator) */
130  retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
131  if (retval != ERROR_OK) {
132  LOG_ERROR("could not read SYSCLK_CTRL");
134  }
135 
136  if ((sysclk_ctrl & 1) == 0)
137  sysclk = lpc32xx_info->osc_freq;
138  else
139  sysclk = 13000;
140 
141  /* determine selected HCLK source */
142  retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
143  if (retval != ERROR_OK) {
144  LOG_ERROR("could not read HCLK_CTRL");
146  }
147 
148  if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
149  hclk = sysclk;
150  else {
151  retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
152  if (retval != ERROR_OK) {
153  LOG_ERROR("could not read HCLKPLL_CTRL");
155  }
156  hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
157 
158  retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
159  if (retval != ERROR_OK) {
160  LOG_ERROR("could not read CLKDIV_CTRL");
162  }
163 
164  if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
165  hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
166  else /* HCLK uses HCLK_PLL */
167  hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
168  }
169 
170  LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
171 
172  cycle = (1.0 / hclk) * 1000000.0;
173 
174  return cycle;
175 }
176 
177 static int lpc32xx_init(struct nand_device *nand)
178 {
179  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
180  struct target *target = nand->target;
181  int bus_width = nand->bus_width ? nand->bus_width : 8;
182  int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
183  int page_size = nand->page_size ? nand->page_size : 512;
184  int retval;
185 
186  if (target->state != TARGET_HALTED) {
187  LOG_ERROR("target must be halted to use LPC32xx "
188  "NAND flash controller");
190  }
191 
192  /* sanitize arguments */
193  if (bus_width != 8) {
194  LOG_ERROR("LPC32xx doesn't support %i", bus_width);
196  }
197 
198  /* inform calling code about selected bus width */
199  nand->bus_width = bus_width;
200 
201  if ((address_cycles < 3) || (address_cycles > 5)) {
202  LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
204  }
205 
206  if ((page_size != 512) && (page_size != 2048)) {
207  LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
209  }
210 
211  /* select MLC controller if none is currently selected */
212  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
213  LOG_DEBUG("no LPC32xx NAND flash controller selected, "
214  "using default 'slc'");
216  }
217 
218  if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
219  uint32_t mlc_icr_value = 0x0;
220  float cycle;
221  int twp, twh, trp, treh, trhz, trbwb, tcea;
222 
223  /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
224  retval = target_write_u32(target, 0x400040c8, 0x22);
225  if (retval != ERROR_OK) {
226  LOG_ERROR("could not set FLASHCLK_CTRL");
228  }
229 
230  /* MLC_CEH = 0x0 (Force nCE assert) */
231  retval = target_write_u32(target, 0x200b804c, 0x0);
232  if (retval != ERROR_OK) {
233  LOG_ERROR("could not set MLC_CEH");
235  }
236 
237  /* MLC_LOCK = 0xa25e (unlock protected registers) */
238  retval = target_write_u32(target, 0x200b8044, 0xa25e);
239  if (retval != ERROR_OK) {
240  LOG_ERROR("could not set MLC_LOCK");
242  }
243 
244  /* MLC_ICR = configuration */
245  if (lpc32xx_info->sw_write_protection)
246  mlc_icr_value |= 0x8;
247  if (page_size == 2048)
248  mlc_icr_value |= 0x4;
249  if (address_cycles == 4)
250  mlc_icr_value |= 0x2;
251  if (bus_width == 16)
252  mlc_icr_value |= 0x1;
253  retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
254  if (retval != ERROR_OK) {
255  LOG_ERROR("could not set MLC_ICR");
257  }
258 
259  /* calculate NAND controller timings */
260  cycle = lpc32xx_cycle_time(nand);
261 
262  twp = ((40 / cycle) + 1);
263  twh = ((20 / cycle) + 1);
264  trp = ((30 / cycle) + 1);
265  treh = ((15 / cycle) + 1);
266  trhz = ((30 / cycle) + 1);
267  trbwb = ((100 / cycle) + 1);
268  tcea = ((45 / cycle) + 1);
269 
270  /* MLC_LOCK = 0xa25e (unlock protected registers) */
271  retval = target_write_u32(target, 0x200b8044, 0xa25e);
272  if (retval != ERROR_OK) {
273  LOG_ERROR("could not set MLC_LOCK");
275  }
276 
277  /* MLC_TIME_REG */
278  retval = target_write_u32(target, 0x200b8034,
279  (twp & 0xf)
280  | ((twh & 0xf) << 4)
281  | ((trp & 0xf) << 8)
282  | ((treh & 0xf) << 12)
283  | ((trhz & 0x7) << 16)
284  | ((trbwb & 0x1f) << 19)
285  | ((tcea & 0x3) << 24));
286  if (retval != ERROR_OK) {
287  LOG_ERROR("could not set MLC_TIME_REG");
289  }
290 
291  retval = lpc32xx_reset(nand);
292  if (retval != ERROR_OK)
294  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
295  float cycle;
296  int r_setup, r_hold, r_width, r_rdy;
297  int w_setup, w_hold, w_width, w_rdy;
298 
299  /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
300  retval = target_write_u32(target, 0x400040c8, 0x05);
301  if (retval != ERROR_OK) {
302  LOG_ERROR("could not set FLASHCLK_CTRL");
304  }
305 
306  /* after reset set other registers of SLC,
307  * so reset calling is here at the beginning
308  */
309  retval = lpc32xx_reset(nand);
310  if (retval != ERROR_OK)
312 
313  /* SLC_CFG =
314  Force nCE assert,
315  DMA ECC enabled,
316  ECC enabled,
317  DMA burst enabled,
318  DMA read from SLC,
319  WIDTH = bus_width)
320  */
321  retval = target_write_u32(target, 0x20020014,
322  0x3e | ((bus_width == 16) ? 1 : 0));
323  if (retval != ERROR_OK) {
324  LOG_ERROR("could not set SLC_CFG");
326  }
327 
328  /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
329  retval = target_write_u32(target, 0x20020020, 0x03);
330  if (retval != ERROR_OK) {
331  LOG_ERROR("could not set SLC_IEN");
333  }
334 
335  /* DMA configuration */
336 
337  /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
338  retval = target_write_u32(target, 0x400040e8, 0x01);
339  if (retval != ERROR_OK) {
340  LOG_ERROR("could not set DMACLK_CTRL");
342  }
343 
344  /* DMACConfig = DMA enabled*/
345  retval = target_write_u32(target, 0x31000030, 0x01);
346  if (retval != ERROR_OK) {
347  LOG_ERROR("could not set DMACConfig");
349  }
350 
351  /* calculate NAND controller timings */
352  cycle = lpc32xx_cycle_time(nand);
353 
354  r_setup = w_setup = 0;
355  r_hold = w_hold = 10 / cycle;
356  r_width = 30 / cycle;
357  w_width = 40 / cycle;
358  r_rdy = w_rdy = 100 / cycle;
359 
360  /* SLC_TAC: SLC timing arcs register */
361  retval = target_write_u32(target, 0x2002002c,
362  (r_setup & 0xf)
363  | ((r_hold & 0xf) << 4)
364  | ((r_width & 0xf) << 8)
365  | ((r_rdy & 0xf) << 12)
366  | ((w_setup & 0xf) << 16)
367  | ((w_hold & 0xf) << 20)
368  | ((w_width & 0xf) << 24)
369  | ((w_rdy & 0xf) << 28));
370  if (retval != ERROR_OK) {
371  LOG_ERROR("could not set SLC_TAC");
373  }
374  }
375 
376  return ERROR_OK;
377 }
378 
379 static int lpc32xx_reset(struct nand_device *nand)
380 {
381  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
382  struct target *target = nand->target;
383  int retval;
384 
385  if (target->state != TARGET_HALTED) {
386  LOG_ERROR("target must be halted to use "
387  "LPC32xx NAND flash controller");
389  }
390 
391  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
392  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
394  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
395  /* MLC_CMD = 0xff (reset controller and NAND device) */
396  retval = target_write_u32(target, 0x200b8000, 0xff);
397  if (retval != ERROR_OK) {
398  LOG_ERROR("could not set MLC_CMD");
400  }
401 
402  if (!lpc32xx_controller_ready(nand, 100)) {
403  LOG_ERROR("LPC32xx MLC NAND controller timed out "
404  "after reset");
406  }
407  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
408  /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
409  retval = target_write_u32(target, 0x20020010, 0x6);
410  if (retval != ERROR_OK) {
411  LOG_ERROR("could not set SLC_CTRL");
413  }
414 
415  if (!lpc32xx_controller_ready(nand, 100)) {
416  LOG_ERROR("LPC32xx SLC NAND controller timed out "
417  "after reset");
419  }
420  }
421 
422  return ERROR_OK;
423 }
424 
425 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
426 {
427  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
428  struct target *target = nand->target;
429  int retval;
430 
431  if (target->state != TARGET_HALTED) {
432  LOG_ERROR("target must be halted to use "
433  "LPC32xx NAND flash controller");
435  }
436 
437  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
438  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
440  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
441  /* MLC_CMD = command */
442  retval = target_write_u32(target, 0x200b8000, command);
443  if (retval != ERROR_OK) {
444  LOG_ERROR("could not set MLC_CMD");
446  }
447  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
448  /* SLC_CMD = command */
449  retval = target_write_u32(target, 0x20020008, command);
450  if (retval != ERROR_OK) {
451  LOG_ERROR("could not set SLC_CMD");
453  }
454  }
455 
456  return ERROR_OK;
457 }
458 
459 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
460 {
461  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
462  struct target *target = nand->target;
463  int retval;
464 
465  if (target->state != TARGET_HALTED) {
466  LOG_ERROR("target must be halted to use "
467  "LPC32xx NAND flash controller");
469  }
470 
471  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
472  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
474  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
475  /* MLC_ADDR = address */
476  retval = target_write_u32(target, 0x200b8004, address);
477  if (retval != ERROR_OK) {
478  LOG_ERROR("could not set MLC_ADDR");
480  }
481  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
482  /* SLC_ADDR = address */
483  retval = target_write_u32(target, 0x20020004, address);
484  if (retval != ERROR_OK) {
485  LOG_ERROR("could not set SLC_ADDR");
487  }
488  }
489 
490  return ERROR_OK;
491 }
492 
493 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
494 {
495  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
496  struct target *target = nand->target;
497  int retval;
498 
499  if (target->state != TARGET_HALTED) {
500  LOG_ERROR("target must be halted to use "
501  "LPC32xx NAND flash controller");
503  }
504 
505  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
506  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
508  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
509  /* MLC_DATA = data */
510  retval = target_write_u32(target, 0x200b0000, data);
511  if (retval != ERROR_OK) {
512  LOG_ERROR("could not set MLC_DATA");
514  }
515  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
516  /* SLC_DATA = data */
517  retval = target_write_u32(target, 0x20020000, data);
518  if (retval != ERROR_OK) {
519  LOG_ERROR("could not set SLC_DATA");
521  }
522  }
523 
524  return ERROR_OK;
525 }
526 
527 static int lpc32xx_read_data(struct nand_device *nand, void *data)
528 {
529  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
530  struct target *target = nand->target;
531  int retval;
532 
533  if (target->state != TARGET_HALTED) {
534  LOG_ERROR("target must be halted to use LPC32xx "
535  "NAND flash controller");
537  }
538 
539  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
540  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
542  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
543  /* data = MLC_DATA, use sized access */
544  if (nand->bus_width == 8) {
545  uint8_t *data8 = data;
546  retval = target_read_u8(target, 0x200b0000, data8);
547  } else {
548  LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
550  }
551  if (retval != ERROR_OK) {
552  LOG_ERROR("could not read MLC_DATA");
554  }
555  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
556  uint32_t data32;
557 
558  /* data = SLC_DATA, must use 32-bit access */
559  retval = target_read_u32(target, 0x20020000, &data32);
560  if (retval != ERROR_OK) {
561  LOG_ERROR("could not read SLC_DATA");
563  }
564 
565  if (nand->bus_width == 8) {
566  uint8_t *data8 = data;
567  *data8 = data32 & 0xff;
568  } else {
569  LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
571  }
572  }
573 
574  return ERROR_OK;
575 }
576 
577 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
578  uint8_t *data, uint32_t data_size,
579  uint8_t *oob, uint32_t oob_size)
580 {
581  struct target *target = nand->target;
582  int retval;
583  uint8_t status;
584  static uint8_t page_buffer[512];
585  static uint8_t oob_buffer[6];
586  int quarter, num_quarters;
587 
588  /* MLC_CMD = sequential input */
589  retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
590  if (retval != ERROR_OK) {
591  LOG_ERROR("could not set MLC_CMD");
593  }
594 
595  if (nand->page_size == 512) {
596  /* MLC_ADDR = 0x0 (one column cycle) */
597  retval = target_write_u32(target, 0x200b8004, 0x0);
598  if (retval != ERROR_OK) {
599  LOG_ERROR("could not set MLC_ADDR");
601  }
602 
603  /* MLC_ADDR = row */
604  retval = target_write_u32(target, 0x200b8004, page & 0xff);
605  if (retval != ERROR_OK) {
606  LOG_ERROR("could not set MLC_ADDR");
608  }
609  retval = target_write_u32(target, 0x200b8004,
610  (page >> 8) & 0xff);
611  if (retval != ERROR_OK) {
612  LOG_ERROR("could not set MLC_ADDR");
614  }
615 
616  if (nand->address_cycles == 4) {
617  retval = target_write_u32(target, 0x200b8004,
618  (page >> 16) & 0xff);
619  if (retval != ERROR_OK) {
620  LOG_ERROR("could not set MLC_ADDR");
622  }
623  }
624  } else {
625  /* MLC_ADDR = 0x0 (two column cycles) */
626  retval = target_write_u32(target, 0x200b8004, 0x0);
627  if (retval != ERROR_OK) {
628  LOG_ERROR("could not set MLC_ADDR");
630  }
631  retval = target_write_u32(target, 0x200b8004, 0x0);
632  if (retval != ERROR_OK) {
633  LOG_ERROR("could not set MLC_ADDR");
635  }
636 
637  /* MLC_ADDR = row */
638  retval = target_write_u32(target, 0x200b8004, page & 0xff);
639  if (retval != ERROR_OK) {
640  LOG_ERROR("could not set MLC_ADDR");
642  }
643  retval = target_write_u32(target, 0x200b8004,
644  (page >> 8) & 0xff);
645  if (retval != ERROR_OK) {
646  LOG_ERROR("could not set MLC_ADDR");
648  }
649  }
650 
651  /* when using the MLC controller, we have to treat a large page device
652  * as being made out of four quarters, each the size of a small page
653  * device
654  */
655  num_quarters = (nand->page_size == 2048) ? 4 : 1;
656 
657  for (quarter = 0; quarter < num_quarters; quarter++) {
658  int thisrun_data_size = (data_size > 512) ? 512 : data_size;
659  int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
660 
661  memset(page_buffer, 0xff, 512);
662  if (data) {
663  memcpy(page_buffer, data, thisrun_data_size);
664  data_size -= thisrun_data_size;
665  data += thisrun_data_size;
666  }
667 
668  memset(oob_buffer, 0xff, 6);
669  if (oob) {
670  memcpy(oob_buffer, oob, thisrun_oob_size);
671  oob_size -= thisrun_oob_size;
672  oob += thisrun_oob_size;
673  }
674 
675  /* write MLC_ECC_ENC_REG to start encode cycle */
676  retval = target_write_u32(target, 0x200b8008, 0x0);
677  if (retval != ERROR_OK) {
678  LOG_ERROR("could not set MLC_ECC_ENC_REG");
680  }
681 
682  retval = target_write_memory(target, 0x200a8000,
683  4, 128, page_buffer);
684  if (retval != ERROR_OK) {
685  LOG_ERROR("could not set MLC_BUF (data)");
687  }
688  retval = target_write_memory(target, 0x200a8000,
689  1, 6, oob_buffer);
690  if (retval != ERROR_OK) {
691  LOG_ERROR("could not set MLC_BUF (oob)");
693  }
694 
695  /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
696  retval = target_write_u32(target, 0x200b8010, 0x0);
697  if (retval != ERROR_OK) {
698  LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
700  }
701 
702  if (!lpc32xx_controller_ready(nand, 1000)) {
703  LOG_ERROR("timeout while waiting for "
704  "completion of auto encode cycle");
706  }
707  }
708 
709  /* MLC_CMD = auto program command */
710  retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
711  if (retval != ERROR_OK) {
712  LOG_ERROR("could not set MLC_CMD");
714  }
715 
716  retval = nand_read_status(nand, &status);
717  if (retval != ERROR_OK) {
718  LOG_ERROR("couldn't read status");
720  }
721 
722  if (status & NAND_STATUS_FAIL) {
723  LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
724  status);
726  }
727 
728  return ERROR_OK;
729 }
730 
731 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
732  * target internal memory. The transfer to/from flash is done by DMA. This
733  * function sets up the dma linked list in host memory for later transfer to
734  * target.
735  */
736 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
737  int do_read)
738 {
739  uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
740 
741  /* DMACCxControl =
742  TransferSize =64,
743  Source burst size =16,
744  Destination burst size = 16,
745  Source transfer width = 32 bit,
746  Destination transfer width = 32 bit,
747  Source AHB master select = M0,
748  Destination AHB master select = M0,
749  Source increment = 0, // set later
750  Destination increment = 0, // set later
751  Terminal count interrupt enable bit = 0 // set on last
752  */ /*
753  * Write Operation Sequence for Small Block NAND
754  * ----------------------------------------------------------
755  * 1. X'fer 256 bytes of data from Memory to Flash.
756  * 2. Copy generated ECC data from Register to Spare Area
757  * 3. X'fer next 256 bytes of data from Memory to Flash.
758  * 4. Copy generated ECC data from Register to Spare Area.
759  * 5. X'fer 16 bytes of Spare area from Memory to Flash.
760  * Read Operation Sequence for Small Block NAND
761  * ----------------------------------------------------------
762  * 1. X'fer 256 bytes of data from Flash to Memory.
763  * 2. Copy generated ECC data from Register to ECC calc Buffer.
764  * 3. X'fer next 256 bytes of data from Flash to Memory.
765  * 4. Copy generated ECC data from Register to ECC calc Buffer.
766  * 5. X'fer 16 bytes of Spare area from Flash to Memory.
767  * Write Operation Sequence for Large Block NAND
768  * ----------------------------------------------------------
769  * 1. Steps(1-4) of Write Operations repeated for four times
770  * which generates 16 DMA descriptors to X'fer 2048 bytes of
771  * data & 32 bytes of ECC data.
772  * 2. X'fer 64 bytes of Spare area from Memory to Flash.
773  * Read Operation Sequence for Large Block NAND
774  * ----------------------------------------------------------
775  * 1. Steps(1-4) of Read Operations repeated for four times
776  * which generates 16 DMA descriptors to X'fer 2048 bytes of
777  * data & 32 bytes of ECC data.
778  * 2. X'fer 64 bytes of Spare area from Flash to Memory.
779  */
780 
781  ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
782  | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
783 
784  /* DMACCxControl =
785  TransferSize =1,
786  Source burst size =4,
787  Destination burst size = 4,
788  Source transfer width = 32 bit,
789  Destination transfer width = 32 bit,
790  Source AHB master select = M0,
791  Destination AHB master select = M0,
792  Source increment = 0,
793  Destination increment = 1,
794  Terminal count interrupt enable bit = 0
795  */
796  ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
797  | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
798 
799  /* DMACCxControl =
800  TransferSize =16 for lp or 4 for sp,
801  Source burst size =16,
802  Destination burst size = 16,
803  Source transfer width = 32 bit,
804  Destination transfer width = 32 bit,
805  Source AHB master select = M0,
806  Destination AHB master select = M0,
807  Source increment = 0, // set later
808  Destination increment = 0, // set later
809  Terminal count interrupt enable bit = 1 // set on last
810  */
811  oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
812  | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
813  | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
814  if (do_read) {
815  ctrl |= 1 << 27;/* Destination increment = 1 */
816  oob_ctrl |= 1 << 27; /* Destination increment = 1 */
817  dmasrc = 0x20020038; /* SLC_DMA_DATA */
818  dmadst = target_mem_base + DATA_OFFS;
819  } else {
820  ctrl |= 1 << 26;/* Source increment = 1 */
821  oob_ctrl |= 1 << 26; /* Source increment = 1 */
822  dmasrc = target_mem_base + DATA_OFFS;
823  dmadst = 0x20020038; /* SLC_DMA_DATA */
824  }
825  /*
826  * Write Operation Sequence for Small Block NAND
827  * ----------------------------------------------------------
828  * 1. X'fer 256 bytes of data from Memory to Flash.
829  * 2. Copy generated ECC data from Register to Spare Area
830  * 3. X'fer next 256 bytes of data from Memory to Flash.
831  * 4. Copy generated ECC data from Register to Spare Area.
832  * 5. X'fer 16 bytes of Spare area from Memory to Flash.
833  * Read Operation Sequence for Small Block NAND
834  * ----------------------------------------------------------
835  * 1. X'fer 256 bytes of data from Flash to Memory.
836  * 2. Copy generated ECC data from Register to ECC calc Buffer.
837  * 3. X'fer next 256 bytes of data from Flash to Memory.
838  * 4. Copy generated ECC data from Register to ECC calc Buffer.
839  * 5. X'fer 16 bytes of Spare area from Flash to Memory.
840  * Write Operation Sequence for Large Block NAND
841  * ----------------------------------------------------------
842  * 1. Steps(1-4) of Write Operations repeated for four times
843  * which generates 16 DMA descriptors to X'fer 2048 bytes of
844  * data & 32 bytes of ECC data.
845  * 2. X'fer 64 bytes of Spare area from Memory to Flash.
846  * Read Operation Sequence for Large Block NAND
847  * ----------------------------------------------------------
848  * 1. Steps(1-4) of Read Operations repeated for four times
849  * which generates 16 DMA descriptors to X'fer 2048 bytes of
850  * data & 32 bytes of ECC data.
851  * 2. X'fer 64 bytes of Spare area from Flash to Memory.
852  */
853  for (i = 0; i < page_size/0x100; i++) {
854  dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
855  dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
856  dmalist[i*2].next_lli =
857  target_mem_base + (i*2 + 1) * sizeof(struct dmac_ll);
858  dmalist[i*2].next_ctrl = ctrl;
859 
860  dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
861  dmalist[(i*2) + 1].dma_dest =
862  target_mem_base + ECC_OFFS + i * 4;
863  dmalist[(i*2) + 1].next_lli =
864  target_mem_base + (i*2 + 2) * sizeof(struct dmac_ll);
865  dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
866 
867  }
868  if (do_read)
869  dmadst = target_mem_base + SPARE_OFFS;
870  else {
871  dmasrc = target_mem_base + SPARE_OFFS;
872  dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
873  dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
874  }
875  dmalist[i*2].dma_src = dmasrc;
876  dmalist[i*2].dma_dest = dmadst;
877  dmalist[i*2].next_lli = 0;
878  dmalist[i*2].next_ctrl = oob_ctrl;
879 
880  return i * 2 + 1; /* Number of descriptors */
881 }
882 
883 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
884  int do_wait)
885 {
886  struct target *target = nand->target;
887  int retval;
888 
889  /* DMACIntTCClear = ch0 */
890  retval = target_write_u32(target, 0x31000008, 1);
891  if (retval != ERROR_OK) {
892  LOG_ERROR("Could not set DMACIntTCClear");
893  return retval;
894  }
895 
896  /* DMACIntErrClear = ch0 */
897  retval = target_write_u32(target, 0x31000010, 1);
898  if (retval != ERROR_OK) {
899  LOG_ERROR("Could not set DMACIntErrClear");
900  return retval;
901  }
902 
903  /* DMACCxConfig=
904  E=1,
905  SrcPeripheral = 1 (SLC),
906  DestPeripheral = 1 (SLC),
907  FlowCntrl = 2 (Pher -> Mem, DMA),
908  IE = 0,
909  ITC = 0,
910  L= 0,
911  H=0
912  */
913  retval = target_write_u32(target, 0x31000110,
914  1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
915  | 0<<15 | 0<<16 | 0<<18);
916  if (retval != ERROR_OK) {
917  LOG_ERROR("Could not set DMACC0Config");
918  return retval;
919  }
920 
921  /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
922  retval = target_write_u32(target, 0x20020010, 0x3);
923  if (retval != ERROR_OK) {
924  LOG_ERROR("Could not set SLC_CTRL");
925  return retval;
926  }
927 
928  /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
929  retval = target_write_u32(target, 0x20020028, 2);
930  if (retval != ERROR_OK) {
931  LOG_ERROR("Could not set SLC_ICR");
932  return retval;
933  }
934 
935  /* SLC_TC */
936  retval = target_write_u32(target, 0x20020030, count);
937  if (retval != ERROR_OK) {
938  LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
939  return retval;
940  }
941 
942  /* Wait finish */
943  if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
944  LOG_ERROR("timeout while waiting for completion of DMA");
946  }
947 
948  return retval;
949 }
950 
951 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
952 {
953  struct target *target = nand->target;
954 
955  LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
956 
957  do {
958  uint32_t tc_stat;
959  uint32_t err_stat;
960  int retval;
961 
962  /* Read DMACRawIntTCStat */
963  retval = target_read_u32(target, 0x31000014, &tc_stat);
964  if (retval != ERROR_OK) {
965  LOG_ERROR("Could not read DMACRawIntTCStat");
966  return 0;
967  }
968  /* Read DMACRawIntErrStat */
969  retval = target_read_u32(target, 0x31000018, &err_stat);
970  if (retval != ERROR_OK) {
971  LOG_ERROR("Could not read DMACRawIntErrStat");
972  return 0;
973  }
974  if ((tc_stat | err_stat) & 1) {
975  LOG_DEBUG("lpc32xx_dma_ready count=%d",
976  timeout);
977  if (err_stat & 1) {
978  LOG_ERROR("lpc32xx_dma_ready "
979  "DMA error, aborted");
980  return 0;
981  } else
982  return 1;
983  }
984 
985  alive_sleep(1);
986  } while (timeout-- > 0);
987 
988  return 0;
989 }
990 
991 static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
992  const uint32_t *ecc, int count)
993 {
994  int i;
995  for (i = 0; i < (count * 3); i += 3) {
996  uint32_t ce = ecc[i/3];
997  ce = ~(ce << 2) & 0xFFFFFF;
998  spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
999  spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1000  spare[i] = (uint8_t)(ce & 0xFF);
1001  }
1002  return 0;
1003 }
1004 
1005 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1006 {
1007  int addr = 0;
1008  while (oob_size > 0) {
1009  LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1010  oob[0], oob[1], oob[2], oob[3],
1011  oob[4], oob[5], oob[6], oob[7]);
1012  oob += 8;
1013  addr += 8;
1014  oob_size -= 8;
1015  }
1016 }
1017 
1018 static int lpc32xx_write_page_slc(struct nand_device *nand,
1019  struct working_area *pworking_area,
1020  uint32_t page, uint8_t *data,
1021  uint32_t data_size, uint8_t *oob,
1022  uint32_t oob_size)
1023 {
1024  struct target *target = nand->target;
1025  int retval;
1026  uint32_t target_mem_base;
1027 
1028  LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
1029  "data_size=%" PRIu32 ", oob_size=%" PRIu32,
1030  page, !!data, !!oob, data_size, oob_size);
1031 
1032  target_mem_base = pworking_area->address;
1033  /*
1034  * Skip writing page which has all 0xFF data as this will
1035  * generate 0x0 value.
1036  */
1037  if (data && !oob) {
1038  uint32_t i, all_ff = 1;
1039  for (i = 0; i < data_size; i++)
1040  if (data[i] != 0xFF) {
1041  all_ff = 0;
1042  break;
1043  }
1044  if (all_ff)
1045  return ERROR_OK;
1046  }
1047  /* Make the dma descriptors in local memory */
1048  int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1049  /* Write them to target.
1050  XXX: Assumes host and target have same byte sex.
1051  */
1052  retval = target_write_memory(target, target_mem_base, 4,
1053  nll * sizeof(struct dmac_ll) / 4,
1054  (uint8_t *)dmalist);
1055  if (retval != ERROR_OK) {
1056  LOG_ERROR("Could not write DMA descriptors to IRAM");
1057  return retval;
1058  }
1059 
1060  retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1061  if (retval != ERROR_OK) {
1062  LOG_ERROR("NAND_CMD_SEQIN failed");
1063  return retval;
1064  }
1065 
1066  /* SLC_CFG =
1067  Force nCE assert,
1068  DMA ECC enabled,
1069  ECC enabled,
1070  DMA burst enabled,
1071  DMA write to SLC,
1072  WIDTH = bus_width
1073  */
1074  retval = target_write_u32(target, 0x20020014, 0x3c);
1075  if (retval != ERROR_OK) {
1076  LOG_ERROR("Could not set SLC_CFG");
1077  return retval;
1078  }
1079  if (data) {
1080  /* Write data to target */
1081  static uint8_t fdata[2048];
1082  memset(fdata, 0xFF, nand->page_size);
1083  memcpy(fdata, data, data_size);
1084  retval = target_write_memory(target,
1085  target_mem_base + DATA_OFFS,
1086  4, nand->page_size/4, fdata);
1087  if (retval != ERROR_OK) {
1088  LOG_ERROR("Could not write data to IRAM");
1089  return retval;
1090  }
1091 
1092  /* Write first descriptor to DMA controller */
1093  retval = target_write_memory(target, 0x31000100, 4,
1094  sizeof(struct dmac_ll) / 4,
1095  (uint8_t *)dmalist);
1096  if (retval != ERROR_OK) {
1097  LOG_ERROR("Could not write DMA descriptor to DMAC");
1098  return retval;
1099  }
1100 
1101  /* Start xfer of data from iram to flash using DMA */
1102  int tot_size = nand->page_size;
1103  tot_size += tot_size == 2048 ? 64 : 16;
1104  retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1105  if (retval != ERROR_OK) {
1106  LOG_ERROR("DMA failed");
1107  return retval;
1108  }
1109 
1110  /* Wait for DMA to finish. SLC is not finished at this stage */
1111  if (!lpc32xx_dma_ready(nand, 100)) {
1112  LOG_ERROR("Data DMA failed during write");
1114  }
1115  } /* data xfer */
1116 
1117  /* Copy OOB to iram */
1118  static uint8_t foob[64];
1119  int foob_size = nand->page_size == 2048 ? 64 : 16;
1120  memset(foob, 0xFF, foob_size);
1121  if (oob) /* Raw mode */
1122  memcpy(foob, oob, oob_size);
1123  else {
1124  /* Get HW generated ECC, made while writing data */
1125  int ecc_count = nand->page_size == 2048 ? 8 : 2;
1126  static uint32_t hw_ecc[8];
1127  retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1128  4, ecc_count, (uint8_t *)hw_ecc);
1129  if (retval != ERROR_OK) {
1130  LOG_ERROR("Reading hw generated ECC from IRAM failed");
1131  return retval;
1132  }
1133  /* Copy to oob, at correct offsets */
1134  static uint8_t ecc[24];
1135  slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1136  const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1137  int i;
1138  for (i = 0; i < ecc_count * 3; i++)
1139  foob[layout[i]] = ecc[i];
1140  lpc32xx_dump_oob(foob, foob_size);
1141  }
1142  retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1143  foob_size / 4, foob);
1144  if (retval != ERROR_OK) {
1145  LOG_ERROR("Writing OOB to IRAM failed");
1146  return retval;
1147  }
1148 
1149  /* Write OOB descriptor to DMA controller */
1150  retval = target_write_memory(target, 0x31000100, 4,
1151  sizeof(struct dmac_ll) / 4,
1152  (uint8_t *)(&dmalist[nll-1]));
1153  if (retval != ERROR_OK) {
1154  LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1155  return retval;
1156  }
1157  if (data) {
1158  /* Only restart DMA with last descriptor,
1159  * don't setup SLC again */
1160 
1161  /* DMACIntTCClear = ch0 */
1162  retval = target_write_u32(target, 0x31000008, 1);
1163  if (retval != ERROR_OK) {
1164  LOG_ERROR("Could not set DMACIntTCClear");
1165  return retval;
1166  }
1167  /* DMACCxConfig=
1168  * E=1,
1169  * SrcPeripheral = 1 (SLC),
1170  * DestPeripheral = 1 (SLC),
1171  * FlowCntrl = 2 (Pher -> Mem, DMA),
1172  * IE = 0,
1173  * ITC = 0,
1174  * L= 0,
1175  * H=0
1176  */
1177  retval = target_write_u32(target, 0x31000110,
1178  1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1179  | 0<<15 | 0<<16 | 0<<18);
1180  if (retval != ERROR_OK) {
1181  LOG_ERROR("Could not set DMACC0Config");
1182  return retval;
1183  }
1184  /* Wait finish */
1185  if (!lpc32xx_tc_ready(nand, 100)) {
1186  LOG_ERROR("timeout while waiting for "
1187  "completion of DMA");
1189  }
1190  } else {
1191  /* Start xfer of data from iram to flash using DMA */
1192  retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1193  if (retval != ERROR_OK) {
1194  LOG_ERROR("DMA OOB failed");
1195  return retval;
1196  }
1197  }
1198 
1199  /* Let NAND start actual writing */
1200  retval = nand_write_finish(nand);
1201  if (retval != ERROR_OK) {
1202  LOG_ERROR("nand_write_finish failed");
1203  return retval;
1204  }
1205 
1206  return ERROR_OK;
1207 }
1208 
1209 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1210  uint8_t *data, uint32_t data_size,
1211  uint8_t *oob, uint32_t oob_size)
1212 {
1213  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1214  struct target *target = nand->target;
1215  int retval = ERROR_OK;
1216 
1217  if (target->state != TARGET_HALTED) {
1218  LOG_ERROR("target must be halted to use LPC32xx "
1219  "NAND flash controller");
1221  }
1222 
1223  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
1224  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1226  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1227  if (!data && oob) {
1228  LOG_ERROR("LPC32xx MLC controller can't write "
1229  "OOB data only");
1231  }
1232 
1233  if (oob && (oob_size > 24)) {
1234  LOG_ERROR("LPC32xx MLC controller can't write more "
1235  "than 6 bytes for each quarter's OOB data");
1237  }
1238 
1239  if (data_size > (uint32_t)nand->page_size) {
1240  LOG_ERROR("data size exceeds page size");
1242  }
1243 
1244  retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1245  oob, oob_size);
1246  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1247  struct working_area *pworking_area;
1248  if (!data && oob) {
1249  /*
1250  * if oob only mode is active original method is used
1251  * as SLC controller hangs during DMA interworking. (?)
1252  * Anyway the code supports the oob only mode below.
1253  */
1254  return nand_write_page_raw(nand, page, data,
1255  data_size, oob, oob_size);
1256  }
1258  nand->page_size + DATA_OFFS,
1259  &pworking_area);
1260  if (retval != ERROR_OK) {
1261  LOG_ERROR("Can't allocate working area in "
1262  "LPC internal RAM");
1264  }
1265  retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1266  data, data_size, oob, oob_size);
1267  target_free_working_area(target, pworking_area);
1268  }
1269 
1270  return retval;
1271 }
1272 
1273 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1274  uint8_t *data, uint32_t data_size,
1275  uint8_t *oob, uint32_t oob_size)
1276 {
1277  struct target *target = nand->target;
1278  static uint8_t page_buffer[2048];
1279  static uint8_t oob_buffer[64];
1280  uint32_t page_bytes_done = 0;
1281  uint32_t oob_bytes_done = 0;
1282  uint32_t mlc_isr;
1283  int retval;
1284 
1285  if (!data && oob) {
1286  /* MLC_CMD = Read OOB
1287  * we can use the READOOB command on both small and large page
1288  * devices, as the controller translates the 0x50 command to
1289  * a 0x0 with appropriate positioning of the serial buffer
1290  * read pointer
1291  */
1292  retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1293  } else {
1294  /* MLC_CMD = Read0 */
1295  retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1296  }
1297  if (retval != ERROR_OK) {
1298  LOG_ERROR("could not set MLC_CMD");
1300  }
1301  if (nand->page_size == 512) {
1302  /* small page device
1303  * MLC_ADDR = 0x0 (one column cycle) */
1304  retval = target_write_u32(target, 0x200b8004, 0x0);
1305  if (retval != ERROR_OK) {
1306  LOG_ERROR("could not set MLC_ADDR");
1308  }
1309 
1310  /* MLC_ADDR = row */
1311  retval = target_write_u32(target, 0x200b8004, page & 0xff);
1312  if (retval != ERROR_OK) {
1313  LOG_ERROR("could not set MLC_ADDR");
1315  }
1316  retval = target_write_u32(target, 0x200b8004,
1317  (page >> 8) & 0xff);
1318  if (retval != ERROR_OK) {
1319  LOG_ERROR("could not set MLC_ADDR");
1321  }
1322 
1323  if (nand->address_cycles == 4) {
1324  retval = target_write_u32(target, 0x200b8004,
1325  (page >> 16) & 0xff);
1326  if (retval != ERROR_OK) {
1327  LOG_ERROR("could not set MLC_ADDR");
1329  }
1330  }
1331  } else {
1332  /* large page device
1333  * MLC_ADDR = 0x0 (two column cycles) */
1334  retval = target_write_u32(target, 0x200b8004, 0x0);
1335  if (retval != ERROR_OK) {
1336  LOG_ERROR("could not set MLC_ADDR");
1338  }
1339  retval = target_write_u32(target, 0x200b8004, 0x0);
1340  if (retval != ERROR_OK) {
1341  LOG_ERROR("could not set MLC_ADDR");
1343  }
1344 
1345  /* MLC_ADDR = row */
1346  retval = target_write_u32(target, 0x200b8004, page & 0xff);
1347  if (retval != ERROR_OK) {
1348  LOG_ERROR("could not set MLC_ADDR");
1350  }
1351  retval = target_write_u32(target, 0x200b8004,
1352  (page >> 8) & 0xff);
1353  if (retval != ERROR_OK) {
1354  LOG_ERROR("could not set MLC_ADDR");
1356  }
1357 
1358  /* MLC_CMD = Read Start */
1359  retval = target_write_u32(target, 0x200b8000,
1361  if (retval != ERROR_OK) {
1362  LOG_ERROR("could not set MLC_CMD");
1364  }
1365  }
1366 
1367  while (page_bytes_done < (uint32_t)nand->page_size) {
1368  /* MLC_ECC_AUTO_DEC_REG = dummy */
1369  retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1370  if (retval != ERROR_OK) {
1371  LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1373  }
1374 
1375  if (!lpc32xx_controller_ready(nand, 1000)) {
1376  LOG_ERROR("timeout while waiting for "
1377  "completion of auto decode cycle");
1379  }
1380 
1381  retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1382  if (retval != ERROR_OK) {
1383  LOG_ERROR("could not read MLC_ISR");
1385  }
1386 
1387  if (mlc_isr & 0x8) {
1388  if (mlc_isr & 0x40) {
1389  LOG_ERROR("uncorrectable error detected: "
1390  "0x%2.2x", (unsigned)mlc_isr);
1392  }
1393 
1394  LOG_WARNING("%i symbol error detected and corrected",
1395  ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1396  }
1397 
1398  if (data) {
1399  retval = target_read_memory(target, 0x200a8000, 4, 128,
1400  page_buffer + page_bytes_done);
1401  if (retval != ERROR_OK) {
1402  LOG_ERROR("could not read MLC_BUF (data)");
1404  }
1405  }
1406 
1407  if (oob) {
1408  retval = target_read_memory(target, 0x200a8000, 4, 4,
1409  oob_buffer + oob_bytes_done);
1410  if (retval != ERROR_OK) {
1411  LOG_ERROR("could not read MLC_BUF (oob)");
1413  }
1414  }
1415 
1416  page_bytes_done += 512;
1417  oob_bytes_done += 16;
1418  }
1419 
1420  if (data)
1421  memcpy(data, page_buffer, data_size);
1422 
1423  if (oob)
1424  memcpy(oob, oob_buffer, oob_size);
1425 
1426  return ERROR_OK;
1427 }
1428 
1429 static int lpc32xx_read_page_slc(struct nand_device *nand,
1430  struct working_area *pworking_area,
1431  uint32_t page, uint8_t *data,
1432  uint32_t data_size, uint8_t *oob,
1433  uint32_t oob_size)
1434 {
1435  struct target *target = nand->target;
1436  int retval;
1437  uint32_t target_mem_base;
1438 
1439  LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
1440  page, data_size, oob_size);
1441 
1442  target_mem_base = pworking_area->address;
1443 
1444  /* Make the dma descriptors in local memory */
1445  int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1446  /* Write them to target.
1447  XXX: Assumes host and target have same byte sex.
1448  */
1449  retval = target_write_memory(target, target_mem_base, 4,
1450  nll * sizeof(struct dmac_ll) / 4,
1451  (uint8_t *)dmalist);
1452  if (retval != ERROR_OK) {
1453  LOG_ERROR("Could not write DMA descriptors to IRAM");
1454  return retval;
1455  }
1456 
1457  retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1458  if (retval != ERROR_OK) {
1459  LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1460  return retval;
1461  }
1462 
1463  /* SLC_CFG =
1464  Force nCE assert,
1465  DMA ECC enabled,
1466  ECC enabled,
1467  DMA burst enabled,
1468  DMA read from SLC,
1469  WIDTH = bus_width
1470  */
1471  retval = target_write_u32(target, 0x20020014, 0x3e);
1472  if (retval != ERROR_OK) {
1473  LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1474  return retval;
1475  }
1476 
1477  /* Write first descriptor to DMA controller */
1478  retval = target_write_memory(target, 0x31000100, 4,
1479  sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist);
1480  if (retval != ERROR_OK) {
1481  LOG_ERROR("Could not write DMA descriptor to DMAC");
1482  return retval;
1483  }
1484 
1485  /* Start xfer of data from flash to iram using DMA */
1486  int tot_size = nand->page_size;
1487  tot_size += nand->page_size == 2048 ? 64 : 16;
1488  retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1489  if (retval != ERROR_OK) {
1490  LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1491  return retval;
1492  }
1493 
1494  /* Copy data from iram */
1495  if (data) {
1496  retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1497  4, data_size/4, data);
1498  if (retval != ERROR_OK) {
1499  LOG_ERROR("Could not read data from IRAM");
1500  return retval;
1501  }
1502  }
1503  if (oob) {
1504  /* No error correction, just return data as read from flash */
1505  retval = target_read_memory(target,
1506  target_mem_base + SPARE_OFFS, 4,
1507  oob_size/4, oob);
1508  if (retval != ERROR_OK) {
1509  LOG_ERROR("Could not read OOB from IRAM");
1510  return retval;
1511  }
1512  return ERROR_OK;
1513  }
1514 
1515  /* Copy OOB from flash, stored in IRAM */
1516  static uint8_t foob[64];
1517  retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1518  4, nand->page_size == 2048 ? 16 : 4, foob);
1519  lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1520  if (retval != ERROR_OK) {
1521  LOG_ERROR("Could not read OOB from IRAM");
1522  return retval;
1523  }
1524  /* Copy ECC from HW, generated while reading */
1525  int ecc_count = nand->page_size == 2048 ? 8 : 2;
1526  static uint32_t hw_ecc[8]; /* max size */
1527  retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1528  ecc_count, (uint8_t *)hw_ecc);
1529  if (retval != ERROR_OK) {
1530  LOG_ERROR("Could not read hw generated ECC from IRAM");
1531  return retval;
1532  }
1533  static uint8_t ecc[24];
1534  slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1535  /* Copy ECC from flash using correct layout */
1536  static uint8_t fecc[24];/* max size */
1537  const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1538  int i;
1539  for (i = 0; i < ecc_count * 3; i++)
1540  fecc[i] = foob[layout[i]];
1541  /* Compare ECC and possibly correct data */
1542  for (i = 0; i < ecc_count; i++) {
1543  retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1544  &ecc[i * 3]);
1545  if (retval > 0)
1546  LOG_WARNING("error detected and corrected: %" PRIu32 "/%d",
1547  page, i);
1548  if (retval < 0)
1549  break;
1550  }
1551  if (i == ecc_count)
1552  retval = ERROR_OK;
1553  else {
1554  LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i);
1555  retval = ERROR_NAND_OPERATION_FAILED;
1556  }
1557  return retval;
1558 }
1559 
1560 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1561  uint8_t *data, uint32_t data_size,
1562  uint8_t *oob, uint32_t oob_size)
1563 {
1564  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1565  struct target *target = nand->target;
1566  int retval = ERROR_OK;
1567 
1568  if (target->state != TARGET_HALTED) {
1569  LOG_ERROR("target must be halted to use LPC32xx "
1570  "NAND flash controller");
1572  }
1573 
1574  if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
1575  LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1577  } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1578  if (data_size > (uint32_t)nand->page_size) {
1579  LOG_ERROR("data size exceeds page size");
1581  }
1582  retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1583  oob, oob_size);
1584  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1585  struct working_area *pworking_area;
1586 
1588  nand->page_size + 0x200,
1589  &pworking_area);
1590  if (retval != ERROR_OK) {
1591  LOG_ERROR("Can't allocate working area in "
1592  "LPC internal RAM");
1594  }
1595  retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1596  data, data_size, oob, oob_size);
1597  target_free_working_area(target, pworking_area);
1598  }
1599 
1600  return retval;
1601 }
1602 
1603 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1604 {
1605  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1606  struct target *target = nand->target;
1607  int retval;
1608 
1609  if (target->state != TARGET_HALTED) {
1610  LOG_ERROR("target must be halted to use LPC32xx "
1611  "NAND flash controller");
1613  }
1614 
1615  LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1616 
1617  do {
1618  if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1619  uint8_t status;
1620 
1621  /* Read MLC_ISR, wait for controller to become ready */
1622  retval = target_read_u8(target, 0x200b8048, &status);
1623  if (retval != ERROR_OK) {
1624  LOG_ERROR("could not set MLC_STAT");
1626  }
1627 
1628  if (status & 2) {
1629  LOG_DEBUG("lpc32xx_controller_ready count=%d",
1630  timeout);
1631  return 1;
1632  }
1633  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1634  uint32_t status;
1635 
1636  /* Read SLC_STAT and check READY bit */
1637  retval = target_read_u32(target, 0x20020018, &status);
1638  if (retval != ERROR_OK) {
1639  LOG_ERROR("could not set SLC_STAT");
1641  }
1642 
1643  if (status & 1) {
1644  LOG_DEBUG("lpc32xx_controller_ready count=%d",
1645  timeout);
1646  return 1;
1647  }
1648  }
1649 
1650  alive_sleep(1);
1651  } while (timeout-- > 0);
1652 
1653  return 0;
1654 }
1655 
1656 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1657 {
1658  struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1659  struct target *target = nand->target;
1660  int retval;
1661 
1662  if (target->state != TARGET_HALTED) {
1663  LOG_ERROR("target must be halted to use LPC32xx "
1664  "NAND flash controller");
1666  }
1667 
1668  LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1669 
1670  do {
1671  if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
1672  uint8_t status = 0x0;
1673 
1674  /* Read MLC_ISR, wait for NAND flash device to
1675  * become ready */
1676  retval = target_read_u8(target, 0x200b8048, &status);
1677  if (retval != ERROR_OK) {
1678  LOG_ERROR("could not read MLC_ISR");
1680  }
1681 
1682  if (status & 1) {
1683  LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1684  timeout);
1685  return 1;
1686  }
1687  } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
1688  uint32_t status = 0x0;
1689 
1690  /* Read SLC_STAT and check READY bit */
1691  retval = target_read_u32(target, 0x20020018, &status);
1692  if (retval != ERROR_OK) {
1693  LOG_ERROR("could not read SLC_STAT");
1695  }
1696 
1697  if (status & 1) {
1698  LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1699  timeout);
1700  return 1;
1701  }
1702  }
1703 
1704  alive_sleep(1);
1705  } while (timeout-- > 0);
1706 
1707  return 0;
1708 }
1709 
1710 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1711 {
1712  struct target *target = nand->target;
1713 
1714  LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1715 
1716  do {
1717  uint32_t status = 0x0;
1718  int retval;
1719  /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1720  retval = target_read_u32(target, 0x2002001c, &status);
1721  if (retval != ERROR_OK) {
1722  LOG_ERROR("Could not read SLC_INT_STAT");
1723  return 0;
1724  }
1725  if (status & 2) {
1726  LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1727  return 1;
1728  }
1729 
1730  alive_sleep(1);
1731  } while (timeout-- > 0);
1732 
1733  return 0;
1734 }
1735 
1736 COMMAND_HANDLER(handle_lpc32xx_select_command)
1737 {
1738  struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1739  char *selected[] = {
1740  "no", "mlc", "slc"
1741  };
1742 
1743  if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1745 
1746  unsigned num;
1747  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1748  struct nand_device *nand = get_nand_device_by_num(num);
1749  if (!nand) {
1750  command_print(CMD, "nand device '#%s' is out of bounds",
1751  CMD_ARGV[0]);
1752  return ERROR_OK;
1753  }
1754 
1755  lpc32xx_info = nand->controller_priv;
1756 
1757  if (CMD_ARGC >= 2) {
1758  if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1759  lpc32xx_info->selected_controller =
1761  } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1762  lpc32xx_info->selected_controller =
1764  } else
1766  }
1767 
1768  command_print(CMD, "%s controller selected",
1769  selected[lpc32xx_info->selected_controller]);
1770 
1771  return ERROR_OK;
1772 }
1773 
1774 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1775  {
1776  .name = "select",
1777  .handler = handle_lpc32xx_select_command,
1778  .mode = COMMAND_EXEC,
1779  .help = "select MLC or SLC controller (default is MLC)",
1780  .usage = "bank_id ['mlc'|'slc' ]",
1781  },
1783 };
1784 static const struct command_registration lpc32xx_command_handler[] = {
1785  {
1786  .name = "lpc32xx",
1787  .mode = COMMAND_ANY,
1788  .help = "LPC32xx NAND flash controller commands",
1789  .usage = "",
1791  },
1793 };
1794 
1796  .name = "lpc32xx",
1797  .commands = lpc32xx_command_handler,
1798  .nand_device_command = lpc32xx_nand_device_command,
1799  .init = lpc32xx_init,
1800  .reset = lpc32xx_reset,
1801  .command = lpc32xx_command,
1802  .address = lpc32xx_address,
1803  .write_data = lpc32xx_write_data,
1804  .read_data = lpc32xx_read_data,
1805  .write_page = lpc32xx_write_page,
1806  .read_page = lpc32xx_read_page,
1807  .nand_ready = lpc32xx_nand_ready,
1808 };
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
ecc
Definition: davinci.c:22
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
int nand_read_status(struct nand_device *nand, uint8_t *status)
int nand_write_finish(struct nand_device *nand)
int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
struct nand_device * get_nand_device_by_num(int num)
int nand_page_command(struct nand_device *nand, uint32_t page, uint8_t cmd, bool oob_only)
void alive_sleep(uint64_t ms)
Definition: log.c:456
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define DATA_OFFS
Definition: lpc32xx.c:38
static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
Definition: lpc32xx.c:1710
static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, int do_read)
Definition: lpc32xx.c:736
static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
Definition: lpc32xx.c:88
static int lpc32xx_write_page_slc(struct nand_device *nand, struct working_area *pworking_area, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1018
static const struct command_registration lpc32xx_command_handler[]
Definition: lpc32xx.c:1784
#define ECC_OFFS
Definition: lpc32xx.c:36
static int lpc32xx_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1209
static int lpc32xx_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1560
static const int sp_ooblayout[]
Definition: lpc32xx.c:40
static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
Definition: lpc32xx.c:1603
static int lpc32xx_address(struct nand_device *nand, uint8_t address)
Definition: lpc32xx.c:459
static const int lp_ooblayout[]
Definition: lpc32xx.c:43
static int lpc32xx_read_data(struct nand_device *nand, void *data)
Definition: lpc32xx.c:527
static float lpc32xx_cycle_time(struct nand_device *nand)
Definition: lpc32xx.c:116
static int lpc32xx_init(struct nand_device *nand)
Definition: lpc32xx.c:177
static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1273
static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, int do_wait)
Definition: lpc32xx.c:883
static const struct command_registration lpc32xx_exec_command_handlers[]
Definition: lpc32xx.c:1774
static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
Definition: lpc32xx.c:493
static int lpc32xx_reset(struct nand_device *nand)
Definition: lpc32xx.c:379
static struct dmac_ll dmalist[(2048/256) *2+1]
Definition: lpc32xx.c:57
COMMAND_HANDLER(handle_lpc32xx_select_command)
Definition: lpc32xx.c:1736
static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1005
static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:577
static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
Definition: lpc32xx.c:951
static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
Definition: lpc32xx.c:1656
static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare, const uint32_t *ecc, int count)
Definition: lpc32xx.c:991
#define SPARE_OFFS
Definition: lpc32xx.c:37
NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
Definition: lpc32xx.c:61
static int lpc32xx_read_page_slc(struct nand_device *nand, struct working_area *pworking_area, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc32xx.c:1429
static int lpc32xx_command(struct nand_device *nand, uint8_t command)
Definition: lpc32xx.c:425
@ LPC32XX_MLC_CONTROLLER
Definition: lpc32xx.h:13
@ LPC32XX_SLC_CONTROLLER
Definition: lpc32xx.h:14
@ LPC32XX_NO_CONTROLLER
Definition: lpc32xx.h:12
#define ERROR_NAND_OPERATION_TIMEOUT
Definition: nand/core.h:218
#define ERROR_NAND_OPERATION_FAILED
Definition: nand/core.h:217
int nand_correct_data(struct nand_device *nand, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
nand_correct_data - Detect and correct a 1 bit error for 256 byte block
Definition: ecc.c:113
@ NAND_CMD_SEQIN
Definition: nand/core.h:148
@ NAND_CMD_READSTART
Definition: nand/core.h:155
@ NAND_CMD_READOOB
Definition: nand/core.h:144
@ NAND_CMD_READ0
Definition: nand/core.h:140
@ NAND_CMD_PAGEPROG
Definition: nand/core.h:143
@ NAND_STATUS_FAIL
Definition: nand/core.h:162
#define ERROR_NAND_OPERATION_NOT_SUPPORTED
Definition: nand/core.h:219
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
const char * name
Definition: command.h:235
volatile uint32_t next_lli
Definition: lpc32xx.c:53
volatile uint32_t dma_dest
Definition: lpc32xx.c:52
volatile uint32_t dma_src
Definition: lpc32xx.c:51
volatile uint32_t next_ctrl
Definition: lpc32xx.c:54
uint32_t sw_wp_upper_bound
Definition: lpc32xx.h:22
uint32_t sw_wp_lower_bound
Definition: lpc32xx.h:21
enum lpc32xx_selected_controller selected_controller
Definition: lpc32xx.h:19
void * controller_priv
Definition: nand/core.h:51
int page_size
Definition: nand/core.h:56
int address_cycles
Definition: nand/core.h:55
int bus_width
Definition: nand/core.h:54
struct target * target
Definition: nand/core.h:49
Interface for NAND flash controllers.
Definition: nand/driver.h:23
Definition: target.h:116
enum target_state state
Definition: target.h:157
Definition: psoc6.c:84
target_addr_t address
Definition: target.h:86
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2598
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2060
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2118
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
@ TARGET_HALTED
Definition: target.h:56
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t count[4]
Definition: vdebug.c:22