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armv8_dpm.h File Reference
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Macros

#define DRCR_CBRRQ   (1 << 4)
 
#define DRCR_CLEAR_EXCEPTIONS   (1 << 2)
 
#define DRCR_CSE   (1 << 2)
 
#define DRCR_CSPA   (1 << 3)
 
#define DRCR_HALT   (1 << 0)
 
#define DRCR_RESTART   (1 << 1)
 
#define DSCR_CUR_EL   (0x3 << 8)
 
#define DSCR_DEBUG_STATUS_MASK   (0x1F << 0)
 
#define DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */
 
#define DSCR_DTR_TX_FULL   (0x1 << 29)
 
#define DSCR_EL_STATUS_MASK   (0xF << 10)
 
#define DSCR_ERR   (0x1 << 6)
 
#define DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */
 
#define DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)
 
#define DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)
 
#define DSCR_HDE   (0x1 << 14)
 
#define DSCR_INTDIS_MASK   (0x3 << 22)
 
#define DSCR_ITE   (0x1 << 24)
 
#define DSCR_ITO   (0x1 << 28)
 
#define DSCR_MA   (0x1 << 20)
 
#define DSCR_NON_SECURE   (0x1 << 18)
 
#define DSCR_PIPE_ADVANCE   (0x1 << 25)
 
#define DSCR_RTO   (0x1 << 27) /* bit 28 is reserved */
 
#define DSCR_SDD   (0x1 << 16)
 
#define DSCR_SYS_ERROR_PEND   (0x1 << 7)
 
#define DSCR_TDA   (0x1 << 21)
 
#define DSCR_TXU   (0x1 << 26)
 
#define DSCRV8_ENTRY_BKPT   (0x7)
 
#define DSCRV8_ENTRY_EXCEPTION_CATCH   (0x37)
 
#define DSCRV8_ENTRY_EXT_DEBUG   (0x13)
 
#define DSCRV8_ENTRY_HALT_STEP   (0x3B)
 
#define DSCRV8_ENTRY_HALT_STEP_EXECLU   (0x1F)
 
#define DSCRV8_ENTRY_HALT_STEP_NORMAL   (0x1B)
 
#define DSCRV8_ENTRY_HLT   (0x2F)
 
#define DSCRV8_ENTRY_NON_DEBUG   (0x2)
 
#define DSCRV8_ENTRY_OS_UNLOCK   (0x23)
 
#define DSCRV8_ENTRY_RESET_CATCH   (0x27)
 
#define DSCRV8_ENTRY_RESTARTING   (0x1)
 
#define DSCRV8_ENTRY_SW_ACCESS_DBG   (0x33)
 
#define DSCRV8_ENTRY_WATCHPOINT   (0x2B)
 
#define DSCRV8_HALT_MASK   (0x3C)
 
#define PRCR_CORENPDRQ   (1 << 0)
 
#define PRCR_COREPURQ   (1 << 3)
 
#define PRCR_CWRR   (1 << 2)
 
#define PRSR_DLK   (1 << 6)
 
#define PRSR_EDAD   (1 << 7)
 
#define PRSR_EPMAD   (1 << 9)
 
#define PRSR_HALT   (1 << 4)
 
#define PRSR_OSLK   (1 << 5)
 
#define PRSR_PU   (1 << 0)
 
#define PRSR_RESET   (1 << 2)
 
#define PRSR_SDAD   (1 << 8)
 
#define PRSR_SDR   (1 << 11)
 
#define PRSR_SPD   (1 << 1)
 
#define PRSR_SPMAD   (1 << 10)
 
#define PRSR_SR   (1 << 3)
 

Functions

enum arm_state armv8_dpm_get_core_state (struct arm_dpm *dpm)
 Get core state from EDSCR, without necessity to retrieve CPSR. More...
 
void armv8_dpm_handle_exception (struct arm_dpm *dpm)
 
int armv8_dpm_initialize (struct arm_dpm *dpm)
 Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module. More...
 
int armv8_dpm_modeswitch (struct arm_dpm *dpm, enum arm_mode mode)
 
int armv8_dpm_read_current_registers (struct arm_dpm *)
 Read basic registers of the the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). More...
 
void armv8_dpm_report_dscr (struct arm_dpm *dpm, uint32_t dcsr)
 
void armv8_dpm_report_wfar (struct arm_dpm *, uint64_t wfar)
 
int armv8_dpm_setup (struct arm_dpm *dpm)
 This wraps an implementation of DPM primitives. More...
 
int armv8_dpm_write_dirty_registers (struct arm_dpm *, bool bpwp)
 Writes all modified core registers for all processor modes. More...
 

Macro Definition Documentation

#define DRCR_CBRRQ   (1 << 4)

Definition at line 85 of file armv8_dpm.h.

#define DRCR_CLEAR_EXCEPTIONS   (1 << 2)

Definition at line 97 of file armv8_dpm.h.

#define DRCR_CSE   (1 << 2)

Definition at line 83 of file armv8_dpm.h.

Referenced by aarch64_debug_entry(), and armv8_dpm_handle_exception().

#define DRCR_CSPA   (1 << 3)

Definition at line 84 of file armv8_dpm.h.

#define DRCR_HALT   (1 << 0)

Definition at line 95 of file armv8_dpm.h.

#define DRCR_RESTART   (1 << 1)

Definition at line 96 of file armv8_dpm.h.

#define DSCR_CUR_EL   (0x3 << 8)

Definition at line 48 of file armv8_dpm.h.

#define DSCR_DEBUG_STATUS_MASK   (0x1F << 0)

Definition at line 45 of file armv8_dpm.h.

#define DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */

Definition at line 62 of file armv8_dpm.h.

#define DSCR_DTR_TX_FULL   (0x1 << 29)

Definition at line 61 of file armv8_dpm.h.

#define DSCR_EL_STATUS_MASK   (0xF << 10)

Definition at line 49 of file armv8_dpm.h.

#define DSCR_ERR   (0x1 << 6)
#define DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */

Definition at line 91 of file armv8_dpm.h.

#define DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)

Definition at line 89 of file armv8_dpm.h.

#define DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)

Definition at line 90 of file armv8_dpm.h.

#define DSCR_HDE   (0x1 << 14)
#define DSCR_INTDIS_MASK   (0x3 << 22)

Definition at line 55 of file armv8_dpm.h.

#define DSCR_ITE   (0x1 << 24)
#define DSCR_ITO   (0x1 << 28)

Definition at line 60 of file armv8_dpm.h.

#define DSCR_MA   (0x1 << 20)

Definition at line 53 of file armv8_dpm.h.

Referenced by aarch64_read_apb_ap_memory(), and aarch64_write_apb_ap_memory().

#define DSCR_NON_SECURE   (0x1 << 18)

Definition at line 52 of file armv8_dpm.h.

#define DSCR_PIPE_ADVANCE   (0x1 << 25)

Definition at line 57 of file armv8_dpm.h.

#define DSCR_RTO   (0x1 << 27) /* bit 28 is reserved */

Definition at line 59 of file armv8_dpm.h.

#define DSCR_SDD   (0x1 << 16)

Definition at line 51 of file armv8_dpm.h.

#define DSCR_SYS_ERROR_PEND   (0x1 << 7)

Definition at line 47 of file armv8_dpm.h.

Referenced by aarch64_read_apb_ap_memory(), and aarch64_write_apb_ap_memory().

#define DSCR_TDA   (0x1 << 21)

Definition at line 54 of file armv8_dpm.h.

#define DSCR_TXU   (0x1 << 26)

Definition at line 58 of file armv8_dpm.h.

#define DSCRV8_ENTRY_BKPT   (0x7)

Definition at line 69 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_EXCEPTION_CATCH   (0x37)

Definition at line 78 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_EXT_DEBUG   (0x13)

Definition at line 70 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_HALT_STEP   (0x3B)

Definition at line 79 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_HALT_STEP_EXECLU   (0x1F)

Definition at line 72 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_HALT_STEP_NORMAL   (0x1B)

Definition at line 71 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_HLT   (0x2F)

Definition at line 76 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_NON_DEBUG   (0x2)

Definition at line 67 of file armv8_dpm.h.

#define DSCRV8_ENTRY_OS_UNLOCK   (0x23)

Definition at line 73 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_RESET_CATCH   (0x27)

Definition at line 74 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_RESTARTING   (0x1)

Definition at line 68 of file armv8_dpm.h.

#define DSCRV8_ENTRY_SW_ACCESS_DBG   (0x33)

Definition at line 77 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_ENTRY_WATCHPOINT   (0x2B)

Definition at line 75 of file armv8_dpm.h.

Referenced by armv8_dpm_report_dscr().

#define DSCRV8_HALT_MASK   (0x3C)

Definition at line 80 of file armv8_dpm.h.

#define PRCR_CORENPDRQ   (1 << 0)

Definition at line 114 of file armv8_dpm.h.

Referenced by aarch64_examine_first().

#define PRCR_COREPURQ   (1 << 3)

Definition at line 116 of file armv8_dpm.h.

Referenced by aarch64_examine_first().

#define PRCR_CWRR   (1 << 2)

Definition at line 115 of file armv8_dpm.h.

#define PRSR_DLK   (1 << 6)

Definition at line 106 of file armv8_dpm.h.

#define PRSR_EDAD   (1 << 7)

Definition at line 107 of file armv8_dpm.h.

#define PRSR_EPMAD   (1 << 9)

Definition at line 109 of file armv8_dpm.h.

#define PRSR_HALT   (1 << 4)
#define PRSR_OSLK   (1 << 5)

Definition at line 105 of file armv8_dpm.h.

#define PRSR_PU   (1 << 0)

Definition at line 100 of file armv8_dpm.h.

Referenced by aarch64_examine_first().

#define PRSR_RESET   (1 << 2)

Definition at line 102 of file armv8_dpm.h.

#define PRSR_SDAD   (1 << 8)

Definition at line 108 of file armv8_dpm.h.

#define PRSR_SDR   (1 << 11)
#define PRSR_SPD   (1 << 1)

Definition at line 101 of file armv8_dpm.h.

#define PRSR_SPMAD   (1 << 10)

Definition at line 110 of file armv8_dpm.h.

#define PRSR_SR   (1 << 3)

Definition at line 103 of file armv8_dpm.h.

Function Documentation

enum arm_state armv8_dpm_get_core_state ( struct arm_dpm dpm)

Get core state from EDSCR, without necessity to retrieve CPSR.

Definition at line 50 of file armv8_dpm.c.

References ARM_STATE_AARCH64, ARM_STATE_ARM, arm_dpm::dscr, and arm_dpm::last_el.

Referenced by aarch64_debug_entry(), armv8_dpm_handle_exception(), armv8_dpm_modeswitch(), and dpmv8_exec_opcode().

int armv8_dpm_initialize ( struct arm_dpm dpm)

Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.

Definition at line 1453 of file armv8_dpm.c.

References arm_dpm::arm, dpm_bp::bpwp, dpm_wp::bpwp, arm_dpm::bpwp_disable, arm_dpm::dbp, arm_dpm::dwp, ERROR_OK, LOG_WARNING, arm_dpm::nbp, dpm_bpwp::number, arm_dpm::nwp, arm::target, and target_name().

Referenced by aarch64_dpm_setup().

int armv8_dpm_read_current_registers ( struct arm_dpm dpm)

Read basic registers of the the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).

In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).

Definition at line 705 of file armv8_dpm.c.

References arm::arch_info, arm_dpm::arm, ARM_MODE_ANY, armv8_curel_from_core_mode(), ARMV8_PC, ARMV8_R0, ARMV8_R1, armv8_reg_current(), armv8_set_cpsr(), arm::core_cache, dpmv8_read_reg(), ERROR_OK, arm_dpm::finish, arm_dpm::instr_read_data_r0, arm_dpm::last_el, arm_reg::mode, arm_dpm::prepare, READ_REG_DSPSR, and reg_cache::reg_list.

Referenced by aarch64_debug_entry().

void armv8_dpm_report_wfar ( struct arm_dpm ,
uint64_t  wfar 
)
int armv8_dpm_setup ( struct arm_dpm dpm)

This wraps an implementation of DPM primitives.

Each interface provider supplies a structure like this, which is the glue between upper level code and the lower level hardware access.

It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with support for CPU register access.

This wraps an implementation of DPM primitives.

Initially this only covers the register cache.

Oh, and watchpoints. Yeah.

Definition at line 1373 of file armv8_dpm.c.

References target_type::add_breakpoint, target_type::add_watchpoint, arm_dpm::arm, arm_dpm::arm_reg_current, armv8_build_reg_cache(), armv8_dpm_full_context(), armv8_dpm_read_core_reg(), armv8_dpm_write_core_reg(), armv8_reg_current(), arm_dpm::bpwp_disable, arm::core_cache, arm_dpm::dbp, arm_dpm::didr, arm::dpm, dpmv8_add_breakpoint(), dpmv8_add_watchpoint(), dpmv8_bpwp_disable(), dpmv8_dpm_finish(), dpmv8_dpm_prepare(), dpmv8_instr_cpsr_sync(), dpmv8_instr_execute(), dpmv8_instr_read_data_dcc(), dpmv8_instr_read_data_dcc_64(), dpmv8_instr_read_data_r0(), dpmv8_instr_read_data_r0_64(), dpmv8_instr_write_data_dcc(), dpmv8_instr_write_data_dcc_64(), dpmv8_instr_write_data_r0(), dpmv8_instr_write_data_r0_64(), dpmv8_mcr(), dpmv8_mrc(), dpmv8_remove_breakpoint(), dpmv8_remove_watchpoint(), arm_dpm::dwp, ERROR_FAIL, ERROR_OK, arm_dpm::finish, arm::full_context, arm_dpm::instr_cpsr_sync, arm_dpm::instr_execute, arm_dpm::instr_read_data_dcc, arm_dpm::instr_read_data_dcc_64, arm_dpm::instr_read_data_r0, arm_dpm::instr_read_data_r0_64, arm_dpm::instr_write_data_dcc, arm_dpm::instr_write_data_dcc_64, arm_dpm::instr_write_data_r0, arm_dpm::instr_write_data_r0_64, LOG_INFO, arm::mcr, arm::mrc, arm_dpm::nbp, NULL, arm_dpm::nwp, arm_dpm::prepare, arm::read_core_reg, target_type::remove_breakpoint, target_type::remove_watchpoint, arm::target, target_name(), target::type, and arm::write_core_reg.

Referenced by aarch64_dpm_setup().

int armv8_dpm_write_dirty_registers ( struct arm_dpm dpm,
bool  bpwp 
)

Writes all modified core registers for all processor modes.

In normal operation this is called on exit from halting debug state.

Parameters
dpmrepresents the processor
bpwptrue ensures breakpoints and watchpoints are set, false ensures they are cleared

Definition at line 829 of file armv8_dpm.c.

References target_type::add_breakpoint, reg::arch_info, arm_dpm::arm, ARM_MODE_ANY, armv8_curel_from_core_mode(), armv8_dpm_modeswitch(), ARMV8_PC, ARMV8_xPSR, dpm_bp::bp, dpm_bp::bpwp, dpm_wp::bpwp, arm::core_cache, arm_dpm::dbp, reg::dirty, dpmv8_add_breakpoint(), dpmv8_maybe_update_bpwp(), dpmv8_write_reg(), arm_dpm::dwp, ERROR_OK, arm_dpm::finish, arm_dpm::instr_cpsr_sync, arm_dpm::last_el, arm_reg::mode, arm_dpm::nbp, NULL, reg_cache::num_regs, arm_dpm::nwp, arm_dpm::prepare, reg_cache::reg_list, breakpoint::set, watchpoint::set, arm::target, target::type, reg::valid, and dpm_wp::wp.

Referenced by aarch64_restore_context().