10 #ifndef OPENOCD_TARGET_ARM11_DBGTAP_H
11 #define OPENOCD_TARGET_ARM11_DBGTAP_H
18 void *in_data,
void *out_data,
struct scan_field *field);
30 uint32_t opcode, uint32_t *data,
size_t count);
32 uint32_t opcode, uint32_t *data,
size_t count);
34 uint32_t opcode, uint32_t data);
36 uint32_t opcode, uint32_t *data,
size_t count);
38 uint32_t opcode, uint32_t *data);
40 uint32_t opcode, uint32_t data);
67 uint32_t address, uint32_t *result);
int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Execute an instruction via ITR while handing data into the core via DTR.
int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Load data into core via DTR then move it to r0 then execute one instruction via ITR.
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, tap_state_t state)
int arm11_bpwp_flush(struct arm11_common *arm11)
Flush any pending breakpoint and watchpoint updates.
int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
Read word from address.
int arm11_read_dscr(struct arm11_common *arm11)
Read and save the Debug Status and Control Register (DSCR).
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
Write the Debug Status and Control Register (DSCR)
int arm11_run_instr_data_from_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution...
int arm11_sc7_clear_vbw(struct arm11_common *arm11)
Clear VCR and all breakpoints and watchpoints via scan chain 7.
int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
Set up high-level debug module utilities.
void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
Write JTAG instruction register.
int arm11_run_instr_data_finish(struct arm11_common *arm11)
Cleanup after ITR/DTR operations from the arm11_run_instr...
int arm11_run_instr_data_prepare(struct arm11_common *arm11)
Prepare the stage for ITR/DTR operations from the arm11_run_instr...
int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t *data)
Execute one instruction via ITR then load r0 into DTR and read DTR from core.
void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *in_data, void *out_data, struct scan_field *field)
Code de-clutter: Construct struct scan_field to write out a value.
int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
Write VCR register.
void arm11_dpm_deinit(struct arm11_common *arm11)
int arm11_run_instr_data_to_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
Execute one instruction via ITR.
int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state)
Select and write to Scan Chain Register (SCREG)
int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
Apply reads and writes to scan chain 7.
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
Used with arm11_sc7_run to make a list of read/write commands for scan chain 7.
uint8_t address
Register address mode.
uint32_t value
If write then set this to value to be written.
bool write
Access mode: true for write, false for read.
This structure defines a single scan field in the scan.
1.9.1